[NOTE ] coreboot-25.12-573-ge31d32443e84 Wed Feb 25 10:47:39 UTC 2026 x86_32 bootblock starting (log level: 8)... [DEBUG] CPU: Intel(R) Core(TM) i5-8250U CPU @ 1.60GHz [DEBUG] CPU: ID 806ea, Kabylake Y0, ucode: 000000f5 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 5914 (rev 08) is Kabylake-R ULT [DEBUG] PCH: device id 9d4e (rev 21) is Kabylake-U iHDCP 2.2 Premium [DEBUG] IGD: device id 5917 (rev 07) is Kaby Lake-R ULT GT2 [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route from MISCCFG register [DEBUG] Starting cbfs_boot_device [DEBUG] Starting cbfs_boot_device [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000. [DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 7 [DEBUG] FMAP: area COREBOOT found @ 711000 (9367552 bytes) [INFO ] Booting from COREBOOT region [INFO ] CBFS: mcache @0xfef04e00 built for 15 files, used 0x33c of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x67dc0 size 0xf718 in mcache @0xfef04e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot-25.12-573-ge31d32443e84 Wed Feb 25 10:47:39 UTC 2026 x86_32 romstage starting (log level: 8)... [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] pm1_sts: 8100 pm1_en: 4100 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00400000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00000402 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: e0800200 00001839 [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] PM1_STS: WAK PWRBTN [DEBUG] prev_sleep_state 5 (S5) [DEBUG] Starting cbfs_boot_device [DEBUG] FMAP: area COREBOOT found @ 711000 (9367552 bytes) [INFO ] Booting from COREBOOT region [INFO ] CBFS: Found 'fspm.bin' @0x9cfc0 size 0x63000 in mcache @0xfef05014 [INFO ] POST: 0x34 [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [SPEW ] MRC cache found, size 6248 bytes [SPEW ] bootmode is set to: 2 (boot assuming no config change) [DEBUG] SPD @ 0x50 [INFO ] SPD: module type is DDR4 [INFO ] SPD: module part number is M471A5244CB0-CWE [INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb [INFO ] SPD: device width 16 bits, bus width 64 bits [INFO ] SPD: module size is 4096 MB [DEBUG] SPD @ 0x51 [INFO ] SPD: module type is DDR4 [INFO ] SPD: module part number is M471A5244CB0-CWE [INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb [INFO ] SPD: device width 16 bits, bus width 64 bits [INFO ] SPD: module size is 4096 MB [INFO ] POST: 0x36 [INFO ] POST: 0x92 [INFO ] POST: 0x98 [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x7afff000 254 entries. [DEBUG] IMD: root @ 0x7affec00 62 entries. [DEBUG] Starting cbfs_boot_device [DEBUG] External stage cache: [DEBUG] IMD: root @ 0x7b3ff000 254 entries. [DEBUG] IMD: root @ 0x7b3fec00 62 entries. [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [DEBUG] MRC: 'RW_MRC_CACHE' does not need update. [DEBUG] 2 DIMMs found [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x7b000000 0x800000 [DEBUG] Subregion 0: 0x7b000000 0x200000 [DEBUG] Subregion 1: 0x7b200000 0x200000 [DEBUG] Subregion 2: 0x7b400000 0x400000 [DEBUG] top_of_ram = 0x7b000000 [DEBUG] Normal boot [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/postcar' @0x124040 size 0x5ce4 in mcache @0xfef05088 [DEBUG] Loading module at 0x7abce000 with entry 0x7abce031. filesize: 0x5948 memsize: 0xbc98 [DEBUG] Processing 215 relocs. Offset value of 0x78bce000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms [NOTE ] coreboot-25.12-573-ge31d32443e84 Wed Feb 25 10:47:39 UTC 2026 x86_32 postcar starting (log level: 8)... [DEBUG] Normal boot [DEBUG] Starting cbfs_boot_device [DEBUG] FMAP: area COREBOOT found @ 711000 (9367552 bytes) [INFO ] Booting from COREBOOT region [INFO ] CBFS: Found 'fallback/ramstage' @0x77540 size 0x1f754 in mcache @0x7abdd0ec [DEBUG] Loading module at 0x7aa7d000 with entry 0x7aa7d000. filesize: 0x3f818 memsize: 0x14ff10 [DEBUG] Processing 4814 relocs. Offset value of 0x76a7d000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms [NOTE ] coreboot-25.12-573-ge31d32443e84 Wed Feb 25 10:47:39 UTC 2026 x86_32 ramstage starting (log level: 8)... [INFO ] POST: 0x39 [INFO ] POST: 0x6f [DEBUG] Normal boot [INFO ] POST: 0x70 [DEBUG] microcode: sig=0x806ea pf=0x80 revision=0xf5 [DEBUG] Starting cbfs_boot_device [DEBUG] FMAP: area COREBOOT found @ 711000 (9367552 bytes) [INFO ] Booting from COREBOOT region [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x67c00 in mcache @0x7abdd02c [DEBUG] Skip microcode update [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fsps.bin' @0x100000 size 0x23ff2 in mcache @0x7abdd254 [DEBUG] Detected 4 core, 8 thread CPU. [DEBUG] Setting up SMI for CPU [DEBUG] IED base = 0x7b400000 [DEBUG] IED size = 0x00400000 [INFO ] Will perform SMM setup. [INFO ] CPU: Intel(R) Core(TM) i5-8250U CPU @ 1.60GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] CPU: APIC: 02 enabled [DEBUG] CPU: APIC: 03 enabled [DEBUG] CPU: APIC: 04 enabled [DEBUG] CPU: APIC: 05 enabled [DEBUG] CPU: APIC: 06 enabled [DEBUG] CPU: APIC: 07 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 7 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [SPEW ] APs are ready after 0us [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [SPEW ] APs are ready after 0us [INFO ] LAPIC 0x1 in XAPIC mode. [INFO ] AP: slot 2 apic_id 1, MCU rev: 0x000000f5 [INFO ] LAPIC 0x4 in XAPIC mode. [INFO ] LAPIC 0x5 in XAPIC mode. [INFO ] AP: slot 1 apic_id 4, MCU rev: 0x000000f5 [INFO ] AP: slot 3 apic_id 5, MCU rev: 0x000000f5 [INFO ] LAPIC 0x6 in XAPIC mode. [INFO ] LAPIC 0x7 in XAPIC mode. [INFO ] AP: slot 4 apic_id 6, MCU rev: 0x000000f5 [INFO ] AP: slot 6 apic_id 7, MCU rev: 0x000000f5 [INFO ] LAPIC 0x2 in XAPIC mode. [INFO ] LAPIC 0x3 in XAPIC mode. [INFO ] AP: slot 7 apic_id 2, MCU rev: 0x000000f5 [INFO ] AP: slot 5 apic_id 3, MCU rev: 0x000000f5 [SPEW ] APs are ready after 100us [SPEW ] smm_setup_relocation_handler: enter [SPEW ] smm_setup_relocation_handler: exit [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x7b004000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7aa9ea82 [DEBUG] Installing permanent SMM handler to 0x7b000000 [DEBUG] HANDLER [0x7b1ff000-0x7b1ffd9f] [DEBUG] CPU 0 [DEBUG] ss0 [0x7b1fec00-0x7b1fefff] [DEBUG] stub0 [0x7b1f7000-0x7b1f719f] [DEBUG] CPU 1 [DEBUG] ss1 [0x7b1fe800-0x7b1febff] [DEBUG] stub1 [0x7b1f6c00-0x7b1f6d9f] [DEBUG] CPU 2 [DEBUG] ss2 [0x7b1fe400-0x7b1fe7ff] [DEBUG] stub2 [0x7b1f6800-0x7b1f699f] [DEBUG] CPU 3 [DEBUG] ss3 [0x7b1fe000-0x7b1fe3ff] [DEBUG] stub3 [0x7b1f6400-0x7b1f659f] [DEBUG] CPU 4 [DEBUG] ss4 [0x7b1fdc00-0x7b1fdfff] [DEBUG] stub4 [0x7b1f6000-0x7b1f619f] [DEBUG] CPU 5 [DEBUG] ss5 [0x7b1fd800-0x7b1fdbff] [DEBUG] stub5 [0x7b1f5c00-0x7b1f5d9f] [DEBUG] CPU 6 [DEBUG] ss6 [0x7b1fd400-0x7b1fd7ff] [DEBUG] stub6 [0x7b1f5800-0x7b1f599f] [DEBUG] CPU 7 [DEBUG] ss7 [0x7b1fd000-0x7b1fd3ff] [DEBUG] stub7 [0x7b1f5400-0x7b1f559f] [DEBUG] stacks [0x7b000000-0x7b003fff] [DEBUG] Loading module at 0x7b1ff000 with entry 0x7b1ff027. filesize: 0xd90 memsize: 0xda0 [DEBUG] Processing 81 relocs. Offset value of 0x7b1ff000 [DEBUG] Loading module at 0x7b1f7000 with entry 0x7b1f7000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x7b1f7000 [DEBUG] smm_module_setup_stub: stack_top = 0x7b004000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000 [DEBUG] SMM Module: placing smm entry code at 7b1f6c00, cpu # 0x1 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f6c00 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f6800, cpu # 0x2 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f6800 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f6400, cpu # 0x3 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f6400 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f6000, cpu # 0x4 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f6000 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f5c00, cpu # 0x5 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f5c00 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f5800, cpu # 0x6 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f5800 0x1a0 bytes [DEBUG] SMM Module: placing smm entry code at 7b1f5400, cpu # 0x7 [SPEW ] smm_place_entry_code: copying from 7b1f7000 to 7b1f5400 0x1a0 bytes [DEBUG] SMM Module: stub loaded at 7b1f7000. Will call 0x7b1ff027 [DEBUG] Clearing SMI status registers [DEBUG] GPE0 STD STS: BATLOW HOTPLUG [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ef000, cpu = 0 [DEBUG] In relocation handler: CPU 0 [DEBUG] New SMBASE=0x7b1ef000 IEDBASE=0x7b400000 [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ee800, cpu = 2 [DEBUG] In relocation handler: CPU 2 [DEBUG] New SMBASE=0x7b1ee800 IEDBASE=0x7b400000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ee000, cpu = 4 [DEBUG] In relocation handler: CPU 4 [DEBUG] New SMBASE=0x7b1ee000 IEDBASE=0x7b400000 [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ed800, cpu = 6 [DEBUG] In relocation handler: CPU 6 [DEBUG] New SMBASE=0x7b1ed800 IEDBASE=0x7b400000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ee400, cpu = 3 [DEBUG] In relocation handler: CPU 3 [DEBUG] New SMBASE=0x7b1ee400 IEDBASE=0x7b400000 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1eec00, cpu = 1 [DEBUG] In relocation handler: CPU 1 [DEBUG] New SMBASE=0x7b1eec00 IEDBASE=0x7b400000 [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ed400, cpu = 7 [DEBUG] In relocation handler: CPU 7 [DEBUG] New SMBASE=0x7b1ed400 IEDBASE=0x7b400000 [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1edc00, cpu = 5 [DEBUG] In relocation handler: CPU 5 [DEBUG] New SMBASE=0x7b1edc00 IEDBASE=0x7b400000 [DEBUG] Relocation complete. [SPEW ] APs are ready after 1100us [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] Clearing out pending MCEs [DEBUG] cpu: energy policy set to 6 [INFO ] Turbo is available but hidden [INFO ] Turbo is available and visible [DEBUG] Skip microcode update [INFO ] CPU #0 initialized [INFO ] Initializing CPU #2 [INFO ] Initializing CPU #3 [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [INFO ] Initializing CPU #7 [INFO ] Initializing CPU #5 [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [INFO ] Initializing CPU #1 [DEBUG] Clearing out pending MCEs [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [INFO ] Initializing CPU #6 [INFO ] Initializing CPU #4 [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] CPU: vendor Intel device 806ea [DEBUG] CPU: family 06, model 8e, stepping 0a [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [DEBUG] Skip microcode update [INFO ] CPU #7 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] Skip microcode update [INFO ] CPU #2 initialized [DEBUG] Skip microcode update [INFO ] CPU #5 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] Skip microcode update [INFO ] CPU #3 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] Skip microcode update [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #1 initialized [DEBUG] Skip microcode update [INFO ] CPU #6 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] Skip microcode update [INFO ] CPU #4 initialized [SPEW ] APs are ready after 100us [INFO ] bsp_do_flight_plan done after 1 msecs. [DEBUG] CPU: frequency set to 3400 MHz [DEBUG] Enabling SMIs. [DEBUG] Locking SMM. [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 23 / 0 ms [DEBUG] IA32_FEATURE_CONTROL status: locked [INFO ] POST: 0x71 [DEBUG] iGPU present - GFXVT_BASE_ADDRESS set [INFO ] POST: 0x93 [INFO ] FSPS, status=0x00000000 [INFO ] POST: 0x99 [INFO ] ITSS IRQ Polarities Before: [INFO ] IPC0: 0x00ff4000 [INFO ] IPC1: 0x00000007 [INFO ] IPC2: 0x00000000 [INFO ] IPC3: 0x00000000 [INFO ] ITSS IRQ Polarities After: [INFO ] IPC0: 0x00ff4000 [INFO ] IPC1: 0x00000007 [INFO ] IPC2: 0x00000000 [INFO ] IPC3: 0x00000000 [INFO ] Found PCIe Root Port #9 at PCI: 00:1d.0. [INFO ] Found PCIe Root Port #11 at PCI: 00:1d.2. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:00:1c.0) which was enabled in devicetree, removing and disabling. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:00:1c.4) which was enabled in devicetree, removing and disabling. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:00:1c.6) which was enabled in devicetree, removing and disabling. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 145 / 0 ms [INFO ] POST: 0x72 [INFO ] Enumerating buses... [SPEW ] Show all devs... Before device enumeration. [SPEW ] Root Device: enabled 1 [SPEW ] CPU_CLUSTER: 0: enabled 1 [SPEW ] DOMAIN: 00000000: enabled 1 [SPEW ] GPIO: 0: enabled 1 [SPEW ] PCI: 00:00:00.0: enabled 1 [SPEW ] PCI: 00:00:01.0: enabled 0 [SPEW ] PCI: 00:00:01.1: enabled 0 [SPEW ] PCI: 00:00:01.2: enabled 0 [SPEW ] PCI: 00:00:02.0: enabled 1 [SPEW ] PCI: 00:00:04.0: enabled 1 [SPEW ] PCI: 00:00:05.0: enabled 0 [SPEW ] PCI: 00:00:07.0: enabled 0 [SPEW ] PCI: 00:00:08.0: enabled 0 [SPEW ] PCI: 00:00:13.0: enabled 0 [SPEW ] PCI: 00:00:14.0: enabled 1 [SPEW ] PCI: 00:00:14.1: enabled 0 [SPEW ] PCI: 00:00:14.2: enabled 1 [SPEW ] PCI: 00:00:14.3: enabled 0 [SPEW ] PCI: 00:00:15.0: enabled 0 [SPEW ] PCI: 00:00:15.1: enabled 0 [SPEW ] PCI: 00:00:15.2: enabled 0 [SPEW ] PCI: 00:00:15.3: enabled 0 [SPEW ] PCI: 00:00:16.0: enabled 0 [SPEW ] PCI: 00:00:16.1: enabled 0 [SPEW ] PCI: 00:00:16.2: enabled 0 [SPEW ] PCI: 00:00:16.3: enabled 0 [SPEW ] PCI: 00:00:16.4: enabled 0 [SPEW ] PCI: 00:00:17.0: enabled 1 [SPEW ] PCI: 00:00:19.0: enabled 0 [SPEW ] PCI: 00:00:19.1: enabled 0 [SPEW ] PCI: 00:00:19.2: enabled 0 [SPEW ] PCI: 00:00:1b.0: enabled 0 [SPEW ] PCI: 00:00:1b.1: enabled 0 [SPEW ] PCI: 00:00:1b.2: enabled 0 [SPEW ] PCI: 00:00:1b.3: enabled 0 [SPEW ] PCI: 00:00:1b.4: enabled 0 [SPEW ] PCI: 00:00:1b.5: enabled 0 [SPEW ] PCI: 00:00:1b.6: enabled 0 [SPEW ] PCI: 00:00:1b.7: enabled 0 [SPEW ] PCI: 00:00:1c.0: enabled 0 [SPEW ] PCI: 00:00:1c.1: enabled 0 [SPEW ] PCI: 00:00:1c.2: enabled 0 [SPEW ] PCI: 00:00:1c.3: enabled 0 [SPEW ] PCI: 00:00:1c.4: enabled 0 [SPEW ] PCI: 00:00:1c.5: enabled 0 [SPEW ] PCI: 00:00:1c.6: enabled 0 [SPEW ] PCI: 00:00:1c.7: enabled 0 [SPEW ] PCI: 00:00:1d.0: enabled 1 [SPEW ] PCI: 00:00:1d.1: enabled 0 [SPEW ] PCI: 00:00:1d.2: enabled 1 [SPEW ] PCI: 00:00:1d.3: enabled 0 [SPEW ] PCI: 00:00:1d.4: enabled 0 [SPEW ] PCI: 00:00:1d.5: enabled 0 [SPEW ] PCI: 00:00:1d.6: enabled 0 [SPEW ] PCI: 00:00:1d.7: enabled 0 [SPEW ] PCI: 00:00:1e.0: enabled 0 [SPEW ] PCI: 00:00:1e.1: enabled 0 [SPEW ] PCI: 00:00:1e.2: enabled 0 [SPEW ] PCI: 00:00:1e.3: enabled 0 [SPEW ] PCI: 00:00:1e.4: enabled 0 [SPEW ] PCI: 00:00:1e.5: enabled 0 [SPEW ] PCI: 00:00:1e.6: enabled 0 [SPEW ] PCI: 00:00:1f.0: enabled 1 [SPEW ] PCI: 00:00:1f.1: enabled 1 [SPEW ] PCI: 00:00:1f.2: enabled 1 [SPEW ] PCI: 00:00:1f.3: enabled 1 [SPEW ] PCI: 00:00:1f.4: enabled 0 [SPEW ] PCI: 00:00:1f.5: enabled 0 [SPEW ] PCI: 00:00:1f.6: enabled 1 [SPEW ] PCI: 00:00:1f.7: enabled 0 [SPEW ] USB0 port 0: enabled 0 [SPEW ] GENERIC: 0.0: enabled 1 [SPEW ] PNP: 00ff.1: enabled 1 [SPEW ] PNP: 00ff.2: enabled 1 [SPEW ] PNP: 0c31.0: enabled 1 [SPEW ] USB2 port 0: enabled 0 [SPEW ] USB2 port 1: enabled 0 [SPEW ] USB2 port 2: enabled 0 [SPEW ] USB2 port 3: enabled 0 [SPEW ] USB2 port 4: enabled 0 [SPEW ] USB2 port 5: enabled 0 [SPEW ] USB2 port 6: enabled 0 [SPEW ] USB2 port 7: enabled 0 [SPEW ] USB2 port 8: enabled 0 [SPEW ] USB2 port 9: enabled 0 [SPEW ] USB3 port 0: enabled 0 [SPEW ] USB3 port 1: enabled 0 [SPEW ] USB3 port 2: enabled 0 [SPEW ] USB3 port 3: enabled 0 [SPEW ] USB3 port 4: enabled 0 [SPEW ] USB3 port 5: enabled 0 [SPEW ] APIC: 00: enabled 1 [SPEW ] APIC: 04: enabled 1 [SPEW ] APIC: 01: enabled 1 [SPEW ] APIC: 05: enabled 1 [SPEW ] APIC: 06: enabled 1 [SPEW ] APIC: 03: enabled 1 [SPEW ] APIC: 07: enabled 1 [SPEW ] APIC: 02: enabled 1 [SPEW ] Compare with tree... [SPEW ] Root Device: enabled 1 [SPEW ] CPU_CLUSTER: 0: enabled 1 [SPEW ] APIC: 00: enabled 1 [SPEW ] APIC: 04: enabled 1 [SPEW ] APIC: 01: enabled 1 [SPEW ] APIC: 05: enabled 1 [SPEW ] APIC: 06: enabled 1 [SPEW ] APIC: 03: enabled 1 [SPEW ] APIC: 07: enabled 1 [SPEW ] APIC: 02: enabled 1 [SPEW ] DOMAIN: 00000000: enabled 1 [SPEW ] GPIO: 0: enabled 1 [SPEW ] PCI: 00:00:00.0: enabled 1 [SPEW ] PCI: 00:00:01.0: enabled 0 [SPEW ] PCI: 00:00:01.1: enabled 0 [SPEW ] PCI: 00:00:01.2: enabled 0 [SPEW ] PCI: 00:00:02.0: enabled 1 [SPEW ] PCI: 00:00:04.0: enabled 1 [SPEW ] PCI: 00:00:05.0: enabled 0 [SPEW ] PCI: 00:00:07.0: enabled 0 [SPEW ] PCI: 00:00:08.0: enabled 0 [SPEW ] PCI: 00:00:13.0: enabled 0 [SPEW ] PCI: 00:00:14.0: enabled 1 [SPEW ] USB0 port 0: enabled 0 [SPEW ] USB2 port 0: enabled 0 [SPEW ] USB2 port 1: enabled 0 [SPEW ] USB2 port 2: enabled 0 [SPEW ] USB2 port 3: enabled 0 [SPEW ] USB2 port 4: enabled 0 [SPEW ] USB2 port 5: enabled 0 [SPEW ] USB2 port 6: enabled 0 [SPEW ] USB2 port 7: enabled 0 [SPEW ] USB2 port 8: enabled 0 [SPEW ] USB2 port 9: enabled 0 [SPEW ] USB3 port 0: enabled 0 [SPEW ] USB3 port 1: enabled 0 [SPEW ] USB3 port 2: enabled 0 [SPEW ] USB3 port 3: enabled 0 [SPEW ] USB3 port 4: enabled 0 [SPEW ] USB3 port 5: enabled 0 [SPEW ] PCI: 00:00:14.1: enabled 0 [SPEW ] PCI: 00:00:14.2: enabled 1 [SPEW ] PCI: 00:00:14.3: enabled 0 [SPEW ] PCI: 00:00:15.0: enabled 0 [SPEW ] PCI: 00:00:15.1: enabled 0 [SPEW ] PCI: 00:00:15.2: enabled 0 [SPEW ] PCI: 00:00:15.3: enabled 0 [SPEW ] PCI: 00:00:16.0: enabled 0 [SPEW ] PCI: 00:00:16.1: enabled 0 [SPEW ] PCI: 00:00:16.2: enabled 0 [SPEW ] PCI: 00:00:16.3: enabled 0 [SPEW ] PCI: 00:00:16.4: enabled 0 [SPEW ] PCI: 00:00:17.0: enabled 1 [SPEW ] PCI: 00:00:19.0: enabled 0 [SPEW ] PCI: 00:00:19.1: enabled 0 [SPEW ] PCI: 00:00:19.2: enabled 0 [SPEW ] PCI: 00:00:1b.0: enabled 0 [SPEW ] PCI: 00:00:1b.1: enabled 0 [SPEW ] PCI: 00:00:1b.2: enabled 0 [SPEW ] PCI: 00:00:1b.3: enabled 0 [SPEW ] PCI: 00:00:1b.4: enabled 0 [SPEW ] PCI: 00:00:1b.5: enabled 0 [SPEW ] PCI: 00:00:1b.6: enabled 0 [SPEW ] PCI: 00:00:1b.7: enabled 0 [SPEW ] PCI: 00:00:1d.0: enabled 1 [SPEW ] PCI: 00:00:1d.2: enabled 1 [SPEW ] PCI: 00:00:1d.4: enabled 0 [SPEW ] PCI: 00:00:1d.5: enabled 0 [SPEW ] PCI: 00:00:1d.6: enabled 0 [SPEW ] PCI: 00:00:1d.7: enabled 0 [SPEW ] PCI: 00:00:1e.0: enabled 0 [SPEW ] PCI: 00:00:1e.1: enabled 0 [SPEW ] PCI: 00:00:1e.2: enabled 0 [SPEW ] PCI: 00:00:1e.3: enabled 0 [SPEW ] PCI: 00:00:1e.4: enabled 0 [SPEW ] PCI: 00:00:1e.5: enabled 0 [SPEW ] PCI: 00:00:1e.6: enabled 0 [SPEW ] PCI: 00:00:1f.0: enabled 1 [SPEW ] PNP: 00ff.1: enabled 1 [SPEW ] PNP: 00ff.2: enabled 1 [SPEW ] PNP: 0c31.0: enabled 1 [SPEW ] PCI: 00:00:1f.1: enabled 1 [SPEW ] PCI: 00:00:1f.2: enabled 1 [SPEW ] PCI: 00:00:1f.3: enabled 1 [SPEW ] PCI: 00:00:1f.4: enabled 0 [SPEW ] PCI: 00:00:1f.5: enabled 0 [SPEW ] PCI: 00:00:1f.6: enabled 1 [SPEW ] PCI: 00:00:1f.7: enabled 0 [DEBUG] Discrete GPU not present [DEBUG] Root Device scanning... [SPEW ] scan_static_bus for Root Device [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [INFO ] POST: 0x24 [DEBUG] PCI: 00:00:00.0 [8086/5914] enabled [DEBUG] PCI: 00:00:02.0 [8086/5917] enabled [DEBUG] PCI: 00:00:04.0 [8086/1903] enabled [DEBUG] PCI: 00:00:14.0 [8086/9d2f] enabled [DEBUG] PCI: 00:00:14.2 [8086/9d31] enabled [INFO ] PCI: Static device PCI: 00:00:17.0 not found, disabling it. [DEBUG] PCI: 00:00:1d.0 [8086/9d18] enabled [DEBUG] PCI: 00:00:1d.2 [8086/9d1a] enabled [DEBUG] PCI: 00:00:1f.0 [8086/9d4e] enabled [DEBUG] PCI: 00:00:1f.1 [8086/9d20] enabled [DEBUG] PCI: 00:00:1f.2 [8086/9d21] enabled [DEBUG] PCI: 00:00:1f.3 [8086/9d71] enabled [DEBUG] PCI: 00:00:1f.6 [8086/15d8] enabled [DEBUG] GPIO: 0 enabled [DEBUG] PCI: 00:00:02.0 scanning... [SPEW ] scan_generic_bus for PCI: 00:00:02.0 [SPEW ] scan_generic_bus for PCI: 00:00:02.0 done [DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs [DEBUG] PCI: 00:00:14.0 scanning... [SPEW ] scan_static_bus for PCI: 00:00:14.0 [DEBUG] USB0 port 0 disabled [SPEW ] scan_static_bus for PCI: 00:00:14.0 done [DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs [DEBUG] PCI: 00:00:1d.0 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:00:1d.0 [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [INFO ] PCI: 00:00:1d.0: ASPM enabled L0s and L1 (no endpoint) [INFO ] PCI: 00:00:1d.0: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1d.0 finished in 0 msecs [DEBUG] PCI: 00:00:1d.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:00:1d.2 [DEBUG] PCI: pci_scan_bus for segment group 00 bus 02 [INFO ] POST: 0x24 [DEBUG] PCI: 00:02:00.0 [144d/a809] enabled [INFO ] POST: 0x25 [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] L1 Sub-State supported from root port 29 [INFO ] L1 Sub-State Support = 0xf [INFO ] CommonModeRestoreTime = 0x28 [INFO ] Power On Value = 0x16, Power On Scale = 0x0 [INFO ] ASPM: Enabled L1 [INFO ] PCI: 00:02:00.0: Enabled LTR [INFO ] PCI: 00:02:00.0: Programmed LTR max latencies [INFO ] PCI: 00:00:1d.2: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1d.2 finished in 0 msecs [DEBUG] PCI: 00:00:1f.0 scanning... [SPEW ] scan_static_bus for PCI: 00:00:1f.0 [INFO ] PMH7: ID 06 Revision 00 [DEBUG] PNP: 00ff.1 enabled [SPEW ] Clearing EC output queue... [SPEW ] EC output queue has been cleared. [SPEW ] Data from EC: 0x4e [SPEW ] Data from EC: 0x32 [SPEW ] Data from EC: 0x37 [SPEW ] Data from EC: 0x48 [SPEW ] Data from EC: 0x54 [SPEW ] Data from EC: 0x32 [SPEW ] Data from EC: 0x36 [SPEW ] Data from EC: 0x57 [SPEW ] Data from EC: 0x24 [SPEW ] Data from EC: 0x03 [SPEW ] Data from EC: 0x50 [SPEW ] Data from EC: 0x11 [INFO ] H8: EC Firmware ID N27HT26W-3.36, Version 5.01B [SPEW ] Data from EC: 0x00 [SPEW ] Data from EC: 0x40 [SPEW ] Data from EC: 0x10 [SPEW ] Data from EC: 0x60 [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed [SPEW ] Data from EC: 0x70 [SPEW ] Data from EC: 0x20 [SPEW ] Data from EC: 0xa6 [SPEW ] Data from EC: 0x10 [SPEW ] Data from EC: 0xa6 [SPEW ] Data from EC: 0x70 [DEBUG] PNP: 00ff.2 enabled [DEBUG] PNP: 0c31.0 enabled [SPEW ] scan_static_bus for PCI: 00:00:1f.0 done [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 4 msecs [DEBUG] PCI: 00:00:1f.2 scanning... [SPEW ] scan_static_bus for PCI: 00:00:1f.2 [SPEW ] scan_static_bus for PCI: 00:00:1f.2 done [DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs [DEBUG] PCI: 00:00:1f.3 scanning... [SPEW ] scan_static_bus for PCI: 00:00:1f.3 [SPEW ] scan_static_bus for PCI: 00:00:1f.3 done [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs [INFO ] POST: 0x25 [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 5 msecs [SPEW ] scan_static_bus for Root Device done [DEBUG] scan_bus: bus Root Device finished in 5 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms [INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE' [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'. [INFO ] POST: 0x73 [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [SPEW ] Root Device read_resources segment group 0 bus 0 [SPEW ] CPU_CLUSTER: 0 read_resources segment group 0 bus 0 [SPEW ] CPU_CLUSTER: 0 read_resources segment group 0 bus 0 done [SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 [DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x0, base: 0xe0000000, size: 0x10000000 [DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x1, base: 0xfed10000, size: 0x8000 [DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x2, base: 0xfed18000, size: 0x1000 [DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x3, base: 0xfed19000, size: 0x1000 [DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x4, base: 0xfed84000, size: 0x1000 [DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x5, base: 0xfed80000, size: 0x4000 [DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x6, base: 0xfed90000, size: 0x1000 [DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x7, base: 0xfed91000, size: 0x1000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x8, base: 0x0, size: 0xa0000 [SPEW ] dev: PCI: 00:00:00.0, index: 0x9, base: 0xc0000, size: 0x7af40000 [SPEW ] dev: PCI: 00:00:00.0, index: 0xa, base: 0x7b000000, size: 0x5000000 [INFO ] Available memory above 4GB: 6144M [SPEW ] dev: PCI: 00:00:00.0, index: 0xb, base: 0x100000000, size: 0x180000000 [SPEW ] dev: PCI: 00:00:00.0, index: 0xc, base: 0xa0000, size: 0x20000 [SPEW ] dev: PCI: 00:00:00.0, index: 0xd, base: 0xc0000, size: 0x40000 [SPEW ] PCI: 00:00:14.0 read_resources segment group 0 bus 0 [SPEW ] PCI: 00:00:14.0 read_resources segment group 0 bus 0 done [SPEW ] PCI: 00:00:1d.0 read_resources segment group 0 bus 1 [SPEW ] PCI: 00:00:1d.0 read_resources segment group 0 bus 1 done [SPEW ] PCI: 00:00:1d.2 read_resources segment group 0 bus 2 [SPEW ] PCI: 00:00:1d.2 read_resources segment group 0 bus 2 done [SPEW ] PCI: 00:00:1f.0 read_resources segment group 0 bus 0 [SPEW ] dev: PNP: 00ff.1, index: 0x15e0, base: 0x15e0, size: 0x10 [SPEW ] dev: PNP: 00ff.2, index: 0x60, base: 0x60, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x64, base: 0x64, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x62, base: 0x62, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x66, base: 0x66, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x1600, base: 0x1600, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x1604, base: 0x1604, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x1602, base: 0x1602, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x1606, base: 0x1606, size: 0x1 [SPEW ] dev: PNP: 00ff.2, index: 0x1610, base: 0x1610, size: 0x10 [SPEW ] PCI: 00:00:1f.0 read_resources segment group 0 bus 0 done [SPEW ] dev: PCI: 00:00:1f.1, index: 0x10, base: 0xfd000000, size: 0x1000000 [SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done [SPEW ] Root Device read_resources segment group 0 bus 0 done [INFO ] Done reading resources. [SPEW ] Show resources in subtree (Root Device)...After reading. [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 [DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00 [DEBUG] APIC: 00 [DEBUG] APIC: 04 [DEBUG] APIC: 01 [DEBUG] APIC: 05 [DEBUG] APIC: 06 [DEBUG] APIC: 03 [DEBUG] APIC: 07 [DEBUG] APIC: 02 [DEBUG] DOMAIN: 00000000 child on link 0 GPIO: 0 [SPEW ] DOMAIN: 00000000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 [SPEW ] DOMAIN: 00000000 resource base 7b000000 size 0 align 0 gran 0 limit dfffffff flags 40040200 index 10000100 [SPEW ] DOMAIN: 00000000 resource base 100000000 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000200 [DEBUG] GPIO: 0 [DEBUG] PCI: 00:00:00.0 [SPEW ] PCI: 00:00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 [SPEW ] PCI: 00:00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 [SPEW ] PCI: 00:00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 [SPEW ] PCI: 00:00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 [SPEW ] PCI: 00:00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 [SPEW ] PCI: 00:00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 [SPEW ] PCI: 00:00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 [SPEW ] PCI: 00:00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 [SPEW ] PCI: 00:00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 8 [SPEW ] PCI: 00:00:00.0 resource base c0000 size 7af40000 align 0 gran 0 limit 0 flags e0004200 index 9 [SPEW ] PCI: 00:00:00.0 resource base 7b000000 size 5000000 align 0 gran 0 limit 0 flags f0000200 index a [SPEW ] PCI: 00:00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index b [SPEW ] PCI: 00:00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c [SPEW ] PCI: 00:00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d [DEBUG] PCI: 00:00:01.0 [DEBUG] PCI: 00:00:01.1 [DEBUG] PCI: 00:00:01.2 [DEBUG] PCI: 00:00:02.0 [SPEW ] PCI: 00:00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 [SPEW ] PCI: 00:00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 [SPEW ] PCI: 00:00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 [DEBUG] PCI: 00:00:04.0 [SPEW ] PCI: 00:00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 [DEBUG] PCI: 00:00:05.0 [DEBUG] PCI: 00:00:07.0 [DEBUG] PCI: 00:00:08.0 [DEBUG] PCI: 00:00:13.0 [DEBUG] PCI: 00:00:14.0 child on link 0 USB0 port 0 [SPEW ] PCI: 00:00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 [DEBUG] USB0 port 0 child on link 0 USB2 port 0 [DEBUG] USB2 port 0 [DEBUG] USB2 port 1 [DEBUG] USB2 port 2 [DEBUG] USB2 port 3 [DEBUG] USB2 port 4 [DEBUG] USB2 port 5 [DEBUG] USB2 port 6 [DEBUG] USB2 port 7 [DEBUG] USB2 port 8 [DEBUG] USB2 port 9 [DEBUG] USB3 port 0 [DEBUG] USB3 port 1 [DEBUG] USB3 port 2 [DEBUG] USB3 port 3 [DEBUG] USB3 port 4 [DEBUG] USB3 port 5 [DEBUG] PCI: 00:00:14.1 [DEBUG] PCI: 00:00:14.2 [SPEW ] PCI: 00:00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 [DEBUG] PCI: 00:00:14.3 [DEBUG] PCI: 00:00:15.0 [DEBUG] PCI: 00:00:15.1 [DEBUG] PCI: 00:00:15.2 [DEBUG] PCI: 00:00:15.3 [DEBUG] PCI: 00:00:16.0 [DEBUG] PCI: 00:00:16.1 [DEBUG] PCI: 00:00:16.2 [DEBUG] PCI: 00:00:16.3 [DEBUG] PCI: 00:00:16.4 [DEBUG] PCI: 00:00:17.0 [DEBUG] PCI: 00:00:19.0 [DEBUG] PCI: 00:00:19.1 [DEBUG] PCI: 00:00:19.2 [DEBUG] PCI: 00:00:1b.0 [DEBUG] PCI: 00:00:1b.1 [DEBUG] PCI: 00:00:1b.2 [DEBUG] PCI: 00:00:1b.3 [DEBUG] PCI: 00:00:1b.4 [DEBUG] PCI: 00:00:1b.5 [DEBUG] PCI: 00:00:1b.6 [DEBUG] PCI: 00:00:1b.7 [DEBUG] PCI: 00:00:1d.0 [SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c [SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 [SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 [DEBUG] PCI: 00:00:1d.2 child on link 0 PCI: 00:02:00.0 [SPEW ] PCI: 00:00:1d.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c [SPEW ] PCI: 00:00:1d.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 [SPEW ] PCI: 00:00:1d.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 [DEBUG] PCI: 00:02:00.0 [SPEW ] PCI: 00:02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 [DEBUG] PCI: 00:00:1d.4 [DEBUG] PCI: 00:00:1d.5 [DEBUG] PCI: 00:00:1d.6 [DEBUG] PCI: 00:00:1d.7 [DEBUG] PCI: 00:00:1e.0 [DEBUG] PCI: 00:00:1e.1 [DEBUG] PCI: 00:00:1e.2 [DEBUG] PCI: 00:00:1e.3 [DEBUG] PCI: 00:00:1e.4 [DEBUG] PCI: 00:00:1e.5 [DEBUG] PCI: 00:00:1e.6 [DEBUG] PCI: 00:00:1f.0 child on link 0 PNP: 00ff.1 [SPEW ] PCI: 00:00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 [SPEW ] PCI: 00:00:1f.0 resource base 1600 size 80 align 0 gran 0 limit 0 flags c0000100 index 84 [SPEW ] PCI: 00:00:1f.0 resource base 15e0 size 10 align 0 gran 0 limit 0 flags c0000100 index 88 [SPEW ] PCI: 00:00:1f.0 resource base 80 size 10 align 0 gran 0 limit 0 flags c0000100 index 8c [DEBUG] PNP: 00ff.1 [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 0 gran 0 limit 0 flags c0000100 index 15e0 [DEBUG] PNP: 00ff.2 [SPEW ] PNP: 00ff.2 resource base 60 size 1 align 0 gran 0 limit 0 flags c0000100 index 60 [SPEW ] PNP: 00ff.2 resource base 62 size 1 align 0 gran 0 limit 0 flags c0000100 index 62 [SPEW ] PNP: 00ff.2 resource base 64 size 1 align 0 gran 0 limit 0 flags c0000100 index 64 [SPEW ] PNP: 00ff.2 resource base 66 size 1 align 0 gran 0 limit 0 flags c0000100 index 66 [SPEW ] PNP: 00ff.2 resource base 1600 size 1 align 0 gran 0 limit 0 flags c0000100 index 1600 [SPEW ] PNP: 00ff.2 resource base 1604 size 1 align 0 gran 0 limit 0 flags c0000100 index 1604 [SPEW ] PNP: 00ff.2 resource base 1602 size 1 align 0 gran 0 limit 0 flags c0000100 index 1602 [SPEW ] PNP: 00ff.2 resource base 1606 size 1 align 0 gran 0 limit 0 flags c0000100 index 1606 [SPEW ] PNP: 00ff.2 resource base 1610 size 10 align 0 gran 0 limit 0 flags c0000100 index 1610 [DEBUG] PNP: 0c31.0 [SPEW ] PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 [DEBUG] PCI: 00:00:1f.1 [SPEW ] PCI: 00:00:1f.1 resource base fd000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 [DEBUG] PCI: 00:00:1f.2 [SPEW ] PCI: 00:00:1f.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 [SPEW ] PCI: 00:00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags d0000200 index 48 [SPEW ] PCI: 00:00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 [DEBUG] PCI: 00:00:1f.3 [SPEW ] PCI: 00:00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 [SPEW ] PCI: 00:00:1f.3 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 20 [DEBUG] PCI: 00:00:1f.4 [DEBUG] PCI: 00:00:1f.5 [DEBUG] PCI: 00:00:1f.6 [SPEW ] PCI: 00:00:1f.6 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 [DEBUG] PCI: 00:00:1f.7 [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [DEBUG] PCI: 00:00:1d.2 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:00:1d.2 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:00:1d.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0x3fff] mem [DEBUG] PCI: 00:00:1d.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:00:1d.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:00:1d.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00001600 limit 0000167f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 000015e0 limit 000015ef io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 8c base 00000080 limit 0000008f io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.1 15e0 base 000015e0 limit 000015ef io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 60 base 00000060 limit 00000060 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 62 base 00000062 limit 00000062 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 64 base 00000064 limit 00000064 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 66 base 00000066 limit 00000066 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 1600 base 00001600 limit 00001600 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 1604 base 00001604 limit 00001604 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 1602 base 00001602 limit 00001602 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 1606 base 00001606 limit 00001606 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 00ff.2 1610 base 00001610 limit 0000161f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: 5e0, Tag: 100 [INFO ] * Base: 15f0, Size: 10, Tag: 100 [INFO ] * Base: 1680, Size: 180, Tag: 100 [INFO ] * Base: 1900, Size: e700, Tag: 100 [DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 7affffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 7b000000 limit 7fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 27fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [INFO ] * Base: 280000000, Size: 7d80000000, Tag: 200 [DEBUG] PCI: 00:00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem [DEBUG] PCI: 00:00:02.0 10 * [0xcf000000 - 0xcfffffff] limit: cfffffff mem [DEBUG] PCI: 00:00:1d.2 20 * [0xcef00000 - 0xceffffff] limit: ceffffff mem [DEBUG] PCI: 00:00:1f.6 10 * [0xceee0000 - 0xceefffff] limit: ceefffff mem [DEBUG] PCI: 00:00:14.0 10 * [0xceed0000 - 0xceedffff] limit: ceedffff mem [DEBUG] PCI: 00:00:1f.3 20 * [0xceec0000 - 0xceecffff] limit: ceecffff mem [DEBUG] PCI: 00:00:04.0 10 * [0xceeb8000 - 0xceebffff] limit: ceebffff mem [DEBUG] PCI: 00:00:1f.2 10 * [0xceeb4000 - 0xceeb7fff] limit: ceeb7fff mem [DEBUG] PCI: 00:00:1f.3 10 * [0xceeb0000 - 0xceeb3fff] limit: ceeb3fff mem [DEBUG] PCI: 00:00:14.2 10 * [0xceeaf000 - 0xceeaffff] limit: ceeaffff mem [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done [DEBUG] PCI: 00:02:00.0 10 * [0xcef00000 - 0xcef03fff] limit: cef03fff mem [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [SPEW ] Root Device assign_resources, segment group 0 bus 0 [SPEW ] DOMAIN: 00000000 assign_resources, segment group 0 bus 0 [DEBUG] PCI: 00:00:02.0 10 <- [0x00000000cf000000 - 0x00000000cfffffff] size 0x01000000 gran 0x18 mem64 [DEBUG] PCI: 00:00:02.0 18 <- [0x00000000d0000000 - 0x00000000dfffffff] size 0x10000000 gran 0x1c prefmem64 [DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:00:04.0 10 <- [0x00000000ceeb8000 - 0x00000000ceebffff] size 0x00008000 gran 0x0f mem64 [DEBUG] PCI: 00:00:14.0 10 <- [0x00000000ceed0000 - 0x00000000ceedffff] size 0x00010000 gran 0x10 mem64 [SPEW ] PCI: 00:00:14.0 assign_resources, segment group 0 bus 0 [SPEW ] PCI: 00:00:14.0 assign_resources, segment group 0 bus 0 done [DEBUG] PCI: 00:00:14.2 10 <- [0x00000000ceeaf000 - 0x00000000ceeaffff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:00:1d.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io [DEBUG] PCI: 00:00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem [DEBUG] PCI: 00:00:1d.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem [DEBUG] PCI: 00:00:1d.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io [DEBUG] PCI: 00:00:1d.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem [DEBUG] PCI: 00:00:1d.2 20 <- [0x00000000cef00000 - 0x00000000ceffffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem [SPEW ] PCI: 00:00:1d.2 assign_resources, segment group 0 bus 2 [DEBUG] PCI: 00:02:00.0 10 <- [0x00000000cef00000 - 0x00000000cef03fff] size 0x00004000 gran 0x0e mem64 [SPEW ] PCI: 00:00:1d.2 assign_resources, segment group 0 bus 2 done [SPEW ] PCI: 00:00:1f.0 assign_resources, segment group 0 bus 0 [SPEW ] PCI: 00:00:1f.0 assign_resources, segment group 0 bus 0 done [SPEW ] LPC: Trying to open IO window from 15e0 size 10 [DEBUG] LPC: Opened IO window LGIR3: base 15e0 size 10 [DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64 [DEBUG] LPC: enabling default decode range LPC_IOE_EC_62_66 [DEBUG] LPC: enabling default decode range LPC_IOE_KBC_60_64 [DEBUG] LPC: enabling default decode range LPC_IOE_EC_62_66 [SPEW ] LPC: Trying to open IO window from 1600 size 1 [SPEW ] LPC: Trying to open IO window from 1604 size 1 [SPEW ] LPC: Trying to open IO window from 1602 size 1 [SPEW ] LPC: Trying to open IO window from 1606 size 1 [SPEW ] LPC: Trying to open IO window from 1610 size 10 [DEBUG] PCI: 00:00:1f.2 10 <- [0x00000000ceeb4000 - 0x00000000ceeb7fff] size 0x00004000 gran 0x0e mem [DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000ceeb0000 - 0x00000000ceeb3fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:1f.3 20 <- [0x00000000ceec0000 - 0x00000000ceecffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:00:1f.6 10 <- [0x00000000ceee0000 - 0x00000000ceefffff] size 0x00020000 gran 0x11 mem [SPEW ] DOMAIN: 00000000 assign_resources, segment group 0 bus 0 done [SPEW ] Root Device assign_resources, segment group 0 bus 0 done [INFO ] Done setting resources. [SPEW ] Show resources in subtree (Root Device)...After assigning values. [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 [DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00 [DEBUG] APIC: 00 [DEBUG] APIC: 04 [DEBUG] APIC: 01 [DEBUG] APIC: 05 [DEBUG] APIC: 06 [DEBUG] APIC: 03 [DEBUG] APIC: 07 [DEBUG] APIC: 02 [DEBUG] DOMAIN: 00000000 child on link 0 GPIO: 0 [SPEW ] DOMAIN: 00000000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 [SPEW ] DOMAIN: 00000000 resource base 7b000000 size 0 align 0 gran 0 limit dfffffff flags 40040200 index 10000100 [SPEW ] DOMAIN: 00000000 resource base 100000000 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000200 [DEBUG] GPIO: 0 [DEBUG] PCI: 00:00:00.0 [SPEW ] PCI: 00:00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 [SPEW ] PCI: 00:00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 [SPEW ] PCI: 00:00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 [SPEW ] PCI: 00:00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 [SPEW ] PCI: 00:00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 [SPEW ] PCI: 00:00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 [SPEW ] PCI: 00:00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 [SPEW ] PCI: 00:00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 [SPEW ] PCI: 00:00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 8 [SPEW ] PCI: 00:00:00.0 resource base c0000 size 7af40000 align 0 gran 0 limit 0 flags e0004200 index 9 [SPEW ] PCI: 00:00:00.0 resource base 7b000000 size 5000000 align 0 gran 0 limit 0 flags f0000200 index a [SPEW ] PCI: 00:00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index b [SPEW ] PCI: 00:00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c [SPEW ] PCI: 00:00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d [DEBUG] PCI: 00:00:01.0 [DEBUG] PCI: 00:00:01.1 [DEBUG] PCI: 00:00:01.2 [DEBUG] PCI: 00:00:02.0 [SPEW ] PCI: 00:00:02.0 resource base cf000000 size 1000000 align 24 gran 24 limit cfffffff flags 60000201 index 10 [SPEW ] PCI: 00:00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18 [SPEW ] PCI: 00:00:02.0 resource base ffc0 size 40 align 6 gran 6 limit ffff flags 60000100 index 20 [DEBUG] PCI: 00:00:04.0 [SPEW ] PCI: 00:00:04.0 resource base ceeb8000 size 8000 align 15 gran 15 limit ceebffff flags 60000201 index 10 [DEBUG] PCI: 00:00:05.0 [DEBUG] PCI: 00:00:07.0 [DEBUG] PCI: 00:00:08.0 [DEBUG] PCI: 00:00:13.0 [DEBUG] PCI: 00:00:14.0 child on link 0 USB0 port 0 [SPEW ] PCI: 00:00:14.0 resource base ceed0000 size 10000 align 16 gran 16 limit ceedffff flags 60000201 index 10 [DEBUG] USB0 port 0 child on link 0 USB2 port 0 [DEBUG] USB2 port 0 [DEBUG] USB2 port 1 [DEBUG] USB2 port 2 [DEBUG] USB2 port 3 [DEBUG] USB2 port 4 [DEBUG] USB2 port 5 [DEBUG] USB2 port 6 [DEBUG] USB2 port 7 [DEBUG] USB2 port 8 [DEBUG] USB2 port 9 [DEBUG] USB3 port 0 [DEBUG] USB3 port 1 [DEBUG] USB3 port 2 [DEBUG] USB3 port 3 [DEBUG] USB3 port 4 [DEBUG] USB3 port 5 [DEBUG] PCI: 00:00:14.1 [DEBUG] PCI: 00:00:14.2 [SPEW ] PCI: 00:00:14.2 resource base ceeaf000 size 1000 align 12 gran 12 limit ceeaffff flags 60000201 index 10 [DEBUG] PCI: 00:00:14.3 [DEBUG] PCI: 00:00:15.0 [DEBUG] PCI: 00:00:15.1 [DEBUG] PCI: 00:00:15.2 [DEBUG] PCI: 00:00:15.3 [DEBUG] PCI: 00:00:16.0 [DEBUG] PCI: 00:00:16.1 [DEBUG] PCI: 00:00:16.2 [DEBUG] PCI: 00:00:16.3 [DEBUG] PCI: 00:00:16.4 [DEBUG] PCI: 00:00:17.0 [DEBUG] PCI: 00:00:19.0 [DEBUG] PCI: 00:00:19.1 [DEBUG] PCI: 00:00:19.2 [DEBUG] PCI: 00:00:1b.0 [DEBUG] PCI: 00:00:1b.1 [DEBUG] PCI: 00:00:1b.2 [DEBUG] PCI: 00:00:1b.3 [DEBUG] PCI: 00:00:1b.4 [DEBUG] PCI: 00:00:1b.5 [DEBUG] PCI: 00:00:1b.6 [DEBUG] PCI: 00:00:1b.7 [DEBUG] PCI: 00:00:1d.0 [SPEW ] PCI: 00:00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c [SPEW ] PCI: 00:00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 [SPEW ] PCI: 00:00:1d.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20 [DEBUG] PCI: 00:00:1d.2 child on link 0 PCI: 00:02:00.0 [SPEW ] PCI: 00:00:1d.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c [SPEW ] PCI: 00:00:1d.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 [SPEW ] PCI: 00:00:1d.2 resource base cef00000 size 100000 align 20 gran 20 limit ceffffff flags 60080202 index 20 [DEBUG] PCI: 00:02:00.0 [SPEW ] PCI: 00:02:00.0 resource base cef00000 size 4000 align 14 gran 14 limit cef03fff flags 60000201 index 10 [DEBUG] PCI: 00:00:1d.4 [DEBUG] PCI: 00:00:1d.5 [DEBUG] PCI: 00:00:1d.6 [DEBUG] PCI: 00:00:1d.7 [DEBUG] PCI: 00:00:1e.0 [DEBUG] PCI: 00:00:1e.1 [DEBUG] PCI: 00:00:1e.2 [DEBUG] PCI: 00:00:1e.3 [DEBUG] PCI: 00:00:1e.4 [DEBUG] PCI: 00:00:1e.5 [DEBUG] PCI: 00:00:1e.6 [DEBUG] PCI: 00:00:1f.0 child on link 0 PNP: 00ff.1 [SPEW ] PCI: 00:00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 [SPEW ] PCI: 00:00:1f.0 resource base 1600 size 80 align 0 gran 0 limit 0 flags c0000100 index 84 [SPEW ] PCI: 00:00:1f.0 resource base 15e0 size 10 align 0 gran 0 limit 0 flags c0000100 index 88 [SPEW ] PCI: 00:00:1f.0 resource base 80 size 10 align 0 gran 0 limit 0 flags c0000100 index 8c [DEBUG] PNP: 00ff.1 [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 0 gran 0 limit 0 flags c0000100 index 15e0 [DEBUG] PNP: 00ff.2 [SPEW ] PNP: 00ff.2 resource base 60 size 1 align 0 gran 0 limit 0 flags c0000100 index 60 [SPEW ] PNP: 00ff.2 resource base 62 size 1 align 0 gran 0 limit 0 flags c0000100 index 62 [SPEW ] PNP: 00ff.2 resource base 64 size 1 align 0 gran 0 limit 0 flags c0000100 index 64 [SPEW ] PNP: 00ff.2 resource base 66 size 1 align 0 gran 0 limit 0 flags c0000100 index 66 [SPEW ] PNP: 00ff.2 resource base 1600 size 1 align 0 gran 0 limit 0 flags c0000100 index 1600 [SPEW ] PNP: 00ff.2 resource base 1604 size 1 align 0 gran 0 limit 0 flags c0000100 index 1604 [SPEW ] PNP: 00ff.2 resource base 1602 size 1 align 0 gran 0 limit 0 flags c0000100 index 1602 [SPEW ] PNP: 00ff.2 resource base 1606 size 1 align 0 gran 0 limit 0 flags c0000100 index 1606 [SPEW ] PNP: 00ff.2 resource base 1610 size 10 align 0 gran 0 limit 0 flags c0000100 index 1610 [DEBUG] PNP: 0c31.0 [SPEW ] PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 [DEBUG] PCI: 00:00:1f.1 [SPEW ] PCI: 00:00:1f.1 resource base fd000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 [DEBUG] PCI: 00:00:1f.2 [SPEW ] PCI: 00:00:1f.2 resource base ceeb4000 size 4000 align 14 gran 14 limit ceeb7fff flags 60000200 index 10 [SPEW ] PCI: 00:00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags d0000200 index 48 [SPEW ] PCI: 00:00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 40 [DEBUG] PCI: 00:00:1f.3 [SPEW ] PCI: 00:00:1f.3 resource base ceeb0000 size 4000 align 14 gran 14 limit ceeb3fff flags 60000201 index 10 [SPEW ] PCI: 00:00:1f.3 resource base ceec0000 size 10000 align 16 gran 16 limit ceecffff flags 60000201 index 20 [DEBUG] PCI: 00:00:1f.4 [DEBUG] PCI: 00:00:1f.5 [DEBUG] PCI: 00:00:1f.6 [SPEW ] PCI: 00:00:1f.6 resource base ceee0000 size 20000 align 17 gran 17 limit ceefffff flags 60000200 index 10 [DEBUG] PCI: 00:00:1f.7 [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1 ms [INFO ] POST: 0x94 [INFO ] POST: 0xa2 [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6 [DEBUG] 0x000000007b000000 - 0x00000000cfffffff size 0x55000000 type 0 [DEBUG] 0x00000000d0000000 - 0x00000000dfffffff size 0x10000000 type 1 [DEBUG] 0x00000000e0000000 - 0x00000000ffffffff size 0x20000000 type 0 [DEBUG] 0x0000000100000000 - 0x000000027fffffff size 0x180000000 type 6 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 [SPEW ] apic_id 0x0 call enable_fixed_mtrr() [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 6/6. [DEBUG] MTRR: UC selected as default type. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 [DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0 [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 [DEBUG] MTRR: 3 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 [INFO ] LAPIC 0x1 in XAPIC mode. [INFO ] LAPIC 0x3 in XAPIC mode. [INFO ] LAPIC 0x2 in XAPIC mode. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26f 0x0606060606060606 [INFO ] LAPIC 0x6 in XAPIC mode. [INFO ] LAPIC 0x7 in XAPIC mode. [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x268 0x0606060606060606 [INFO ] LAPIC 0x4 in XAPIC mode. [INFO ] LAPIC 0x5 in XAPIC mode. [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26d 0x0606060606060606 [SPEW ] apic_id 0x3 call enable_fixed_mtrr() [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x5: MTRR: Fixed MSR 0x26f 0x0606060606060606 [SPEW ] apic_id 0x1 call enable_fixed_mtrr() [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x7: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x3 setup mtrr for CPU physical address size: 39 bits [DEBUG] apic_id 0x1 setup mtrr for CPU physical address size: 39 bits [SPEW ] apic_id 0x5 call enable_fixed_mtrr() [SPEW ] apic_id 0x7 call enable_fixed_mtrr() [SPEW ] apic_id 0x4 call enable_fixed_mtrr() [DEBUG] apic_id 0x7 setup mtrr for CPU physical address size: 39 bits [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x4 setup mtrr for CPU physical address size: 39 bits [DEBUG] apic_id 0x5 setup mtrr for CPU physical address size: 39 bits [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606 [SPEW ] apic_id 0x6 call enable_fixed_mtrr() [DEBUG] apic_id 0x6 setup mtrr for CPU physical address size: 39 bits [SPEW ] apic_id 0x2 call enable_fixed_mtrr() [DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits [DEBUG] MTRR: TEMPORARY Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6 [DEBUG] 0x000000007b000000 - 0x00000000feffffff size 0x84000000 type 0 [DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5 [DEBUG] 0x0000000100000000 - 0x000000027fffffff size 0x180000000 type 6 [DEBUG] MTRR: default type WB/UC MTRR counts: 10/6. [DEBUG] MTRR: UC selected as default type. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 [DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0 [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0 [DEBUG] MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5 [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [INFO ] POST: 0x93 [DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 1 / 0 ms [INFO ] POST: 0x74 [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 subsystem <- 8086/5914 [DEBUG] PCI: 00:00:00.0 cmd <- 06 [DEBUG] PCI: 00:00:02.0 subsystem <- 8086/5917 [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:04.0 subsystem <- 8086/1903 [DEBUG] PCI: 00:00:04.0 cmd <- 02 [DEBUG] PCI: 00:00:14.0 subsystem <- 8086/9d2f [DEBUG] PCI: 00:00:14.0 cmd <- 02 [DEBUG] PCI: 00:00:14.2 subsystem <- 8086/9d31 [DEBUG] PCI: 00:00:14.2 cmd <- 02 [DEBUG] PCI: 00:00:1d.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1d.0 subsystem <- 8086/9d18 [DEBUG] PCI: 00:00:1d.0 cmd <- 00 [DEBUG] PCI: 00:00:1d.2 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1d.2 subsystem <- 8086/9d1a [DEBUG] PCI: 00:00:1d.2 cmd <- 06 [DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/9d4e [DEBUG] PCI: 00:00:1f.0 cmd <- 07 [DEBUG] PCI: 00:00:1f.2 subsystem <- 8086/9d21 [DEBUG] PCI: 00:00:1f.2 cmd <- 02 [DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/9d71 [DEBUG] PCI: 00:00:1f.3 cmd <- 02 [DEBUG] PCI: 00:00:1f.6 subsystem <- 8086/15d8 [DEBUG] PCI: 00:00:1f.6 cmd <- 02 [DEBUG] PCI: 00:02:00.0 cmd <- 02 [INFO ] done. [INFO ] POST: 0x75 [INFO ] Initializing devices... [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:00.0 init [INFO ] CPU TDP = 15 Watts [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 18 Watts [DEBUG] PCI: 00:00:00.0 init finished in 1 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:02.0 init [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'vbt.bin' @0x9c640 size 0x48d in mcache @0x7abdd1e4 [INFO ] Found a VBT of 4106 bytes [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000 [DEBUG] PCI: 00:00:02.0 init finished in 407 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:04.0 init [DEBUG] PCI: 00:00:04.0 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:14.0 init [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:14.2 init [DEBUG] PCI: 00:00:14.2 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1d.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1d.0 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1d.2 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1d.2 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1f.0 init [DEBUG] IOAPIC: Initializing IOAPIC at fec00000 [DEBUG] IOAPIC: ID = 0x00 [SPEW ] IOAPIC: Dumping registers [SPEW ] reg 0x0000: 0x00000000 [SPEW ] reg 0x0001: 0x00770020 [SPEW ] reg 0x0002: 0x00000000 [DEBUG] IOAPIC: 120 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at fec00000 [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x18 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x19 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x1f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x20 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x21 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x22 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x23 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x24 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x25 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x26 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x27 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x28 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x29 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x2f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x30 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x31 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x32 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x33 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x34 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x35 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x36 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x37 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x38 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x39 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x3f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x40 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x41 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x42 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x43 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x44 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x45 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x46 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x47 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x48 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x49 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x4f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x50 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x51 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x52 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x53 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x54 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x55 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x56 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x57 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x58 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x59 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x5f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x60 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x61 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x62 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x63 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x64 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x65 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x66 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x67 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x68 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x69 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6a value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6b value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6c value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6d value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6e value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x6f value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x70 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x71 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x72 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x73 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x74 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x75 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x76 value 0x00000000 0x00010000 [SPEW ] IOAPIC: vector 0x77 value 0x00000000 0x00010000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700 [DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1f.2 init [DEBUG] RTC Init [INFO ] Keep power state after power failure. [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route from MISCCFG register [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] Disabling Deep S3 [DEBUG] Disabling Deep S3 [DEBUG] Disabling Deep S4 [DEBUG] Disabling Deep S4 [DEBUG] Disabling Deep S5 [DEBUG] Disabling Deep S5 [DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xceeb0000 [DEBUG] azalia_audio: codec_mask = 0x01 [DEBUG] azalia_audio: initializing codec #0... [DEBUG] azalia_audio: - vendor/device id: 0x10ec0257 [DEBUG] azalia_audio: - verb size: 72 [DEBUG] azalia_audio: - verb loaded [DEBUG] PCI: 00:00:1f.3 init finished in 6 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00:1f.6 init [DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:02:00.0 init [DEBUG] PCI: 00:02:00.0 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PNP: 00ff.2 init [DEBUG] PNP: 00ff.2 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] Devices initialized [SPEW ] Show all devs... After init. [SPEW ] Root Device: enabled 1 [SPEW ] CPU_CLUSTER: 0: enabled 1 [SPEW ] DOMAIN: 00000000: enabled 1 [SPEW ] GPIO: 0: enabled 1 [SPEW ] PCI: 00:00:00.0: enabled 1 [SPEW ] PCI: 00:00:01.0: enabled 0 [SPEW ] PCI: 00:00:01.1: enabled 0 [SPEW ] PCI: 00:00:01.2: enabled 0 [SPEW ] PCI: 00:00:02.0: enabled 1 [SPEW ] PCI: 00:00:04.0: enabled 1 [SPEW ] PCI: 00:00:05.0: enabled 0 [SPEW ] PCI: 00:00:07.0: enabled 0 [SPEW ] PCI: 00:00:08.0: enabled 0 [SPEW ] PCI: 00:00:13.0: enabled 0 [SPEW ] PCI: 00:00:14.0: enabled 1 [SPEW ] PCI: 00:00:14.1: enabled 0 [SPEW ] PCI: 00:00:14.2: enabled 1 [SPEW ] PCI: 00:00:14.3: enabled 0 [SPEW ] PCI: 00:00:15.0: enabled 0 [SPEW ] PCI: 00:00:15.1: enabled 0 [SPEW ] PCI: 00:00:15.2: enabled 0 [SPEW ] PCI: 00:00:15.3: enabled 0 [SPEW ] PCI: 00:00:16.0: enabled 0 [SPEW ] PCI: 00:00:16.1: enabled 0 [SPEW ] PCI: 00:00:16.2: enabled 0 [SPEW ] PCI: 00:00:16.3: enabled 0 [SPEW ] PCI: 00:00:16.4: enabled 0 [SPEW ] PCI: 00:00:17.0: enabled 0 [SPEW ] PCI: 00:00:19.0: enabled 0 [SPEW ] PCI: 00:00:19.1: enabled 0 [SPEW ] PCI: 00:00:19.2: enabled 0 [SPEW ] PCI: 00:00:1b.0: enabled 0 [SPEW ] PCI: 00:00:1b.1: enabled 0 [SPEW ] PCI: 00:00:1b.2: enabled 0 [SPEW ] PCI: 00:00:1b.3: enabled 0 [SPEW ] PCI: 00:00:1b.4: enabled 0 [SPEW ] PCI: 00:00:1b.5: enabled 0 [SPEW ] PCI: 00:00:1b.6: enabled 0 [SPEW ] PCI: 00:00:1b.7: enabled 0 [SPEW ] PCI: 00:00:1c.0: enabled 0 [SPEW ] PCI: 00:00:1c.1: enabled 0 [SPEW ] PCI: 00:00:1c.2: enabled 0 [SPEW ] PCI: 00:00:1c.3: enabled 0 [SPEW ] PCI: 00:00:1c.4: enabled 0 [SPEW ] PCI: 00:00:1c.5: enabled 0 [SPEW ] PCI: 00:00:1c.6: enabled 0 [SPEW ] PCI: 00:00:1c.7: enabled 0 [SPEW ] PCI: 00:00:1d.0: enabled 1 [SPEW ] PCI: 00:00:1d.1: enabled 0 [SPEW ] PCI: 00:00:1d.2: enabled 1 [SPEW ] PCI: 00:00:1d.3: enabled 0 [SPEW ] PCI: 00:00:1d.4: enabled 0 [SPEW ] PCI: 00:00:1d.5: enabled 0 [SPEW ] PCI: 00:00:1d.6: enabled 0 [SPEW ] PCI: 00:00:1d.7: enabled 0 [SPEW ] PCI: 00:00:1e.0: enabled 0 [SPEW ] PCI: 00:00:1e.1: enabled 0 [SPEW ] PCI: 00:00:1e.2: enabled 0 [SPEW ] PCI: 00:00:1e.3: enabled 0 [SPEW ] PCI: 00:00:1e.4: enabled 0 [SPEW ] PCI: 00:00:1e.5: enabled 0 [SPEW ] PCI: 00:00:1e.6: enabled 0 [SPEW ] PCI: 00:00:1f.0: enabled 1 [SPEW ] PCI: 00:00:1f.1: enabled 1 [SPEW ] PCI: 00:00:1f.2: enabled 1 [SPEW ] PCI: 00:00:1f.3: enabled 1 [SPEW ] PCI: 00:00:1f.4: enabled 0 [SPEW ] PCI: 00:00:1f.5: enabled 0 [SPEW ] PCI: 00:00:1f.6: enabled 1 [SPEW ] PCI: 00:00:1f.7: enabled 0 [SPEW ] USB0 port 0: enabled 0 [SPEW ] GENERIC: 0.0: enabled 0 [SPEW ] PNP: 00ff.1: enabled 1 [SPEW ] PNP: 00ff.2: enabled 1 [SPEW ] PNP: 0c31.0: enabled 1 [SPEW ] USB2 port 0: enabled 0 [SPEW ] USB2 port 1: enabled 0 [SPEW ] USB2 port 2: enabled 0 [SPEW ] USB2 port 3: enabled 0 [SPEW ] USB2 port 4: enabled 0 [SPEW ] USB2 port 5: enabled 0 [SPEW ] USB2 port 6: enabled 0 [SPEW ] USB2 port 7: enabled 0 [SPEW ] USB2 port 8: enabled 0 [SPEW ] USB2 port 9: enabled 0 [SPEW ] USB3 port 0: enabled 0 [SPEW ] USB3 port 1: enabled 0 [SPEW ] USB3 port 2: enabled 0 [SPEW ] USB3 port 3: enabled 0 [SPEW ] USB3 port 4: enabled 0 [SPEW ] USB3 port 5: enabled 0 [SPEW ] APIC: 00: enabled 1 [SPEW ] APIC: 04: enabled 1 [SPEW ] APIC: 01: enabled 1 [SPEW ] APIC: 05: enabled 1 [SPEW ] APIC: 06: enabled 1 [SPEW ] APIC: 03: enabled 1 [SPEW ] APIC: 07: enabled 1 [SPEW ] APIC: 02: enabled 1 [SPEW ] PCI: 00:02:00.0: enabled 1 [DEBUG] BS: BS_DEV_INIT run times (exec / console): 416 / 0 ms [INFO ] POST: 0x76 [INFO ] Finalize devices... [DEBUG] PCI: 00:00:02.0 final [DEBUG] PCI: 00:00:1f.2 final [DEBUG] PCI: 00:00:1f.3 final [INFO ] Devices finalized [INFO ] POST: 0x77 [INFO ] POST: 0x79 [INFO ] POST: 0x9c [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x982c0 size 0x4337 in mcache @0x7abdd1b8 [DEBUG] Starting cbfs_boot_device [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 7aa0e000. [DEBUG] ACPI: * FACS [DEBUG] SCI is IRQ 9, GSI 9 [DEBUG] ACPI: * FACP [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] Found 1 CPU(s) with 4/8 physical/logical core(s) each. [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PSS: 1601MHz power 15000 control 0x2200 status 0x2200 [DEBUG] PSS: 1600MHz power 15000 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 12823 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 10732 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 8737 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 6832 control 0x800 status 0x800 [DEBUG] PSS: 600MHz power 5000 control 0x600 status 0x600 [DEBUG] PSS: 400MHz power 3255 control 0x400 status 0x400 [DEBUG] PCI space above 4GB MMIO is at 0x280000000, len = 0x7d80000000 [DEBUG] Empty min sleep state array returned [INFO ] Returning default LPI constraint package [INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in [INFO ] ACPI: * H8 [INFO ] H8: BDC detection not implemented. Assuming BDC installed [INFO ] H8: WWAN detection not implemented. Assuming WWAN installed [DEBUG] ACPI: * SSDT [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] ACPI: * LPIT [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] IOAPIC: 120 interrupts [DEBUG] SCI is IRQ 9, GSI 9 [DEBUG] ACPI: * APIC [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] current = 7aa13f90 [DEBUG] ACPI: * DMAR [DEBUG] ACPI: added table 6/32, length now 84 [DEBUG] acpi_write_dbg2_pci_uart: Device not found [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 7/32, length now 92 [INFO ] ACPI: done. [DEBUG] ACPI tables: 24672 bytes. [DEBUG] smbios_write_tables: 7aa06000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12-573-ge31d32443e84' [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [DEBUG] SMBIOS tables: 1080 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 653b [DEBUG] Writing coreboot table at 0x7aa32000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED [DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES [DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED [DEBUG] 5. 0000000000100000-000000007aa05fff: RAM [DEBUG] 6. 000000007aa06000-000000007aa7cfff: CONFIGURATION TABLES [DEBUG] 7. 000000007aa7d000-000000007abccfff: RAMSTAGE [DEBUG] 8. 000000007abcd000-000000007affffff: CONFIGURATION TABLES [DEBUG] 9. 000000007b000000-000000007fffffff: RESERVED [DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED [DEBUG] 11. 00000000fd000000-00000000fe00ffff: RESERVED [DEBUG] 12. 00000000fed10000-00000000fed19fff: RESERVED [DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED [DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED [DEBUG] 15. 0000000100000000-000000027fffffff: RAM [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [DEBUG] Starting cbfs_boot_device [DEBUG] Wrote coreboot table at: 0x7aa32000, 0x490 bytes, checksum f11f [DEBUG] coreboot table: 1192 bytes. [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000 [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000 [DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000 [DEBUG] CONSOLE 3. 0x7abde000 0x00020000 [DEBUG] RO MCACHE 4. 0x7abdd000 0x0000033c [DEBUG] TIME STAMP 5. 0x7abdc000 0x00000910 [DEBUG] MEM INFO 6. 0x7abda000 0x000010c8 [DEBUG] AFTER CAR 7. 0x7abcd000 0x0000d000 [DEBUG] RAMSTAGE 8. 0x7aa7c000 0x00151000 [DEBUG] REFCODE 9. 0x7aa4e000 0x0002e000 [DEBUG] SMM BACKUP 10. 0x7aa3e000 0x00010000 [DEBUG] IGD OPREGION11. 0x7aa3a000 0x00003200 [DEBUG] COREBOOT 12. 0x7aa32000 0x00008000 [DEBUG] ACPI 13. 0x7aa0e000 0x00024000 [DEBUG] SMBIOS 14. 0x7aa06000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400 [DEBUG] FSP RUNTIME 1. 0x7affebe0 0x00000004 [DEBUG] FMAP 2. 0x7affea80 0x0000015e [DEBUG] POWER STATE 3. 0x7affea40 0x00000040 [DEBUG] FSPM VERSION 4. 0x7affea20 0x00000004 [DEBUG] ROMSTAGE 5. 0x7affea00 0x00000004 [DEBUG] ROMSTG STCK 6. 0x7affe940 0x000000a8 [DEBUG] ACPI GNVS 7. 0x7affe900 0x00000038 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 0 ms [INFO ] POST: 0x7a [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/payload' @0x129d80 size 0x11e7c9 in mcache @0x7abdd2cc [DEBUG] Checking segment from ROM address 0xff83adac [DEBUG] Checking segment from ROM address 0xff83adc8 [DEBUG] Loading segment from ROM address 0xff83adac [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xff83ade4 filesize 0x11e791 [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x000000000011e791 [DEBUG] using LZMA [SPEW ] [ 0x00800000, 01000000, 0x01000000) <- ff83ade4 [DEBUG] Loading segment from ROM address 0xff83adc8 [DEBUG] Entry Point 0x008021d8 [SPEW ] Loaded segments [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 126 / 0 ms [INFO ] POST: 0x95 [INFO ] POST: 0xa3 [INFO ] POST: 0x88 [INFO ] POST: 0x89 [DEBUG] Finalizing chipset. [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [INFO ] POST: 0xfe [INFO ] POST: 0x7b [DEBUG] mp_park_aps done after 0 msecs. [DEBUG] Jumping to boot code at 0x008021d8(0x7aa32000) [INFO ] POST: 0xf8 [SPEW ] CPU0: stack: 0x7aabc820 - 0x7aabe820, lowest used address 0x7aabdf3c, stack used: 2276 bytes