[NOTE ] coreboot-4.15-1686-gaade40c3f6 Mon Feb 21 16:02:41 UTC 2022 bootblock starting (log level: 7)... [DEBUG] FSP TempRamInit successful... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x850000. [DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 5 [DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes) [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x8170 [DEBUG] BS: bootblock times (exec / console): total (unknown) / 38 ms   [NOTE ] coreboot-4.15-1686-gaade40c3f6 Mon Feb 21 16:02:41 UTC 2022 romstage starting (log level: 7)... [DEBUG] FSP TempRamInit was successful... [INFO ] GPIO table: 0xff857660, entry num: 0x98! [DEBUG] Changing GpioPad PID: c2 Offset: 0x470 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x478 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x480 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x488 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x490 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x498 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x4a0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x4a8 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x4b0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x4d8 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! [DEBUG] Changing GpioPad PID: c2 Offset: 0x500 PadModeP1: 1 P2: 0 R: 0x45000600 Fx45000200 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x498 PadModeP1: 2 P2: 3 R: 0x45000a02 Fx05000e02 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x4a0 PadModeP1: 3 P2: 0 R: 0x45000e00 Fx45040100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x4a8 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45020102 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x4b0 PadModeP1: 1 P2: 3 R: 0x45000602 Fx45000e02 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x4c8 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x4d0 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! [ERROR] GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=21)!The owner is CSME [ERROR] ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. [ERROR] ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. [ERROR] GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=22)!The owner is CSME [ERROR] ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. [ERROR] ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. [DEBUG] Changing GpioPad PID: c5 Offset: 0x560 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x568 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x570 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x578 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x580 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [ERROR] GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=39)!The owner is CSME [ERROR] ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. [ERROR] ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. [ERROR] GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=40)!The owner is CSME [ERROR] ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. [ERROR] ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. [ERROR] GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=48)!The owner is CSME [ERROR] ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. [ERROR] ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. [DEBUG] Changing GpioPad PID: c5 Offset: 0x618 PadModeP1: 1 P2: 0 R: 0x45000600 Fx45000100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x620 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000000 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x628 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x630 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x648 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x688 PadModeP1: 1 P2: 0 R: 0x44000600 Fx44000100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x710 PadModeP1: 1 P2: 0 R: 0x45000700 Fx45000100 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x718 PadModeP1: 1 P2: 2 R: 0x45000702 Fx45000b02 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x728 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x730 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x738 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x740 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x748 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x750 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x758 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x760 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x768 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x770 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x778 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! [DEBUG] Changing GpioPad PID: c5 Offset: 0x780 PadModeP1: 0 P2: 0 R: 0x45000200 Fx45000200 ! [DEBUG] TCO base address set to 0x400! [DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes) [INFO ] CBFS: Found 'fspm.bin' @0x20dc0 size 0x90000 [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) ============= FSP Spec v2.0 Header Revision v3 (DNV-FSP0 v0.0.1.11) ============= Fsp BootFirmwareVolumeBase - 0xFF871000 Fsp BootFirmwareVolumeSize - 0x90000 Fsp TemporaryRamBase - 0xFEF60000 Fsp TemporaryRamSize - 0x4FF00 Fsp PeiTemporaryRamBase - 0xFEF60000 Fsp PeiTemporaryRamSize - 0x27F80 Fsp StackBase - 0xFEF87F80 Fsp StackSize - 0x27F80 Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FF871000, size is 0x00090000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FF87D588 EntryPoint=0x000FF87D668 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 4D8B155B-C059-4C8F-8926-06FD4331DB8A Install PPI: A60C6B59-E459-425D-9C69-0BCC9CB27D81 Loading PEIM at 0x000FF881654 EntryPoint=0x000FF881734 FSP BUILD ID : 0015.D99 Initialise SYSTEM_CONFIGURATION Initialise PCH_SETUP CustomerRevision: version xxx Updating Policies with Memory Init UPD PCDs... 0x03 : PcdInterleaveMode 0x00 : PcdHalfWidthEnable 0x01 : PcdTclIdle 0x00 : PcdMemoryPreservation 0x00 : PcdMemoryThermalThrottling Install PPI: 70CEA1D9-0FEE-4E68-8F26-5FCD6D092FCC Build PCH_SETUP HOB at 0xFEF61350(0x16C bytes) Build SYSTEM_CONFIGURATION HOB at 0xFEF614D8(0x650 bytes) Build PLATFORM_INFO_HOB HOB at 0xFEF61B40(0xC6 bytes) Install PPI: 2AB86EF5-ECB5-4134-B556-3854CA1FE1B4 Loading PEIM at 0x000FF884DD4 EntryPoint=0x000FF884EB4 Install PPI: D14319E2-407A-9580-8DE5-51A8FFC6D7D7 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FF888484 EntryPoint=0x000FF888554 FspInitPreMemEntryPoint() - Start Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F Setting BootMode to BOOT_ASSUMING_NO_CONFIGURATION_CHANGES [SPS] (ICC) MeFiaMuxConfigGet [HECI] Resetting HECI interface (CSR: 80000002/80000008, MEFS1:000F0345) [HECI] Send msg: 80140008 00040000 ... [HECI] Got msg: 80240008 00040000 ... [SPS] (ICC) MeFiaMuxConfigGet: FIA Mux configuration retrieved, number of lanes allowed: (20) [SPS] (ICC) MeFiaMuxConfigGet: Received number of Lanes allowed = 0x14 [SPS] (ICC) MeFiaMuxConfigGet: Received FIA Mux Lanes Configuration = 0xEA55555555 [SPS] (ICC) MeFiaMuxConfigGet: Received SATA Lanes Configuration = 0x40555555 [SPS] (ICC) MeFiaMuxConfigGet: Received PCIE Root Ports Configuration = 0x51 [SPS] (ICC) MeFiaMuxConfigGet: End - Success FiaMuxCreatePolicyDefaults() MeFiaMuxConfigGet status = Success, MuxConfiguration 0xEA55555555, NumLanesAllowed 0x14 SataLaneConfiguration 0x40555555, PcieRootPortsConfiguration 0x51 UpdatePeiFiaMuxPolicy SkuNumLanesAllowed: 0x14 FiaMuxConfig.MuxConfiguration: 0xEA55555555 FiaMuxConfig.SataLaneConfiguration: 0x40555555 FiaMuxConfig.PcieRootPortsConfiguration: 0x51 FiaMuxConfigRequest.MuxConfiguration: 0xEA55555555 FiaMuxConfigRequest.SataLaneConfiguration: 0x40555555 FiaMuxConfigRequest.PcieRootPortsConfiguration: 0x51 FIA Mux Policy ready!! Install PPI: 43CC4396-68AF-42DA-A905-4AF2EDEC2847 FIA MUX PEI Policy Initialization Done Install PPI: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Silicon PEI Policy Initialization Done policy 80400042 ------------------ PCH SATA Config 0 Policy Override ------------------ Sata controller 0 is not on FIA config ------------------ PCH SATA Config 1 Policy Override ------------------ FIA: SATA controller 1 is enabled FIA Mux Lane 0xC config is 0x1 Disabling port: 0x0 FIA Mux Lane 0xD config is 0x1 Disabling port: 0x1 FIA Mux Lane 0xE config is 0x1 Disabling port: 0x2 FIA Mux Lane 0xF config is 0x1 Disabling port: 0x3 FIA Mux Lane 0x10 config is 0x2 FIA Mux Lane 0x11 config is 0x2 FIA Mux Lane 0x12 config is 0x2 FIA Mux Lane 0x13 config is 0x3 Disabling port: 0x7 ------------------ PCH USB Config Policy Override ------------------ FIA: XHCI controller is enabled FIA Mux Lane 0x10 config is 0x2 XCHI Port 0x0 is being disabled FIA Mux Lane 0x11 config is 0x2 XCHI Port 0x1 is being disabled FIA Mux Lane 0x12 config is 0x2 XCHI Port 0x2 is being disabled FIA Mux Lane 0x13 config is 0x3 XCHI Port 0x3 is enabled PCH_PWRON: NvmSafeRegister = 1 PCH_PWRON: GpioSafeRegister = 0 PCH_PWRON: DmiSafeRegister = 1 PCH_PWRON: SmbusSafeRegister = 0 PCH_PWRON: RtcSafeRegister = 0 PCH_PWRON: ItssSafeRegister = 0 PCH_PWRON: P2sbSafeRegister = 1 PCH_PWRON: PsthSafeRegister = 1 PCH_PWRON: HostPmSafeRegister = 1 PCH_PWRON: ScsSafeRegister = 1 PCH_PWRON: ThermalSafeRegister = 1 PCH_PWRON: PcieSafeRegister = 1 PCH_PWRON: PsfSafeRegister = 1 PCH_PWRON: XhciSafeSettings = 0 PCH_PWRON: XdciSafeSettings = 1 PCH_PWRON: SataPmSafeRegister = 0 PCH_PWRON: FiaSafeRegister = 0 PCH_PWRON: LpcSafeRegister = 0 PCH_PWRON: IshSafeRegister = 1 PCH_PWRON: HdaSafeRegister = 1 PCH_PWRON: DciSafeRegister = 0 PCH_PWRON: CSI2SafeRegister = 1 ------------------------ PCH Print Platform Protocol Start ------------------------ Revision= C AcpiBase= 1800 MctpBroadcastCycle= 0 ------------------ PCH General Config ------------------ SubSystemVendorId= 8086 SubSystemId= 7270 Crid= 0 ------------------ PCH SATA Config 0 ----------------- Enable= 0 SataMode= 0 PortSettings[0] Enabled= 1 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 1 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 1 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 1 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 1 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 1 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 1 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH SATA Config 1 ----------------- Enable= 1 SataMode= 0 PortSettings[0] Enabled= 0 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 0 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 0 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 0 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 1 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 1 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 0 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH USB Config ------------------ UsbPrecondition= 0 DisableComplianceMode= 0 PortUsb20[0].Enabled= 1 PortUsb20[0].OverCurrentPin= OC8 PortUsb20[0].Afe.Petxiset= 4 PortUsb20[0].Afe.Txiset= 0 PortUsb20[0].Afe.Predeemp= 3 PortUsb20[0].Afe.Pehalfbit= 0 PortUsb20[1].Enabled= 1 PortUsb20[1].OverCurrentPin= OC8 PortUsb20[1].Afe.Petxiset= 4 PortUsb20[1].Afe.Txiset= 0 PortUsb20[1].Afe.Predeemp= 3 PortUsb20[1].Afe.Pehalfbit= 0 PortUsb20[2].Enabled= 1 PortUsb20[2].OverCurrentPin= OC8 PortUsb20[2].Afe.Petxiset= 4 PortUsb20[2].Afe.Txiset= 0 PortUsb20[2].Afe.Predeemp= 3 PortUsb20[2].Afe.Pehalfbit= 0 PortUsb20[3].Enabled= 1 PortUsb20[3].OverCurrentPin= OC8 PortUsb20[3].Afe.Petxiset= 4 PortUsb20[3].Afe.Txiset= 0 PortUsb20[3].Afe.Predeemp= 3 PortUsb20[3].Afe.Pehalfbit= 0 PortUsb30[0] Enabled= 0 PortUsb30[0].OverCurrentPin= OC8 PortUsb30[0].HsioTxDeEmph = 0 PortUsb30[0].HsioTxDeEmphEnable = 0 PortUsb30[0].HsioTxDownscaleAmp = 0 PortUsb30[0].HsioTxDownscaleAmpEnable = 0 PortUsb30[1] Enabled= 0 PortUsb30[1].OverCurrentPin= OC8 PortUsb30[1].HsioTxDeEmph = 0 PortUsb30[1].HsioTxDeEmphEnable = 0 PortUsb30[1].HsioTxDownscaleAmp = 0 PortUsb30[1].HsioTxDownscaleAmpEnable = 0 PortUsb30[2] Enabled= 0 PortUsb30[2].OverCurrentPin= OC8 PortUsb30[2].HsioTxDeEmph = 0 PortUsb30[2].HsioTxDeEmphEnable = 0 PortUsb30[2].HsioTxDownscaleAmp = 0 PortUsb30[2].HsioTxDownscaleAmpEnable = 0 PortUsb30[3] Enabled= 1 PortUsb30[3].OverCurrentPin= OC8 PortUsb30[3].HsioTxDeEmph = 0 PortUsb30[3].HsioTxDeEmphEnable = 0 PortUsb30[3].HsioTxDownscaleAmp = 0 PortUsb30[3].HsioTxDownscaleAmpEnable = 0 XhciEnabled = 0 XhciSsicHalt = 0 EPTypeLockPolicy = 0x00000000 EPTypeLockPolicyPortControl1 = 0x00000000 EPTypeLockPolicyPortControl2 = 0x00000000 TstMnuUnlockUsbForNoa= 0 ------------------ PCH IOAPIC Config ------------------ BdfValid= 1 BusNumber= F0 DeviceNumber= 1F FunctionNumber= 0 IoApicId= 2 ApicRangeSelect= 0 IoApicEntry24_119= 0 ------------------ PCH HPET Config ------------------ Enable 1 BdfValid 0 BusNumber 0 DeviceNumber 0 FunctionNumber 0 Base FED00000 ------------------ PCH SMBUS Config ------------------ Enable= 1 ArpEnable= 0 DynamicPowerGating= 0 SmbusIoBase= EFA0 NumRsvdSmbusAddresses= 4 RsvdSmbusAddressTable= { A2h A0h A2h A0h } ------------------ PCH Lock Down Config ------------------ GlobalSmi= 1 BiosInterface= 1 RtcLock= 1 BiosLock= 1 SpiEiss= 1 ------------------ PCH PM Config ------------------ PowerResetStatusClear MeWakeSts = 0 PowerResetStatusClear MeHrstColdSts = 0 PowerResetStatusClear MeHrstWarmSts = 0 PowerResetStatusClear MeHostPowerDn = 0 PowerResetStatusClear WolOvrWkSts = 0 WakeConfig PmeB0S5Dis = 0 WakeConfig WolEnableOverride = 0 WakeConfig LanWakeFromDeepSx = 0 WakeConfig PcieWakeFromDeepSx = 0 WakeConfig WoWlanEnable = 0 WakeConfig WoWlanDeepSxEnable = 0 PchDeepSxPol = 0 PchSlpS3MinAssert = 0 PchSlpS4MinAssert = 0 PchSlpSusMinAssert = 0 PchSlpAMinAssert = 0 PciClockRun = 0 SlpStrchSusUp = 0 SlpLanLowDc = 0 PwrBtnOverridePeriod = 0 DisableEnergyReport = 0 DisableDsxAcPresentPulldown = 0 PmcReadDisable = 1 PchPwrCycDur = 0 PciePllSsc = 0 CapsuleResetType = 0 PchPmRegisterLock = 0 SlpS0CsMePgQDis = 0 SlpS0GbeDiscQDis = 0 SlpS0ADspD3QDis = 0 SlpS0XhciD3QDis = 0 SlpS0LpioD3QDis = 0 SlpS0IccPllWBEn = 0 SlpS0PUGBEn = 0 ------------------ PCH LPC SIRQ Config ------------------ SirqEnable= 1 SirqMode= 0 StartFramePulse= 0 ------------------ PCH Interrupt Config ------------------ Interrupt assignment: Dxx:Fx INTx IRQ D31:F4 1 023 D31:F7 1 023 D28:F0 1 016 D27:F0 1 016 D27:F1 2 017 D27:F3 3 018 D27:F4 4 019 D26:F2 3 018 D26:F1 2 017 D26:F0 1 016 D24:F0 1 016 D24:F1 2 017 D24:F3 3 018 D24:F4 4 019 D23:F0 1 017 D22:F0 1 016 D21:F0 1 019 D20:F0 1 021 D19:F0 1 020 D18:F0 1 016 D17:F0 4 023 D16:F0 3 022 D15:F0 2 021 D14:F0 1 020 D12:F0 4 019 D11:F0 3 018 D10:F0 2 017 D09:F0 1 016 D06:F0 1 018 D05:F0 1 023 Legacy PIC interrupt routing: PIRQx IRQx PIRQA -> IRQ11 PIRQB -> IRQ10 PIRQC -> IRQ6 PIRQD -> IRQ7 PIRQE -> IRQ12 PIRQF -> IRQ14 PIRQG -> IRQ15 PIRQH -> IRQ15 Other interrupt configuration: GpioIrqRoute= 14 SciIrqSelect= 9 TcoIrqEnable= 0 TcoIrqSelect= 9 ------------------ PCH HSUART Config ---------------- HsUartMode[0]= 0 HsUartMode[1]= 0 HsUartMode[2]= 0 ------------------ PCH TraceHub Config ------------------ TraceHubEnable = 1 TraceHubFwEnable = 1 TraceHubFwDestination = 1 TraceHubPtiMode = 2 TraceHubPtiTraining = 0 TraceHubPtiSpeed = 0 TraceHubMemBaseRegion0 = 0 TraceHubMemBaseRegion1 = 0 EnableMode= 0 MemReg0Size= 100000 MemReg1Size= 100000 ------------------ PCH Flash Protection Config ------------------ WriteProtectionEnable[0]= 1 ReadProtectionEnable[0]= 0 ProtectedRangeLimit[0]= 0 ProtectedRangeBase[0]= 0 WriteProtectionEnable[1]= 1 ReadProtectionEnable[1]= 0 ProtectedRangeLimit[1]= 0 ProtectedRangeBase[1]= 0 WriteProtectionEnable[2]= 1 ReadProtectionEnable[2]= 0 ProtectedRangeLimit[2]= 0 ProtectedRangeBase[2]= 0 WriteProtectionEnable[3]= 1 ReadProtectionEnable[3]= 0 ProtectedRangeLimit[3]= 0 ProtectedRangeBase[3]= 0 WriteProtectionEnable[4]= 1 ReadProtectionEnable[4]= 0 ProtectedRangeLimit[4]= 0 ProtectedRangeBase[4]= 0 ------------------ PCH WDT Config ------------------ DisableAndLock= 1 ------------------ PCH P2SB Config ------------------ SbiUnlock= 0 PsfUnlock= 0 ------------------ PCH DCI Config ------------------ DciEn= 0 DciAutoDetect= 1 ------------------ PCH LPC Config ------------------ EnhancePort8xhDecoding= 1 ------------------ PCH SPI Config ------------------ ShowSpiController= 0 ------------------------ PCH Print Platform Protocol End -------------------------- Install PPI: DFE2B897-0E8E-4926-BC69-E5EDD3F938E1 PCH PEI Policy Initialization Done in Pre-Memory TotalBlockCount = 0x5 TotalPolicySize after adding Block[0x0]= 0x68 TotalPolicySize after adding Block[0x1]= 0x84 TotalPolicySize after adding Block[0x2]= 0xA34 TotalPolicySize after adding Block[0x3]= 0xA48 TotalPolicySize after adding Block[0x4]= 0xA60 TotalPolicySize Final = 0xA60 SaInitPolicy= 0xFEF62BB8 Inside case EnumPlatformConfigId Exiting case EnumPlatformConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x0 Inside case EnumVtdConfigId Vtd->BlockId = 0x3 Vtd->BlockSize = 0x1C Vtd 0x1C and remapping 0x0 Exiting case EnumVtdConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x3 Exiting case EnumMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x1 Exiting case EnumNvMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x2 Exiting case EnumSaRestrictedConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x4 SiSaPolicyPpi->Header.BlockCount = 0x5 UpdatePeiSaPolicy() vtd 1 and remapping 1 Install PPI: F5621AF5-F70B-4360-84F3-C2CF5143CDB8 SA Data HOB installed SystemAgent PEI Platform Policy Initialization Done Pcie IP Policy ready!! Install PPI: BB159A68-8300-43EF-A2A7-F2ADE6C964A6 PCIE IP PEI Policy Initialization Done IQAT IP Policy ready!! Install PPI: AC6BD8E9-0B89-45B1-AE09-A2C017334B6A IQAT IP PEI Policy Initialization Done FspInitPreMemEntryPoint() - End Loading PEIM at 0x000FF895C4C EntryPoint=0x000FF895D1C SiInitPrePolicy : Entry Install PPI: 75AFD0B3-1F2F-4871-AFF2-7AA48AF259D8 PchInitPrePolicy : Entry PCH Series : SKL PCH-H PCH Revision ID: 0x11 PCH Stepping : B1 PCH SKU : (WDT) Readback = 0x00002000 (WDT) Status OK. Install PPI: F38D1338-AF7A-4FB6-91DB-1A9C2183570D Install PPI: 17865DC0-0B8B-4DA8-8B42-7C46B85CCA4D InstallPchReset() Start Install PPI: 433E0F9F-05AE-410A-A0C3-BF298ECB25AC InstallPchReset() End InstallPchSpi() Start Flash Region read Permission : CB Flash Region write Permission : 4A Component 0 SFDP VSCC value : B1D82004 Component 1 SFDP VSCC value : B1D82004 Component Number : 1 Total Flash Size : 1000000 PchStrapBaseAddr : 100 PchStrapSize : FC CpuStrapBaseAddr : 300 CpuStrapSize : 4 Install PPI: FBF26154-4E55-4BDC-AF7B-D918AC443F61 SPI PPI Installed InstallPchSpi() End PchInitPreMem : Entry PCH PWRM Base needs to be programmed before here PCH Revision ID: 0x11 PCH Revision ID: 0x11 PchEarlyInit : Entry PRSTS = 0xFED03010 Value = 0x10100900 ETR3 = 0xE00FA0AC Value = 0x00000000 ConfigureLpcOnEarlyPei() PchEarlyInit : Exit PchInitPreMem : Exit PchInitPrePolicy : Exit Register PPI Notify: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Notify: PPI Guid: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670, Peim notify entry point: FF895D4C SiInitPreMemOnPolicy : Entry PmcStPgInit : Entry ST_PG_FDIS_PMC_1 = 0x00000004 PmcStPgInit : Exit PchOnPolicyInstalled : Entry (Wdt) IsWdtEnabled - no xHCI: Usb2AfeProgramming Start PCH Revision ID: 0x11 PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PCH Revision ID: 0x11 MePolicyPpi not located! Error: Not Found (Hsio) ChipsetInitHob not found [HECI] Send msg: 80040007 000001F2 [HECI] Got msg: 80080007 000081F2 ... (Hsio) Creating HOB to adjust Hsio settings in PchInit, if required (Hsio) ME Reported CRC=0x12FD (Hsio) BIOS Hsio CRC=0x12FD PchHsioBiosProg() Start PostCode <> FIA LOS1 = 00000000 FIA LOS2 = 00000000 FIA LOS3 = 00001222 PCH Revision ID: 0x11 Was detected stepping 3 POSTCODE << C5 >> LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported POSTCODE << C6 >> PchHsioBiosProg() End PostCode <> PchDciConfiguration : Entry ECTRL = 0x00000000 PchDciConfiguration : Exit TraceHubManagePowerGateControl() Hide config space of Trace Hub device TraceHubManagePowerGateControl() Disable config space of Trace Hub ACPI device TraceHubManagePowerGateControl() Power gating Trace Hub device ConfigurePchHSata() Start SataDeviceNumber: 0x13 DisablePchHSataController: DisablePchHSataController() Started Sata Controller Device Number: 0x13 DisablePchHSataController: DisablePchHSataController() Ended ConfigurePchSataAhci() Start SataDeviceNumber: 13 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End ConfigurePchHSata() Start SataDeviceNumber: 0x14 Setting PMC message to enable controller 0x14 ConfigurePchSataAhci() Start SataDeviceNumber: 14 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End InitializePchSmbus() Start Install PPI: 9CA93627-B65B-4324-A202-C0B461764543 InitializePchSmbus() End PchProgramSvidSid : Entry PchProgramSvidSid : Exit PCH Revision ID: 0x11 ConfigureXhciPreMem : Entry XHCI is present USB2PDO = 0xFE6084F8 Value = 0x00000000 USB3PDO = 0xFE6084FC Value = 0x00000007 PCH Revision ID: 0x11 Before XhciHcInit() POSTCODE << C7 >> Xhci Mmio Base = 0xFE600000 Xhci Mmio Base + 0x0000 (Register 0x0000 to 0x001F) = Xhci Mmio Base + 0x0080 (Register 0x0080 to 0x00BF) = Xhci Mmio Base + 0x0480 (Register 0x0480 to 0x05CF) = Xhci Mmio Base + 0x8000 (Register 0x8000 to 0x833F) = Max number of Super Speed Ports = 4 Max number of High Speed Ports = 4 PCH Revision ID: 0x11 PCH Revision ID: 0x11 XHCC1 = 0xE00A8040 Value = 0x003401FD XHCC2 = 0xE00A8044 Value = 0x03CFC68F PCE_REG = 0xE00A80A2 Value = 0x00000002 XHCLKGTEN = 0xE00A8050 Value = 0x07CE6E5B PMCTRL = 0xFE6080A4 Value = 0x49AC509C PM_CS = 0xE00A8074 Value = 0x00000008 PCH Revision ID: 0x11 PCH Revision ID: 0x11 HOST_CTRL_MISC_REG2 = 0xFE6080B4 Value = 0x00000000 PCH Revision ID: 0x11 PCH Revision ID: 0x11 PGCBCTRL_REG = 0xFE6080A8 Value = 0x0D315555 PCH Revision ID: 0x11 PCH Revision ID: 0x11 AUX_CTRL_REG1 = 0xFE6080E0 Value = 0x808CBCE0 XHCI_AUX_CCR = 0xFE60816C Value = 0x0003401C HOST_CTRL_BW_MAX_REG = 0xFE608128 Value = 0x05647F42 USB_LPM_PARAM = 0xFE608170 Value = 0x0C890032 SSPE_REG = 0xFE6080B8 Value = 0x40000008 PchUsbCommon XHCI Capability Pointer = 0xFE608000 POSTCODE << C8 >> XhciOverCurrentMapping : Entry U3OCM1 = 0xE00A80D0 Value = 0x00000000 U2OCM1 = 0xE00A80B0 Value = 0x00000000 XhciOverCurrentMapping : Exit ConfigureXhciPreMem : Exit ConfigureLpcOnPolicy() PchOnPolicyInstalled : Exit SiInitPreMemOnPolicy : Exit SiInitPrePolicy : Exit Loading PEIM at 0x000FF8A4AE4 EntryPoint=0x000FF8A4BB4 ME UMA: ME UMA PPI Driver EntryPoint Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installation status Success Loading PEIM at 0x000FF8A85EC EntryPoint=0x000FF8A86C4 [ME Policy] SSC enabled. Install PPI: 9F685891-4E6F-445C-BB9E-E57A28FA53A0 [ME Policy] ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FF8AB0A0 EntryPoint=0x000FF8AB180 [SPS] SpsPeiEntryPoint called. [SPS] Pre-DID reset is disabled [SPS] Non S3 boot path Register PPI Notify: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06 Loading PEIM at 0x000FF8B038C EntryPoint=0x000FF8B045C Install PPI: C884CCCD-2760-400E-AA9D-6D1A9241D539 Platform Policy read successfully UMA: ME UMA size set to 0. Isoc is Disabled. SMBus Legacy: SPD Write Disable bit is locked now! SMBus Host: SPD Write Disable bit is locked now! MRC VERSION: 0x950440 MRCDATA Size: 115F0 MRC_SAVE_RESTORE Size: 6F2C SocStepping: 16 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 3 DDR_CURRENT_FREQ: 3 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 3 DDR_CURRENT_FREQ: 3 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 DDR4 dimm detected C1.D0: SPD byte 1 = 0x10 C1.D0: SPD byte 2 = 0xC C1.D0: SPD byte 3 = 0x1 C1.D0: SPD byte 4 = 0x84 C1.D0: SPD byte 5 = 0x19 C1.D0: SPD byte 6 = 0x0 C1.D0: SPD byte 7 = 0x8 C1.D0: SPD byte 8 = 0x0 C1.D0: SPD byte 9 = 0x60 C1.D0: SPD byte 11 = 0x3 C1.D0: SPD byte 12 = 0x1 C1.D0: SPD byte 13 = 0xB C1.D0: SPD byte 14 = 0x80 C1.D0: SPD byte 17 = 0x0 C1.D0: SPD byte 18 = 0x7 C1.D0: SPD byte 19 = 0xD C1.D0: SPD byte 20 = 0xF8 C1.D0: SPD byte 21 = 0x7F C1.D0: SPD byte 22 = 0x0 C1.D0: SPD byte 23 = 0x0 C1.D0: SPD byte 24 = 0x6E C1.D0: SPD byte 25 = 0x6E C1.D0: SPD byte 26 = 0x6E C1.D0: SPD byte 27 = 0x11 C1.D0: SPD byte 28 = 0x0 C1.D0: SPD byte 29 = 0x6E C1.D0: SPD byte 30 = 0x20 C1.D0: SPD byte 31 = 0x8 C1.D0: SPD byte 36 = 0x0 C1.D0: SPD byte 37 = 0xA8 C1.D0: SPD byte 38 = 0x1B C1.D0: SPD byte 39 = 0x28 C1.D0: SPD byte 40 = 0x28 C1.D0: SPD byte 117 = 0x0 C1.D0: SPD byte 120 = 0x0 C1.D0: SPD byte 121 = 0x0 C1.D0: SPD byte 122 = 0x0 C1.D0: SPD byte 123 = 0x0 C1.D0: SPD byte 124 = 0xE7 C1.D0: SPD byte 125 = 0xD6 C1.D0: SPD byte 131 = 0x5 C1.D0: SPD byte 133 = 0x80 C1.D0: SPD byte 134 = 0xB3 C1.D0: SPD byte 135 = 0x30 C1.D0: SPD byte 136 = 0x0 C1.D0: SPD byte 137 = 0x0 C1.D0: SPD byte 138 = 0x0 C1.D0: SPD byte 320 = 0x80 C1.D0: SPD byte 321 = 0x2C C1.D0: SPD byte 322 = 0xF C1.D0: SPD byte 323 = 0x16 C1.D0: SPD byte 325 = 0x11 C1.D0: SPD byte 326 = 0xDA C1.D0: SPD byte 327 = 0xD0 C1.D0: SPD byte 328 = 0xBD C1.D0: SPD byte 329 = 0x39 C1.D0: SPD byte 330 = 0x41 C1.D0: SPD byte 331 = 0x53 C1.D0: SPD byte 332 = 0x46 C1.D0: SPD byte 333 = 0x35 C1.D0: SPD byte 334 = 0x31 C1.D0: SPD byte 335 = 0x32 C1.D0: SPD byte 336 = 0x37 C1.D0: SPD byte 337 = 0x32 C1.D0: SPD byte 338 = 0x50 C1.D0: SPD byte 339 = 0x5A C1.D0: SPD byte 340 = 0x2D C1.D0: SPD byte 341 = 0x32 C1.D0: SPD byte 342 = 0x47 C1.D0: SPD byte 343 = 0x33 C1.D0: SPD byte 344 = 0x41 C1.D0: SPD byte 345 = 0x32 C1.D0: SPD byte 346 = 0x20 C1.D0: SPD byte 347 = 0x20 C1.D0: SPD byte 348 = 0x20 C1.D0: SPD byte 349 = 0x32 C1.D0: SPD byte 350 = 0x80 C1.D0: SPD byte 351 = 0x2C C1.D0: SPD byte 352 = 0x41 C1.D0: SPD byte 382 = 0x0 C1.D0: SPD byte 383 = 0x0 DDR4 dimm detected C1.D1: SPD byte 1 = 0x10 C1.D1: SPD byte 2 = 0xC C1.D1: SPD byte 3 = 0x1 C1.D1: SPD byte 4 = 0x84 C1.D1: SPD byte 5 = 0x19 C1.D1: SPD byte 6 = 0x0 C1.D1: SPD byte 7 = 0x8 C1.D1: SPD byte 8 = 0x0 C1.D1: SPD byte 9 = 0x60 C1.D1: SPD byte 11 = 0x3 C1.D1: SPD byte 12 = 0x1 C1.D1: SPD byte 13 = 0xB C1.D1: SPD byte 14 = 0x80 C1.D1: SPD byte 17 = 0x0 C1.D1: SPD byte 18 = 0x7 C1.D1: SPD byte 19 = 0xD C1.D1: SPD byte 20 = 0xF8 C1.D1: SPD byte 21 = 0x7F C1.D1: SPD byte 22 = 0x0 C1.D1: SPD byte 23 = 0x0 C1.D1: SPD byte 24 = 0x6E C1.D1: SPD byte 25 = 0x6E C1.D1: SPD byte 26 = 0x6E C1.D1: SPD byte 27 = 0x11 C1.D1: SPD byte 28 = 0x0 C1.D1: SPD byte 29 = 0x6E C1.D1: SPD byte 30 = 0x20 C1.D1: SPD byte 31 = 0x8 C1.D1: SPD byte 36 = 0x0 C1.D1: SPD byte 37 = 0xA8 C1.D1: SPD byte 38 = 0x1B C1.D1: SPD byte 39 = 0x28 C1.D1: SPD byte 40 = 0x28 C1.D1: SPD byte 117 = 0x0 C1.D1: SPD byte 120 = 0x0 C1.D1: SPD byte 121 = 0x0 C1.D1: SPD byte 122 = 0x0 C1.D1: SPD byte 123 = 0x0 C1.D1: SPD byte 124 = 0xE7 C1.D1: SPD byte 125 = 0xD6 C1.D1: SPD byte 131 = 0x5 C1.D1: SPD byte 133 = 0x80 C1.D1: SPD byte 134 = 0xB3 C1.D1: SPD byte 135 = 0x30 C1.D1: SPD byte 136 = 0x0 C1.D1: SPD byte 137 = 0x0 C1.D1: SPD byte 138 = 0x0 C1.D1: SPD byte 320 = 0x80 C1.D1: SPD byte 321 = 0x2C C1.D1: SPD byte 322 = 0xF C1.D1: SPD byte 323 = 0x16 C1.D1: SPD byte 325 = 0x11 C1.D1: SPD byte 326 = 0xDA C1.D1: SPD byte 327 = 0xD0 C1.D1: SPD byte 328 = 0xBC C1.D1: SPD byte 329 = 0x39 C1.D1: SPD byte 330 = 0x41 C1.D1: SPD byte 331 = 0x53 C1.D1: SPD byte 332 = 0x46 C1.D1: SPD byte 333 = 0x35 C1.D1: SPD byte 334 = 0x31 C1.D1: SPD byte 335 = 0x32 C1.D1: SPD byte 336 = 0x37 C1.D1: SPD byte 337 = 0x32 C1.D1: SPD byte 338 = 0x50 C1.D1: SPD byte 339 = 0x5A C1.D1: SPD byte 340 = 0x2D C1.D1: SPD byte 341 = 0x32 C1.D1: SPD byte 342 = 0x47 C1.D1: SPD byte 343 = 0x33 C1.D1: SPD byte 344 = 0x41 C1.D1: SPD byte 345 = 0x32 C1.D1: SPD byte 346 = 0x20 C1.D1: SPD byte 347 = 0x20 C1.D1: SPD byte 348 = 0x20 C1.D1: SPD byte 349 = 0x32 C1.D1: SPD byte 350 = 0x80 C1.D1: SPD byte 351 = 0x2C C1.D1: SPD byte 352 = 0x41 C1.D1: SPD byte 382 = 0x0 C1.D1: SPD byte 383 = 0x0 DDR Common Frequency - DIMM capability: 6 Setup DDR Frequency - minimum of setup and cap: 6 Warning: MspData data structure hasn't been locked yet MrcFlowStatus = 0x00000000 SpdResetStatus (Fuse) = 0x00000000 SPD_RESET_PCODE (Soft Strap) = 0x00000000 SPD_BIOS_RESET = 0x00000000 SpdSpeedCurrentHw = 0x00000003 DDR Frequency : 2400 VSafe VDDQ_DDR4 Command = 8 Address = 3 Data = BF Polling Busy Bit MEM read to offset=0xFED17084; data=0x00000000 Writing Data register 7080 = BF MEM write to offset=0xFED17080; data=0x000000BF Writing Interface register 7084 = 80000308 MEM write to offset=0xFED17084; data=0x80000308 MEM read to offset=0xFED17084; data=0x00000000 MEM read to offset=0xFED17084; data=0x00000000 SPD_DDR4_MMIDH: 0x002C PPR: 1 S/H: 1 SPD_DDR4_MMIDH: 0x002C PPR: 1 S/H: 1 taaminall 13750, tckminall 833, CLdesired 17 CH1 TCL 17 TRAS = 39 TRP = 17 TRCD = 17 TWR = 18 TRFCL = 313 TWTR = 9 TRRDS = 6 TRTP = 9 TFAW = 26 TCCD = 7 DimmConfig = 0x01221226 DimmConfigs = 220 Ch 1, Dimm 0, Rank 0, MaxDq: 9 DevWidth: 8 Ch 1, Dimm 1, Rank 0, MaxDq: 9 DevWidth: 8 Fast Boot Disabling MRC Messages Command Training will be at 1N Mode tXPC = 5 tXP = 4 PeiInstallPeiMemory MemoryBegin 0x7F7FE000, MemoryLength 0x400000 ME UMA: UMA Enabled flag = 1 ME UMA: UMA Enabled flag = 1 ---------------------- MePlatformPolicyPpi Dump Begin ----------------- Revision : 0x3 MeConfig --- DidEnabled : 0x1 DidInitStat : 0x0 HeciCommunication1 : 0x1 HeciCommunication2 : 0x0 HeciCommunication3 : 0x0 SolEnabled : 0x0 IderEnabled : 0x0 WaitResetWarningAck : 0x0 EnableMePreDidReset : 0x0 ---------------------- MePlatformPolicyPpi Dump End ------------------- ME UMA: Entered ME DRAM Init Done procedure. ME UMA: MeUmaBase read: 0 ME UMA: InitStat: 0 Sending DID as MKHI message [HECI] Send msg: 80080007 000001F0 ... [HECI] Got msg: 80080007 000081F0 ... ME UMA: BiosAction = 7 ME UMA: Sending MemoryInitDoneSent Notification ... Install PPI: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06 Notify: PPI Guid: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06, Peim notify entry point: FF8AB77E [SPS] SpsNonS3Path called [SPS] Waiting for ME firmware init complete [SPS] Sending ME-BIOS Interface Version request [HECI] Send msg: 80010020 00000001 [HECI] Got msg: 800B0020 04010181 ... [SPS] SPS ME-BIOS interface version is 1.1 Feature set is 0x9B8004 [SPS] HOB: features 0x9B8004, flow 0, boot mode 1, cores to disable 0 [SPS] (ICC) Send ICC Set Clock Settings command (SSC Setting 1) [SPS] (ICC) SpsSetCurrenClockingMode [HECI] Send msg: 80300008 00040000 ... [HECI] Got msg: 80300008 00040000 ... [SPS] (ICC) SpsSetCurrenClockingMode exit status = Success [SPS] SpsFspInitComplete Start [SPS] SpsFspInitComplete HOB: features 0x9B8004, flow 0, boot mode 1, cores to disable 0 [SPS] SiliconEnabling Mode Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B [SPS] SpsFspInitComplete End [0] ME UMA: Sent MemoryInitDoneSent Notification (Success) ME UMA: UMA Enabled flag = 1 ME UMA: MeFwsts2 = 88116020. ME UMA: ME FW DID Ack requested to continue to POST. Temp Stack : BaseAddress=0xFEF87F80 Length=0x27F80 Temp Heap : BaseAddress=0xFEF60000 Length=0xDED8 Total temporary memory: 327424 bytes. temporary memory stack ever used: 122876 bytes. temporary memory heap used: 57048 bytes. Old Stack size 163712, New stack size 262144 Stack Hob: BaseAddress=0x7F7FE000 Length=0x40000 Heap Offset = 0x7F722000 Stack Offset = 0x7F771F00 Loading PEIM at 0x0007FBF3190 EntryPoint=0x0007FBF3270 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Loading PEIM at 0x0007FBE51A0 EntryPoint=0x0007FBE5270 FspInitPreMemEntryPoint() - Start Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE FspInitPreMemEntryPoint() - End Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7FBEBFF0 Memory Discovered Notify invoked ... Migrated MemoryInit UPD from 0xFEF0FCE0 to 0x7F853988 FspMemoryInitApi() - [Status: 0x00000000] - End [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x7fbff000 254 entries. [DEBUG] IMD: root @ 0x7fbfec00 62 entries. [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [DEBUG] MRC: updated 'RW_MRC_CACHE'. [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x7fe00000 0x200000 [DEBUG] Subregion 0: 0x7fe00000 0x200000 [DEBUG] Subregion 1: 0x80000000 0x0 [DEBUG] Subregion 2: 0x80000000 0x0 [DEBUG] MTRR Range: Start=7ec00000 End=7f000000 (Size 400000) [DEBUG] MTRR Range: Start=7f000000 End=7f800000 (Size 800000) [DEBUG] MTRR Range: Start=7f800000 End=7fc00000 (Size 400000) [DEBUG] MTRR Range: Start=7fe00000 End=80000000 (Size 200000) [DEBUG] MTRR Range: Start=ff000000 End=0 (Size 1000000) [INFO ] CBFS: Found 'fallback/postcar' @0xc9e40 size 0x46bc [DEBUG] Loading module at 0x7f7d3000 with entry 0x7f7d3031. filesize: 0x43a8 memsize: 0x86b0 [DEBUG] Processing 181 relocs. Offset value of 0x7d7d3000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 663 ms TempRamExitApi() - Begin MTRR programming: MSR_IA32_MTRR_FIX64K_00000 Msr 250 = 0606060606060606 MSR_IA32_MTRR_FIX16K_80000 Msr 258 = 0606060606060606 MSR_IA32_MTRR_FIX16K_A0000 Msr 259 = 0000000000000000 MSR_IA32_MTRR_FIX4K_C0000 Msr 268 = 0606060606060606 MSR_IA32_MTRR_FIX4K_C8000 Msr 269 = 0606060606060606 MSR_IA32_MTRR_FIX4K_D0000 Msr 26A = 0606060606060606 MSR_IA32_MTRR_FIX4K_D8000 Msr 26B = 0606060606060606 MSR_IA32_MTRR_FIX4K_E0000 Msr 26C = 0606060606060606 MSR_IA32_MTRR_FIX4K_E8000 Msr 26D = 0606060606060606 MSR_IA32_MTRR_FIX4K_F0000 Msr 26E = 0606060606060606 MSR_IA32_MTRR_FIX4K_F8000 Msr 26F = 0606060606060606 MSR_IA32_MTRR_PHYSBASE0 Msr 200 = 00000000FF000005 MSR_IA32_MTRR_PHYSMASK0 Msr 201 = 0000007FFF000800 MSR_IA32_MTRR_PHYSBASE1 Msr 202 = 0000000000000006 MSR_IA32_MTRR_PHYSMASK1 Msr 203 = 0000007F80000800 MSR_IA32_MTRR_PHYSBASE2 Msr 204 = 0000000100000006 MSR_IA32_MTRR_PHYSMASK2 Msr 205 = 0000007F00000800 MSR_IA32_MTRR_PHYSBASE3 Msr 206 = 0000000200000006 MSR_IA32_MTRR_PHYSMASK3 Msr 207 = 0000007F80000800 MSR_IA32_MTRR_PHYSBASE4 Msr 208 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK4 Msr 209 = 0000000000000000 MSR_IA32_MTRR_PHYSBASE5 Msr 20A = 0000000000000000 MSR_IA32_MTRR_PHYSMASK5 Msr 20B = 0000000000000000 MSR_IA32_MTRR_PHYSBASE6 Msr 20C = 0000000000000000 MSR_IA32_MTRR_PHYSMASK6 Msr 20D = 0000000000000000 MSR_IA32_MTRR_PHYSBASE7 Msr 20E = 0000000000000000 MSR_IA32_MTRR_PHYSMASK7 Msr 20F = 0000000000000000 MSR_IA32_MTRR_PHYSBASE8 Msr 210 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK8 Msr 211 = 0000000000000000 MSR_IA32_MTRR_PHYSBASE9 Msr 212 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK9 Msr 213 = 0000000000000000 TempRamExitApi() - [Status: 0x00000000] - End   [NOTE ] coreboot-4.15-1686-gaade40c3f6 Mon Feb 21 16:02:41 UTC 2022 postcar starting (log level: 7)... [INFO ] CBFS: Found 'fallback/ramstage' @0xaf40 size 0x12b80 [DEBUG] Loading module at 0x7f790000 with entry 0x7f790000. filesize: 0x25018 memsize: 0x41eb0 [DEBUG] Processing 2738 relocs. Offset value of 0x7e990000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 32 ms굔j5  [NOTE ] coreboot-4.15-1686-gaade40c3f6 Mon Feb 21 16:02:41 UTC 2022 ramstage starting (log level: 7)... [DEBUG] FMAP: area COREBOOT found @ 850200 (8060416 bytes) [INFO ] CBFS: Found 'fsps.bin' @0xb0e00 size 0x19000 [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x8280 size 0x2c00 [DEBUG] FIA MUX Configuration in FSP HOB is: [DEBUG] FiaMuxConfig.SkuNumLanesAllowed = 0x14 [DEBUG] FiaMuxConfig.FiaMuxConfig = 0xea55555555 [DEBUG] FiaMuxConfig.FiaMuxConfig.SataLaneConfiguration = 0x40555555 [DEBUG] FiaMuxConfig.FiaMuxConfig.PcieRootPortsConfiguration = 0x51 [DEBUG] FiaMuxConfig.FiaMuxConfigRequest = 0xea55555555 [DEBUG] FiaMuxConfig.FiaMuxConfigRequest.SataLaneConfiguration = 0x40555555 [DEBUG] FiaMuxConfig.FiaMuxConfigRequest.PcieRootPortsConfiguration = 0x51 [DEBUG] FiaMuxConfigStatus.FiaMuxConfigGetStatus = 0x0 [DEBUG] FiaMuxConfigStatus.FiaMuxConfigSetStatus = 0x0 [DEBUG] FiaMuxConfigStatus.FiaMuxConfigSetRequired = 0x0 SiliconInitApi() - Begin Installing FV at 0x7F776000-0x19000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FF874A7C The 1th FV start address is 0x0007F776000, size is 0x00019000, handle is 0x7F776000 Memory Discovered Notify completed ... Loading PEIM at 0x0007FBE0198 EntryPoint=0x0007FBE0270 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Loading PEIM at 0x0007FBD5000 EntryPoint=0x0007FBD5270 Updating Policies with Silicon Init UPD PCDs... UpdatePeiFiaMuxPolicy from PCD: SkuNumLanesAllowed: 0x14 FiaMuxConfig.MuxConfiguration: 0xEA55555555 FiaMuxConfig.SataLaneConfiguration: 0x40555555 FiaMuxConfig.PcieRootPortsConfiguration: 0x51 FiaMuxConfigRequest.MuxConfiguration: 0xEA55555555 FiaMuxConfigRequest.SataLaneConfiguration: 0x40555555 FiaMuxConfigRequest.PcieRootPortsConfiguration: 0x51 Dump eMMC DLL registers: R_SCC_MEM_TX_CMD_DLL_CNTL, = 0x00000508 R_SCC_MEM_TX_DATA_DLL_CNTL1 = 0x00000C11 R_SCC_MEM_TX_DATA_DLL_CNTL2 = 0x1C2A2A2A R_SCC_MEM_RX_CMD_DATA_DLL_CNTL1 = 0x00191E27 R_SCC_MEM_RX_STROBE_DLL_CNTL = 0x00000A0A R_SCC_MEM_RX_CMD_DATA_DLL_CNTL2 = 0x00010013 R_SCC_MEM_MASTER_DLL_SW_CNTL = 0x00800001 Loading PEIM at 0x0007FBB0000 EntryPoint=0x0007FBB0270 SiInit () - Start Locate PcieIpGlobalPolicy Start PcieIpInit Phase0 PcieIpInit Start PcieIpInitCluster Start, Opcode <> Configure RC0 : bifurcation code 4 Cluster B4 Strap 1 hide E Configure RC1 : bifurcation code 3 Cluster B3 Strap 5 hide A PSF PcieIpBifurcationPSF 4 soc.psf.psf_1_rc_owner_rs0= 0x40101 PcieIpInitCluster End RPBase 0 -> 0xE0048000, port 0, type: 0, bus 0, device 9 RPBase 1 -> 0xFFFFFFFF, port 1, type: 0, bus 0, device 10 RPBase 2 -> 0xFFFFFFFF, port 2, type: 0, bus 0, device 11 RPBase 3 -> 0xFFFFFFFF, port 3, type: 0, bus 0, device 12 RPBase 4 -> 0xE0070000, port 4, type: 0, bus 0, device 14 RPBase 5 -> 0xFFFFFFFF, port 5, type: 0, bus 0, device 15 RPBase 6 -> 0xE0080000, port 6, type: 0, bus 0, device 16 RPBase 7 -> 0xFFFFFFFF, port 7, type: 0, bus 0, device 17 RPBase 8 -> 0xE0030000, port 8, type: 1, bus 0, device 6 RPBase 9 -> 0xE00B0000, port 9, type: 1, bus 0, device 22 RPBase 10 -> 0xE00B8000, port 10, type: 1, bus 0, device 23 PCIE GEN3 configuration sequence, - begin for rp 0 0x000BD0 0 R_PCIE_EQEVALCTL2 BA0 R_PCIE_EQEVALCTL3 33F00802 R_PCIE_EQEVALCTL4 4B30004 R_PCIE_EQEVALCTL5 3A801013 R_PCIE_EQEVALCTL6 4904623 R_PCIE_EQEVALCTL7 20 fomincctl 4FFFF bar FE600004 - command 7 device 9, offset FE603A00 data B506 device 9, offset FE603A04 data B448 device 9, offset FE603A08 data B4CA device 9, offset FE603A0C data B50C device 9, offset FE603A10 data B44E device 9, offset FE603A14 data 34C6 device 9, offset FE603A18 data 34C6 device 9, offset FE603A1C data 34C6 device 9, offset FE603A20 data 34C6 device 9, offset FE603A24 data 34C6 device 9, offset FE603A28 data 34C6 device 9, offset FE603A2C data 34C6 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035CC data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035DC data 0 PCIE GEN3 configuration sequence - end PCIE GEN3 configuration sequence, - begin for rp 4 0x000BD0 0 R_PCIE_EQEVALCTL2 BA0 R_PCIE_EQEVALCTL3 33F00802 R_PCIE_EQEVALCTL4 4B30004 R_PCIE_EQEVALCTL5 3A801013 R_PCIE_EQEVALCTL6 4904623 R_PCIE_EQEVALCTL7 20 fomincctl 4FFFF bar FE600004 - command 7 device E, offset FE603A00 data B506 device E, offset FE603A04 data B448 device E, offset FE603A08 data B4CA device E, offset FE603A0C data B50C device E, offset FE603A10 data B44E device E, offset FE603A14 data 34C6 device E, offset FE603A18 data 34C6 device E, offset FE603A1C data 34C6 device E, offset FE603A20 data 34C6 device E, offset FE603A24 data 34C6 device E, offset FE603A28 data 34C6 device E, offset FE603A2C data 34C6 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035CC data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035DC data 0 PCIE GEN3 configuration sequence - end PCIE GEN3 configuration sequence, - begin for rp 6 0x000BD0 0 R_PCIE_EQEVALCTL2 BA0 R_PCIE_EQEVALCTL3 33F00802 R_PCIE_EQEVALCTL4 4B30004 R_PCIE_EQEVALCTL5 3A801013 R_PCIE_EQEVALCTL6 4904623 R_PCIE_EQEVALCTL7 20 fomincctl 4FFFF bar FE600004 - command 7 device 10, offset FE603A00 data B506 device 10, offset FE603A04 data B448 device 10, offset FE603A08 data B4CA device 10, offset FE603A0C data B50C device 10, offset FE603A10 data B44E device 10, offset FE603A14 data 34C6 device 10, offset FE603A18 data 34C6 device 10, offset FE603A1C data 34C6 device 10, offset FE603A20 data 34C6 device 10, offset FE603A24 data 34C6 device 10, offset FE603A28 data 34C6 device 10, offset FE603A2C data 34C6 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035CC data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035DC data 0 PCIE GEN3 configuration sequence - end PcieIpConfigureLinkSequence end PcieIpInit End FiaMuxConfigMessaging state: 1 PeiFiaMuxConfigInit Start PeiFiaMuxConfigInit End HsuartIpInit Start HsuartIpInit End PeiIqatIpInit Start Enabled IQAT device!! Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 PeiIqatIpInit End SetActiveCores: ActiveCores:4 SetActiveCores: ExistingCores:4 SetActiveCores: Initial CoreDisableMask:0 ActiveCoresMask:4411 SetActiveCores: ActiveCores:4 Setup option 'Active Processor Cores' is 0. All existing cores are active Set PCH_PCR_CORE_DISABLE_MASK_MCHBAR = 0000BBEE SetActiveCores: New # of ActiveCores:4 ActiveCoresSetupValue:4 SetActiveCores: Requesting a Reset to make changes have effect SetActiveCores: Change detected! BYPASS ColdReset - ActiveCoresSetupValue:4 CoreDisableMask:BBEE PchInit - Start Install PPI: 61C68702-4D7E-4F43-8DEF-A74305CE74C5 Register PPI Notify: 9F685891-4E6F-445C-BB9E-E57A28FA53A0 GpioPad (Group=102, Pad=15) not owned by HOST, skip it. GpioPad (Group=102, Pad=16) not owned by HOST, skip it. GpioPad (Group=102, Pad=27) not owned by HOST, skip it. GpioPad (Group=102, Pad=28) not owned by HOST, skip it. GpioPad (Group=102, Pad=30) not owned by HOST, skip it. ------------------ IRQ Usage ------------------ IRQxxx USED IRQ000 0 IRQ001 0 IRQ002 0 IRQ003 0 IRQ004 0 IRQ005 0 IRQ006 0 IRQ007 0 IRQ008 0 IRQ009 0 IRQ010 0 IRQ011 0 IRQ012 0 IRQ013 0 IRQ014 0 IRQ015 0 IRQ016 1 IRQ017 1 IRQ018 1 IRQ019 1 IRQ020 1 IRQ021 1 IRQ022 1 IRQ023 1 IRQ024 0 IRQ025 0 IRQ026 0 IRQ027 0 IRQ028 0 IRQ029 0 IRQ030 0 IRQ031 0 IRQ032 0 IRQ033 0 IRQ034 0 IRQ035 0 IRQ036 0 IRQ037 0 IRQ038 0 IRQ039 0 IRQ040 0 IRQ041 0 IRQ042 0 IRQ043 0 IRQ044 0 IRQ045 0 IRQ046 0 IRQ047 0 IRQ048 0 IRQ049 0 IRQ050 0 IRQ051 0 IRQ052 0 IRQ053 0 IRQ054 0 IRQ055 0 IRQ056 0 IRQ057 0 IRQ058 0 IRQ059 0 IRQ060 0 IRQ061 0 IRQ062 0 IRQ063 0 IRQ064 0 IRQ065 0 IRQ066 0 IRQ067 0 IRQ068 0 IRQ069 0 IRQ070 0 IRQ071 0 IRQ072 0 IRQ073 0 IRQ074 0 IRQ075 0 IRQ076 0 IRQ077 0 IRQ078 0 IRQ079 0 IRQ080 0 IRQ081 0 IRQ082 0 IRQ083 0 IRQ084 0 IRQ085 0 IRQ086 0 IRQ087 0 IRQ088 0 IRQ089 0 IRQ090 0 IRQ091 0 IRQ092 0 IRQ093 0 IRQ094 0 IRQ095 0 IRQ096 0 IRQ097 0 IRQ098 0 IRQ099 0 IRQ100 0 IRQ101 0 IRQ102 0 IRQ103 0 IRQ104 0 IRQ105 0 IRQ106 0 IRQ107 0 IRQ108 0 IRQ109 0 IRQ110 0 IRQ111 0 IRQ112 0 IRQ113 0 IRQ114 0 IRQ115 0 IRQ116 0 IRQ117 0 IRQ118 0 IRQ119 0 IRQ120 0 IRQ121 0 IRQ122 0 IRQ123 0 IRQ124 0 IRQ125 0 IRQ126 0 ConfigureXhci () - Start PchUsbPei XHCI Capability Pointer = 0xFE608000 ConfigureXhci () - End PeiMiscIpInit Start Enabled EMMC device!! Enabled GbE0 device!! Enabled GbE1 device!! PeiMiscIpInit End PchPmInit : Entry PCH Revision ID: 0x11 PM_CFG = 0xFE000018 Value = 0x2180002C PchPmInit : Exit PchInit - End PcieIpInit Phase1 PcieIpInit Start PcieIpLaneEQPresetFeature bifurcation 4 RP 0 base memory: E0048000 offset 20C offset 20E offset 210 offset 212 offset 214 offset 216 offset 218 offset 21A PcieIpLaneEQPresetFeature bifurcationt 3 RP 4 base memory: E0070000 offset 20C offset 20E offset 210 offset 212 RP 6 base memory: E0080000 offset 214 offset 216 offset 218 offset 21A Enabling Clock Gating settings PcieIpInitSwzCtl start Enabling Clock Gating settings PcieIpInitSwzCtl start Enabling Clock Gating settings PcieIpInitSwzCtl start Before link trainning, Opcode <> Enabled PCIE cluster 4!! First PCIE cluster was enabled!! Enabled PCIE cluster 5!! Second PCIE cluster was enabled!! FIA & PCIE are in sync Selected Gen speed 3 RP 0 : 0,9,0 Starting link training for PCie RP 0 : 0,9,0 Selected Gen speed 3 RP 4 : 0,14,0 Starting link training for PCie RP 4 : 0,14,0 Selected Gen speed 3 RP 6 : 0,16,0 Starting link training for PCie RP 6 : 0,16,0 PcieIpInitCluster End B RTRYCTL 3 A RTRYCTL 3 Root port replay timer 0 -> 3 B RTRYCTL 3 A RTRYCTL 3 Root port replay timer 4 -> 3 root port lock 0 -> 0 aspm value 2 B PCIE ASPM LINK CTL 0 A PCIE ASPM LINK CTL 2 B PCIE ASPM LINK CAP 800 A PCIE ASPM LINK CAP 800 PeiPcieDevCtlInit Start PCIE_DCTL = 0x5120 PeiPcieDevCtlInit End PeiPcieDevCtl2Init Start PCIE_DCTL2 = 0x0006 PeiPcieDevCtlInit End PEI PcieIp Link Ctl Start PCIE_LCTL.ExtSynch.Disabled :: PCIE_LCTL = 0x2 PEI PcieIpInit End No Link Reversal : Addr E0048A30 PCIE DeEmphasis = -6dB This root port 0 is not active with HotPlug root port lock 4 -> 0 aspm value 2 B PCIE ASPM LINK CTL 0 A PCIE ASPM LINK CTL 2 B PCIE ASPM LINK CAP 800 A PCIE ASPM LINK CAP 800 PeiPcieDevCtlInit Start PCIE_DCTL = 0x5120 PeiPcieDevCtlInit End PeiPcieDevCtl2Init Start PCIE_DCTL2 = 0x0006 PeiPcieDevCtlInit End PEI PcieIp Link Ctl Start PCIE_LCTL.ExtSynch.Disabled :: PCIE_LCTL = 0x2 PEI PcieIpInit End No Link Reversal : Addr E0070A30 PCIE DeEmphasis = -6dB This root port 4 is not active with HotPlug root port lock 6 -> 0 aspm value 2 B PCIE ASPM LINK CTL 0 A PCIE ASPM LINK CTL 2 B PCIE ASPM LINK CAP 800 A PCIE ASPM LINK CAP 800 PeiPcieDevCtlInit Start PCIE_DCTL = 0x5120 PeiPcieDevCtlInit End PeiPcieDevCtl2Init Start PCIE_DCTL2 = 0x0006 PeiPcieDevCtlInit End PEI PcieIp Link Ctl Start PCIE_LCTL.ExtSynch.Disabled :: PCIE_LCTL = 0x2 PEI PcieIpInit End No Link Reversal : Addr E0080A30 PCIE DeEmphasis = -6dB This root port 6 is not active with HotPlug PcieIpInit End VTd enabled VtdBase = FED90000 [ME] Disabling ME functions: 1 (HECI-2) 4 (HECI-3) 2 (IDE-R) 3 (KT) [ME] Enabling HECI0 [ME] Disabling HECI1 [ME] Disabling HECI4 [ME] Disabling HECI2 [ME] Disabling HECI3 PmcStPgConfig : Entry ST_PG_FDIS_PMC_1 = 0x00000004 PmcStPgConfig : Exit Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6 SiInit () - End Notify: PPI Guid: 9F685891-4E6F-445C-BB9E-E57A28FA53A0, Peim notify entry point: 7FBB1C0D PchHsioOnHeciPpi start (Hsio) ME Reported CRC=0x12FD (Hsio) BIOS Hsio CRC=0x12FD Loading PEIM at 0x0007FBA5000 EntryPoint=0x0007FBA5270 SaInitDxe Start ------------------------ DXE SA Platform Policy Dump Start ----------------- ------------------------ SA PLATFORM CONFIGURATION Begin--------------- SA Clock Gating : 0 MSI Redirection Algorithm : 0 ------------------------ SA PLATFORM CONFIGURATION End--------------- ------------------------ VTD PLATFORM CONFIGURATION Begin--------------- Vtd Enable : 1 Vtd BaseAddress : FED90000 Vtd RmrrUsbBaseAddress : 3E2E0000 Vtd RmrrUsbLimitAddress : 3E2FFFFF Vtd Interrupt remapping : 1 ------------------------ VTD PLATFORM CONFIGURATION End--------------- ------------------------ SA SV MEMORY CONFIGURATION Begin--------------- EnableTagec : 0 ReserveMem : 0 ReserveStartAddr : 0x00000000 ------------------------ SA SV MEMORY CONFIGURATION End--------------- ------------------------ DXE SA Platform Policy Dump End ----------------- Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B SaInitDxe End Loading PEIM at 0x0007FB96000 EntryPoint=0x0007FB96270 Fsp PchInitEntryPoint() Start Common PchInitEntryPoint() Start ConfigureWakeEvents : Entry Enable RTC wake GPE0_STS_127_96 = 0x0000188C Value = 0x00000000 PM1_EN_STS = 0x00001800 Value = 0x04008001 ROW: ROW was not enabled GPE0_EN_127_96 = 0x0000189C Value = 0x00002800 PM_CFG2 = 0xFE00003C Value = 0x00002000 ConfigureWakeEvents : Exit Common PchInitEntryPoint() End Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Fsp PchInitEntryPoint() End Loading PEIM at 0x0007FB89000 EntryPoint=0x0007FB89270 Install PPI: 3FDDA605-A76E-4F46-AD29-12F4531B3D08 Microcode Base/Size are updated. Microcode Base: 0xFF8584B0 Microcode Size: 0x2C00 Detected 4 CPU threads Loading PEIM at 0x0007FB6E000 EntryPoint=0x0007FB6E270 The entry of FspNotificationPeim Reinstall PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 DXE IPL Entry FSP HOB is located at 0x7F83E000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: 7FBB02A2 SiInitOnEndOfPei - Start PchOnEndOfPei after memory PEI module - Start UsbEndOfInit : Entry XHCC2 = 0xE00A8044 Value = 0x83CFC68F UsbEndOfInit : Exit (WDT) EndOfPeiCallback (WDT) BootMode 2, Hob, active 0, ToV 0 PchTraceHubOnEndOfPei : Entry TraceHub Device not present PchOnEndOfPei after memory PEI module - End PmcStPgLock : Entry ST_PG_FDIS_PMC_1 = 0x80000004 PmcStPgLock : Exit SiInitOnEndOfPei - End FSP is waiting for NOTIFY FspSiliconInitApi() - [Status: 0x00000000] - End [INFO ] FSPS returned 0 [DEBUG] CBMEM entry for DIMM info: 0x7f775000 [DEBUG] 0 DIMMs found [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 3472 / 98 ms [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 0000 enabled [DEBUG] DOMAIN: 0000 scanning... [DEBUG] PCI: pci_scan_bus for bus 00 [DEBUG] PCI: 00:00.0 [8086/1980] enabled [DEBUG] PCI: 00:04.0 [8086/19a1] enabled [DEBUG] PCI: 00:05.0 [8086/19a2] enabled [DEBUG] PCI: 00:06.0 subordinate bus PCI Express [DEBUG] PCI: 00:06.0 [8086/19a3] enabled [DEBUG] PCI: 00:09.0 subordinate bus PCI Express [DEBUG] PCI: 00:09.0 [8086/19a4] enabled [DEBUG] PCI: 00:0e.0 subordinate bus PCI Express [DEBUG] PCI: 00:0e.0 [8086/19a8] enabled [DEBUG] PCI: 00:10.0 subordinate bus PCI Express [DEBUG] PCI: 00:10.0 [8086/19aa] enabled [DEBUG] PCI: 00:12.0 [8086/19ac] enabled [DEBUG] PCI: 00:14.0 [8086/19c2] enabled [DEBUG] PCI: 00:15.0 subsystem <- 8086/19d0 [DEBUG] PCI: 00:15.0 cmd <- 00 [DEBUG] PCI: 00:15.0 [8086/19d0] enabled [DEBUG] PCI: 00:16.0 subordinate bus PCI Express [DEBUG] PCI: 00:16.0 [8086/19d1] enabled [DEBUG] PCI: 00:17.0 subordinate bus PCI Express [DEBUG] PCI: 00:17.0 [8086/19d2] enabled [DEBUG] PCI: 00:18.0 [8086/19d3] enabled [DEBUG] PCI: 00:1a.0 [8086/19d8] enabled [DEBUG] PCI: 00:1a.1 [8086/19d8] enabled [DEBUG] PCI: 00:1a.2 [8086/19d8] enabled [DEBUG] PCI: 00:1c.0 [8086/19db] enabled [DEBUG] PCI: 00:1f.0 [8086/19dc] enabled [DEBUG] PCI: 00:1f.2 [8086/19de] enabled [DEBUG] PCI: 00:1f.4 [8086/19df] enabled [DEBUG] PCI: 00:1f.5 [8086/19e0] enabled [DEBUG] PCI: 00:06.0 scanning... [DEBUG] PCI: 00:06.0: No LTR support [DEBUG] PCI: pci_scan_bus for bus 01 [DEBUG] PCI: 01:00.0 [8086/19e2] enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] PCIe: Max_Payload_Size adjusted to 128 [DEBUG] PCI: 01:00.0: No LTR support [DEBUG] scan_bus: bus PCI: 00:06.0 finished in 26 msecs [DEBUG] PCI: 00:09.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] scan_bus: bus PCI: 00:09.0 finished in 4 msecs [DEBUG] PCI: 00:0e.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 03 [DEBUG] scan_bus: bus PCI: 00:0e.0 finished in 4 msecs [DEBUG] PCI: 00:10.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 04 [DEBUG] scan_bus: bus PCI: 00:10.0 finished in 4 msecs [DEBUG] PCI: 00:16.0 scanning... [DEBUG] PCI: 00:16.0: No LTR support [DEBUG] PCI: pci_scan_bus for bus 05 [DEBUG] PCI: 05:00.0 [8086/15ce] enabled [DEBUG] PCI: 05:00.1 [8086/15ce] enabled [INFO ] Enabling Common Clock Configuration [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] PCIe: Max_Payload_Size adjusted to 128 [DEBUG] PCI: 05:00.0: No LTR support [INFO ] Enabling Common Clock Configuration [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] PCIe: Max_Payload_Size adjusted to 128 [DEBUG] PCI: 05:00.1: No LTR support [DEBUG] scan_bus: bus PCI: 00:16.0 finished in 54 msecs [DEBUG] PCI: 00:17.0 scanning... [DEBUG] PCI: 00:17.0: No LTR support [DEBUG] PCI: pci_scan_bus for bus 06 [DEBUG] PCI: 06:00.0 [8086/15cf] enabled [DEBUG] PCI: 06:00.1 [8086/15cf] enabled [INFO ] Enabling Common Clock Configuration [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] PCIe: Max_Payload_Size adjusted to 128 [DEBUG] PCI: 06:00.0: No LTR support [INFO ] Enabling Common Clock Configuration [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] PCIe: Max_Payload_Size adjusted to 128 [DEBUG] PCI: 06:00.1: No LTR support [DEBUG] scan_bus: bus PCI: 00:17.0 finished in 54 msecs [DEBUG] PCI: 00:1f.0 scanning... [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs [DEBUG] PCI: 00:1f.2 scanning... [DEBUG] scan_bus: bus PCI: 00:1f.2 finished in 0 msecs [DEBUG] PCI: 00:1f.4 scanning... [DEBUG] scan_bus: bus PCI: 00:1f.4 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 368 msecs [DEBUG] scan_bus: bus Root Device finished in 385 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 400 ms [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xe0000000-0xefffffff. [DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. [DEBUG] MC MAP: TOUUD: 0x280000000 [DEBUG] MC MAP: TOLUD: 0x80000000 [DEBUG] MC MAP: TSEGMB: 0x7fe00000 [DEBUG] SMM memory location: 0x7fe00000 SMM memory size: 0x200000 [DEBUG] Adding P2SB PCR config space BAR 0xfd000000-0xfe000000. [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === [DEBUG] PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 01:00.0 18 * [0x0 - 0x3ffff] mem [DEBUG] PCI: 01:00.0 20 * [0x40000 - 0x7ffff] mem [DEBUG] PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:16.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:16.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:16.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 05:00.0 30 * [0x0 - 0x7ffff] mem [DEBUG] PCI: 05:00.1 30 * [0x80000 - 0xfffff] mem [DEBUG] PCI: 00:16.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:16.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 05:00.0 10 * [0x0 - 0x1fffff] prefmem [DEBUG] PCI: 05:00.1 10 * [0x200000 - 0x3fffff] prefmem [DEBUG] PCI: 05:00.0 20 * [0x400000 - 0x403fff] prefmem [DEBUG] PCI: 05:00.1 20 * [0x404000 - 0x407fff] prefmem [DEBUG] PCI: 00:16.0 prefmem: size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:17.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:17.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:17.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 06:00.0 30 * [0x0 - 0x7ffff] mem [DEBUG] PCI: 06:00.1 30 * [0x80000 - 0xfffff] mem [DEBUG] PCI: 00:17.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:17.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 06:00.0 10 * [0x0 - 0x1fffff] prefmem [DEBUG] PCI: 06:00.1 10 * [0x200000 - 0x3fffff] prefmem [DEBUG] PCI: 06:00.0 20 * [0x400000 - 0x403fff] prefmem [DEBUG] PCI: 06:00.1 20 * [0x404000 - 0x407fff] prefmem [DEBUG] PCI: 00:17.0 prefmem: size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] update_constraints: PCI: 00:1a.0 10 base 00000000 limit 00000007 io (fixed) [DEBUG] update_constraints: PCI: 00:1a.1 10 base 00000000 limit 00000007 io (fixed) [DEBUG] update_constraints: PCI: 00:1a.2 10 base 00000000 limit 00000007 io (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) [DEBUG] update_constraints: PCI: 00:1f.2 40 base 00001800 limit 000018ff io (fixed) [DEBUG] update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 1000, Size: 800, Tag: 100 [INFO ] * Base: 1900, Size: d6a0, Tag: 100 [INFO ] * Base: efc0, Size: 1040, Tag: 100 [DEBUG] PCI: 00:14.0 20 * [0x1000 - 0x101f] limit: 101f io [DEBUG] PCI: 00:14.0 18 * [0x1020 - 0x1027] limit: 1027 io [DEBUG] PCI: 00:14.0 1c * [0x1028 - 0x102b] limit: 102b io [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff [DEBUG] update_constraints: PCI: 00:00.0 60 base e0000000 limit efffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 48 base fed10000 limit fed17fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 01 base 00100000 limit 7fbfffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 02 base 7fc00000 limit 7fdfffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 03 base 7fe00000 limit 7fffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 27fffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 da base fd000000 limit fdffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 db base fec00000 limit fec00fff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.2 48 base fe000000 limit fe00ffff mem (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [INFO ] * Base: f0000000, Size: d000000, Tag: 200 [INFO ] * Base: fe010000, Size: bf0000, Tag: 200 [INFO ] * Base: fec01000, Size: 10f000, Tag: 200 [INFO ] * Base: fed18000, Size: 2e8000, Tag: 200 [INFO ] * Base: 280000000, Size: 7d80000000, Tag: 100200 [DEBUG] PCI: 00:16.0 24 * [0x80000000 - 0x804fffff] limit: 804fffff prefmem [DEBUG] PCI: 00:17.0 24 * [0x80600000 - 0x80afffff] limit: 80afffff prefmem [DEBUG] PCI: 00:06.0 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem [DEBUG] PCI: 00:16.0 20 * [0x80b00000 - 0x80bfffff] limit: 80bfffff mem [DEBUG] PCI: 00:17.0 20 * [0x80c00000 - 0x80cfffff] limit: 80cfffff mem [DEBUG] PCI: 00:09.0 10 * [0x80d00000 - 0x80d1ffff] limit: 80d1ffff mem [DEBUG] PCI: 00:0e.0 10 * [0x80d20000 - 0x80d3ffff] limit: 80d3ffff mem [DEBUG] PCI: 00:10.0 10 * [0x80d40000 - 0x80d5ffff] limit: 80d5ffff mem [DEBUG] PCI: 00:15.0 10 * [0x80d60000 - 0x80d6ffff] limit: 80d6ffff mem [DEBUG] PCI: 00:1f.2 10 * [0x80d70000 - 0x80d73fff] limit: 80d73fff mem [DEBUG] PCI: 00:14.0 10 * [0x80d74000 - 0x80d75fff] limit: 80d75fff mem [DEBUG] PCI: 00:18.0 10 * [0x80d76000 - 0x80d76fff] limit: 80d76fff mem [DEBUG] PCI: 00:1c.0 10 * [0x80d77000 - 0x80d77fff] limit: 80d77fff mem [DEBUG] PCI: 00:1c.0 18 * [0x80d78000 - 0x80d78fff] limit: 80d78fff mem [DEBUG] PCI: 00:1f.5 10 * [0x80d79000 - 0x80d79fff] limit: 80d79fff mem [DEBUG] PCI: 00:14.0 24 * [0x80d7a000 - 0x80d7a7ff] limit: 80d7a7ff mem [DEBUG] PCI: 00:12.0 10 * [0x80d7b000 - 0x80d7b3ff] limit: 80d7b3ff mem [DEBUG] PCI: 00:14.0 14 * [0x80d7c000 - 0x80d7c0ff] limit: 80d7c0ff mem [DEBUG] PCI: 00:1f.4 10 * [0x80d7d000 - 0x80d7d0ff] limit: 80d7d0ff mem [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done [DEBUG] PCI: 00:06.0 mem: base: 80500000 size: 100000 align: 20 gran: 20 limit: 805fffff [INFO ] PCI: 00:06.0: Resource ranges: [INFO ] * Base: 80500000, Size: 100000, Tag: 200 [DEBUG] PCI: 01:00.0 18 * [0x80500000 - 0x8053ffff] limit: 8053ffff mem [DEBUG] PCI: 01:00.0 20 * [0x80540000 - 0x8057ffff] limit: 8057ffff mem [DEBUG] PCI: 00:06.0 mem: base: 80500000 size: 100000 align: 20 gran: 20 limit: 805fffff done [DEBUG] PCI: 00:16.0 prefmem: base: 80000000 size: 500000 align: 21 gran: 20 limit: 804fffff [INFO ] PCI: 00:16.0: Resource ranges: [INFO ] * Base: 80000000, Size: 500000, Tag: 1200 [DEBUG] PCI: 05:00.0 10 * [0x80000000 - 0x801fffff] limit: 801fffff prefmem [DEBUG] PCI: 05:00.1 10 * [0x80200000 - 0x803fffff] limit: 803fffff prefmem [DEBUG] PCI: 05:00.0 20 * [0x80400000 - 0x80403fff] limit: 80403fff prefmem [DEBUG] PCI: 05:00.1 20 * [0x80404000 - 0x80407fff] limit: 80407fff prefmem [DEBUG] PCI: 00:16.0 prefmem: base: 80000000 size: 500000 align: 21 gran: 20 limit: 804fffff done [DEBUG] PCI: 00:16.0 mem: base: 80b00000 size: 100000 align: 20 gran: 20 limit: 80bfffff [INFO ] PCI: 00:16.0: Resource ranges: [INFO ] * Base: 80b00000, Size: 100000, Tag: 200 [DEBUG] PCI: 05:00.0 30 * [0x80b00000 - 0x80b7ffff] limit: 80b7ffff mem [DEBUG] PCI: 05:00.1 30 * [0x80b80000 - 0x80bfffff] limit: 80bfffff mem [DEBUG] PCI: 00:16.0 mem: base: 80b00000 size: 100000 align: 20 gran: 20 limit: 80bfffff done [DEBUG] PCI: 00:17.0 prefmem: base: 80600000 size: 500000 align: 21 gran: 20 limit: 80afffff [INFO ] PCI: 00:17.0: Resource ranges: [INFO ] * Base: 80600000, Size: 500000, Tag: 1200 [DEBUG] PCI: 06:00.0 10 * [0x80600000 - 0x807fffff] limit: 807fffff prefmem [DEBUG] PCI: 06:00.1 10 * [0x80800000 - 0x809fffff] limit: 809fffff prefmem [DEBUG] PCI: 06:00.0 20 * [0x80a00000 - 0x80a03fff] limit: 80a03fff prefmem [DEBUG] PCI: 06:00.1 20 * [0x80a04000 - 0x80a07fff] limit: 80a07fff prefmem [DEBUG] PCI: 00:17.0 prefmem: base: 80600000 size: 500000 align: 21 gran: 20 limit: 80afffff done [DEBUG] PCI: 00:17.0 mem: base: 80c00000 size: 100000 align: 20 gran: 20 limit: 80cfffff [INFO ] PCI: 00:17.0: Resource ranges: [INFO ] * Base: 80c00000, Size: 100000, Tag: 200 [DEBUG] PCI: 06:00.0 30 * [0x80c00000 - 0x80c7ffff] limit: 80c7ffff mem [DEBUG] PCI: 06:00.1 30 * [0x80c80000 - 0x80cfffff] limit: 80cfffff mem [DEBUG] PCI: 00:17.0 mem: base: 80c00000 size: 100000 align: 20 gran: 20 limit: 80cfffff done [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === [DEBUG] PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io [DEBUG] PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem [DEBUG] PCI: 00:06.0 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 bus 01 mem [DEBUG] PCI: 01:00.0 18 <- [0x0080500000 - 0x008053ffff] size 0x00040000 gran 0x12 mem64 [DEBUG] PCI: 01:00.0 20 <- [0x0080540000 - 0x008057ffff] size 0x00040000 gran 0x12 mem64 [DEBUG] PCI: 00:09.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io [DEBUG] PCI: 00:09.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem [DEBUG] PCI: 00:09.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem [DEBUG] PCI: 00:09.0 10 <- [0x0080d00000 - 0x0080d1ffff] size 0x00020000 gran 0x11 mem64 [DEBUG] PCI: 00:0e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io [DEBUG] PCI: 00:0e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem [DEBUG] PCI: 00:0e.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 03 mem [DEBUG] PCI: 00:0e.0 10 <- [0x0080d20000 - 0x0080d3ffff] size 0x00020000 gran 0x11 mem64 [DEBUG] PCI: 00:10.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io [DEBUG] PCI: 00:10.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem [DEBUG] PCI: 00:10.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 04 mem [DEBUG] PCI: 00:10.0 10 <- [0x0080d40000 - 0x0080d5ffff] size 0x00020000 gran 0x11 mem64 [DEBUG] PCI: 00:12.0 10 <- [0x0080d7b000 - 0x0080d7b3ff] size 0x00000400 gran 0x0a mem64 [DEBUG] PCI: 00:14.0 10 <- [0x0080d74000 - 0x0080d75fff] size 0x00002000 gran 0x0d mem [DEBUG] PCI: 00:14.0 14 <- [0x0080d7c000 - 0x0080d7c0ff] size 0x00000100 gran 0x08 mem [DEBUG] PCI: 00:14.0 18 <- [0x0000001020 - 0x0000001027] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:14.0 1c <- [0x0000001028 - 0x000000102b] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:14.0 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:14.0 24 <- [0x0080d7a000 - 0x0080d7a7ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 00:15.0 10 <- [0x0080d60000 - 0x0080d6ffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:16.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io [DEBUG] PCI: 00:16.0 24 <- [0x0080000000 - 0x00804fffff] size 0x00500000 gran 0x14 bus 05 prefmem [DEBUG] PCI: 00:16.0 20 <- [0x0080b00000 - 0x0080bfffff] size 0x00100000 gran 0x14 bus 05 mem [DEBUG] PCI: 05:00.0 10 <- [0x0080000000 - 0x00801fffff] size 0x00200000 gran 0x15 prefmem64 [DEBUG] PCI: 05:00.0 20 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e prefmem64 [DEBUG] PCI: 05:00.0 30 <- [0x0080b00000 - 0x0080b7ffff] size 0x00080000 gran 0x13 romem [DEBUG] PCI: 05:00.1 10 <- [0x0080200000 - 0x00803fffff] size 0x00200000 gran 0x15 prefmem64 [DEBUG] PCI: 05:00.1 20 <- [0x0080404000 - 0x0080407fff] size 0x00004000 gran 0x0e prefmem64 [DEBUG] PCI: 05:00.1 30 <- [0x0080b80000 - 0x0080bfffff] size 0x00080000 gran 0x13 romem [DEBUG] PCI: 00:17.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io [DEBUG] PCI: 00:17.0 24 <- [0x0080600000 - 0x0080afffff] size 0x00500000 gran 0x14 bus 06 prefmem [DEBUG] PCI: 00:17.0 20 <- [0x0080c00000 - 0x0080cfffff] size 0x00100000 gran 0x14 bus 06 mem [DEBUG] PCI: 06:00.0 10 <- [0x0080600000 - 0x00807fffff] size 0x00200000 gran 0x15 prefmem64 [DEBUG] PCI: 06:00.0 20 <- [0x0080a00000 - 0x0080a03fff] size 0x00004000 gran 0x0e prefmem64 [DEBUG] PCI: 06:00.0 30 <- [0x0080c00000 - 0x0080c7ffff] size 0x00080000 gran 0x13 romem [DEBUG] PCI: 06:00.1 10 <- [0x0080800000 - 0x00809fffff] size 0x00200000 gran 0x15 prefmem64 [DEBUG] PCI: 06:00.1 20 <- [0x0080a04000 - 0x0080a07fff] size 0x00004000 gran 0x0e prefmem64 [DEBUG] PCI: 06:00.1 30 <- [0x0080c80000 - 0x0080cfffff] size 0x00080000 gran 0x13 romem [DEBUG] PCI: 00:18.0 10 <- [0x0080d76000 - 0x0080d76fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:1c.0 10 <- [0x0080d77000 - 0x0080d77fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:1c.0 18 <- [0x0080d78000 - 0x0080d78fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 00:1f.2 10 <- [0x0080d70000 - 0x0080d73fff] size 0x00004000 gran 0x0e mem [DEBUG] PCI: 00:1f.4 10 <- [0x0080d7d000 - 0x0080d7d0ff] size 0x00000100 gran 0x08 mem64 [DEBUG] PCI: 00:1f.5 10 <- [0x0080d79000 - 0x0080d79fff] size 0x00001000 gran 0x0c mem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 1378 ms NotifyPhaseApi() - Begin [Phase: 00000020] FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7FBB569C ConfigureIqatUncorrectableErrorWA () Start, boot mode 0x2.. QatBusNum: 0x1 QatMemBase: 0xE0100000 Vrp2MemBase: 0xE0030000 Vrp2PciCmd: 0x0 QatPciCmd: 0x0 R_IQAT_PFIEERRUNCSTSR: 0xC00 Now R_IQAT_PFIEERRUNCSTSR: 0x0 R_IQAT_PPAERUCS: 0x400000 Now R_IQAT_PPAERUCS: 0x0 R_IQAT_PPAERCS: 0x0 ConfigureIqatUncorrectableErrorWA() End ConfigureIqatSecureRam() Start SetupImrRegion called..(0x7FD00000, 0x80000) SetupImrRegion Low = 0x1FF400 High = 0x1FFFFE00.. MchBar: 0xFED10000 MchBar: LOW read [0xFED16870] = 0x0 MchBar: LOW write [0xFED16870] = 0x801FF400 MchBar: LOW read [0xFED16870] = 0x801FF400 MchBar: HIGH read [0xFED16874] = 0x0 MchBar: HIGH write [0xFED16874] = 0x1FFFFE00 MchBar: HIGH read [0xFED16874] = 0x1FFFFE00 Allowing nCPM to READ / WRITE only MchBar: RAC read [0xFED16880] = 0x0 MchBar: RAC write [0xFED16880] = 0x4000000 MchBar: RAC read [0xFED16880] = 0x4000000 MchBar: WAC read [0xFED16888] = 0x0 MchBar: WAC write [0xFED16888] = 0x4000000 MchBar: RAC read [0xFED16888] = 0x4000000 QatBusNum: 0x1 Vrp2PciCmd: 0x0 QatPmiscBar: 0x80500000 QatPciCmd: 0x0 RamBaseAddrHi: 0x20000 RamBaseAddrLo: 0x0 RamBaseAddrHi: 0x20000 RamBaseAddrLo: 0x7FD00000 ConfigureIqatSecureRam() End NotifyPhaseApi() - End [Status: 0x00000000] [DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 342 / 0 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00.0 subsystem <- 8086/1980 [DEBUG] PCI: 00:00.0 cmd <- 07 [DEBUG] PCI: 00:04.0 subsystem <- 8086/19a1 [DEBUG] PCI: 00:04.0 cmd <- 00 [DEBUG] PCI: 00:05.0 subsystem <- 8086/19a2 [DEBUG] PCI: 00:05.0 cmd <- 04 [DEBUG] PCI: 00:06.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:06.0 cmd <- 06 [DEBUG] PCI: 00:09.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:09.0 cmd <- 02 [DEBUG] PCI: 00:0e.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:0e.0 cmd <- 02 [DEBUG] PCI: 00:10.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:10.0 cmd <- 02 [DEBUG] PCI: 00:12.0 subsystem <- 8086/19ac [DEBUG] PCI: 00:12.0 cmd <- 06 [DEBUG] PCI: 00:14.0 subsystem <- 8086/19c2 [DEBUG] PCI: 00:14.0 cmd <- 43 [DEBUG] PCI: 00:15.0 subsystem <- 8086/19d0 [DEBUG] PCI: 00:15.0 cmd <- 02 [DEBUG] PCI: 00:16.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:16.0 cmd <- 06 [DEBUG] PCI: 00:17.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:17.0 cmd <- 06 [DEBUG] PCI: 00:18.0 subsystem <- 8086/19d3 [DEBUG] PCI: 00:18.0 cmd <- 06 [DEBUG] PCI: 00:1a.0 cmd <- 05 [DEBUG] PCI: 00:1a.1 cmd <- 05 [DEBUG] PCI: 00:1a.2 cmd <- 05 [DEBUG] PCI: 00:1c.0 subsystem <- 8086/19db [DEBUG] PCI: 00:1c.0 cmd <- 06 [DEBUG] PCI: 00:1f.0 subsystem <- 8086/19dc [DEBUG] PCI: 00:1f.0 cmd <- 107 [DEBUG] PCI: 00:1f.2 subsystem <- 8086/19de [DEBUG] PCI: 00:1f.2 cmd <- 06 [DEBUG] PCI: 00:1f.4 subsystem <- 8086/19df [DEBUG] PCI: 00:1f.4 cmd <- 03 [DEBUG] PCI: 00:1f.5 subsystem <- 8086/19e0 [DEBUG] PCI: 00:1f.5 cmd <- 406 [DEBUG] PCI: 01:00.0 cmd <- 02 [DEBUG] PCI: 05:00.0 cmd <- 02 [DEBUG] PCI: 05:00.1 cmd <- 02 [DEBUG] PCI: 06:00.0 cmd <- 02 [DEBUG] PCI: 06:00.1 cmd <- 02 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 181 ms [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007fc00000 size 0x7fb40000 type 6 [DEBUG] 0x000000007fc00000 - 0x000000007fe00000 size 0x00200000 type 0 [DEBUG] 0x000000007fe00000 - 0x0000000080000000 size 0x00200000 type 6 [DEBUG] 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 [DEBUG] 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] CPU physical address size: 39 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 2/12. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x000000007fc00000 mask 0x0000007fffe00000 type 0 [DEBUG] MTRR: 1 base 0x0000000080000000 mask 0x0000007f80000000 type 0  [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled  [DEBUG] Number of Active Cores: 4 of 4 total. [INFO ] Will perform SMM setup. [INFO ] CPU: Intel(R) Atom(TM) CPU C3558R @ 2.40GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 18 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x1c in XAPIC mode. [INFO ] LAPIC 0x14 in XAPIC mode. [INFO ] LAPIC 0x8 in XAPIC mode. [INFO ] AP: slot 3 apic_id 14, MCU rev: 0x00000036 [INFO ] AP: slot 2 apic_id 1c, MCU rev: 0x00000036 [INFO ] AP: slot 1 apic_id 8, MCU rev: 0x00000036 [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1f8 memsize: 0x1f8 [DEBUG] Processing 11 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x7fe02000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f7a061b [DEBUG] Installing permanent SMM handler to 0x7fe00000 [DEBUG] smm_load_module: total_smm_space_needed 7c60, available -> 200000 [DEBUG] Loading module at 0x7fffb000 with entry 0x7fffb981. filesize: 0x1ba0 memsize: 0x5c60 [DEBUG] Processing 98 relocs. Offset value of 0x7fffb000 [DEBUG] smm_load_module: smram_start: 0x7fe00000 [DEBUG] smm_load_module: smram_end: 80000000 [DEBUG] smm_load_module: handler start 0x7fffb981 [DEBUG] smm_load_module: handler_size 68c0 [DEBUG] smm_load_module: fxsave_area 0x00000000 [DEBUG] smm_load_module: fxsave_size 0 [DEBUG] smm_load_module: CONFIG_MSEG_SIZE 0x0 [DEBUG] smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0 [DEBUG] smm_load_module: handler_mod_params.smbase = 0x7fe00000 [DEBUG] smm_load_module: per_cpu_save_state_size = 0x400 [DEBUG] smm_load_module: num_cpus = 0x4 [DEBUG] smm_load_module: total_save_state_size = 0x1000 [DEBUG] smm_load_module: cpu0 entry: 7ffeb000 [DEBUG] smm_create_map: cpus allowed in one segment 30 [DEBUG] smm_create_map: min # of segments needed 1 [DEBUG] CPU 0x0 [DEBUG] smbase 7ffeb000 entry 7fff3000 [DEBUG] ss_start 7fffac00 code_end 7fff31f8 [DEBUG] CPU 0x1 [DEBUG] smbase 7ffeac00 entry 7fff2c00 [DEBUG] ss_start 7fffa800 code_end 7fff2df8 [DEBUG] CPU 0x2 [DEBUG] smbase 7ffea800 entry 7fff2800 [DEBUG] ss_start 7fffa400 code_end 7fff29f8 [DEBUG] CPU 0x3 [DEBUG] smbase 7ffea400 entry 7fff2400 [DEBUG] ss_start 7fffa000 code_end 7fff25f8 [DEBUG] Loading module at 0x7fff3000 with entry 0x7fff3000. filesize: 0x1f8 memsize: 0x1f8 [DEBUG] Processing 11 relocs. Offset value of 0x7fff3000 [INFO ] smm_place_entry_code: smbase 7ffea400, stack_top 7fe02000 [DEBUG] SMM Module: placing smm entry code at 7fff2c00, cpu # 0x1 [DEBUG] smm_place_entry_code: copying from 7fff3000 to 7fff2c00 0x1f8 bytes [DEBUG] SMM Module: placing smm entry code at 7fff2800, cpu # 0x2 [DEBUG] smm_place_entry_code: copying from 7fff3000 to 7fff2800 0x1f8 bytes [DEBUG] SMM Module: placing smm entry code at 7fff2400, cpu # 0x3 [DEBUG] smm_place_entry_code: copying from 7fff3000 to 7fff2400 0x1f8 bytes [DEBUG] smm_module_setup_stub: stack_top = 0x7fe02000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000 [DEBUG] SMM Module: stub loaded at 7fff3000. Will call 0x7fffb981 [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1  [DEBUG] PM1_STS: WAK TMROF  [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeb000, cpu = 0 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffeac00, cpu = 1 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffea800, cpu = 2 [DEBUG] Relocation complete. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7ffea400, cpu = 3 [DEBUG] Relocation complete. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 506f1 [DEBUG] CPU: family 06, model 5f, stepping 01 [DEBUG] Init Denverton-NS SoC cores. [DEBUG] Clearing out pending MCEs [INFO ] Turbo is unavailable [INFO ] CPU #0 initialized [INFO ] Initializing CPU #2 [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device 506f1 [DEBUG] CPU: family 06, model 5f, stepping 01 [INFO ] Initializing CPU #3 [DEBUG] CPU: vendor Intel device 506f1 [DEBUG] CPU: family 06, model 5f, stepping 01 [DEBUG] Init Denverton-NS SoC cores. [DEBUG] Init Denverton-NS SoC cores. [DEBUG] Clearing out pending MCEs [DEBUG] Clearing out pending MCEs [INFO ] CPU #2 initialized [INFO ] CPU #1 initialized [DEBUG] CPU: vendor Intel device 506f1 [DEBUG] CPU: family 06, model 5f, stepping 01 [DEBUG] Init Denverton-NS SoC cores. [DEBUG] Clearing out pending MCEs [INFO ] CPU #3 initialized [INFO ] bsp_do_flight_plan done after 473 msecs. [DEBUG] cpu: frequency set to 2400 [DEBUG] Enabling SMIs. [DEBUG] CPU_CLUSTER: 0 init finished in 701 msecs [DEBUG] PCI: 00:00.0 init [DEBUG] Set BIOS_RESET_CPL [DEBUG] PCI: 00:00.0 init finished in 3 msecs [DEBUG] PCI: 00:04.0 init [DEBUG] PCI: 00:04.0 init finished in 0 msecs [DEBUG] PCI: 00:05.0 init [DEBUG] PCI: 00:05.0 init finished in 0 msecs [DEBUG] PCI: 00:12.0 init [DEBUG] PCI: 00:12.0 init finished in 0 msecs [DEBUG] PCI: 00:14.0 init [DEBUG] SATA: Initializing... [DEBUG] SATA: Controller in AHCI mode. [DEBUG] ABAR: 80D7A000 [DEBUG] PCI: 00:14.0 init finished in 10 msecs [DEBUG] PCI: 00:15.0 init [NOTE ] pch: usb_xhci_init [DEBUG] PCI: 00:15.0 init finished in 3 msecs [DEBUG] PCI: 00:18.0 init [DEBUG] PCI: 00:18.0 init finished in 0 msecs [DEBUG] PCI: 00:1a.0 init [DEBUG] PCI: 00:1a.0 init finished in 0 msecs [DEBUG] PCI: 00:1a.1 init [DEBUG] PCI: 00:1a.1 init finished in 0 msecs [DEBUG] PCI: 00:1a.2 init [DEBUG] PCI: 00:1a.2 init finished in 0 msecs [DEBUG] PCI: 00:1c.0 init [DEBUG] PCI: 00:1c.0 init finished in 0 msecs [DEBUG] PCI: 00:1f.0 init [DEBUG] pch: lpc_init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x01 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [DEBUG] INT_LINE : 255 [DEBUG] pch_pirq_init: 00:00.0 pin 0 int line 255 [DEBUG] INT_LINE : 255 [DEBUG] pch_pirq_init: 00:04.0 pin 0 int line 255 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:05.0, targ_dev PCI: 00:05.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:05.0 from A to A [DEBUG] INT_LINE : 15 [DEBUG] pch_pirq_init: 00:05.0 pin 1 int line 15 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:06.0, targ_dev PCI: 00:06.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:06.0 from A to A [DEBUG] INT_LINE : 6 [DEBUG] pch_pirq_init: 00:06.0 pin 1 int line 6 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:09.0, targ_dev PCI: 00:09.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:09.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:09.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:0e.0, targ_dev PCI: 00:0e.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:0e.0 from A to A [DEBUG] INT_LINE : 12 [DEBUG] pch_pirq_init: 00:0e.0 pin 1 int line 12 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:10.0, targ_dev PCI: 00:10.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:10.0 from C to C [DEBUG] INT_LINE : 15 [DEBUG] pch_pirq_init: 00:10.0 pin 3 int line 15 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:12.0, targ_dev PCI: 00:12.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:12.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:12.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:14.0, targ_dev PCI: 00:14.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:14.0 from A to A [DEBUG] INT_LINE : 14 [DEBUG] pch_pirq_init: 00:14.0 pin 1 int line 14 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:15.0, targ_dev PCI: 00:15.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:15.0 from A to A [DEBUG] INT_LINE : 7 [DEBUG] pch_pirq_init: 00:15.0 pin 1 int line 7 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:16.0, targ_dev PCI: 00:16.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:16.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:16.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:17.0, targ_dev PCI: 00:17.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:17.0 from A to A [DEBUG] INT_LINE : 10 [DEBUG] pch_pirq_init: 00:17.0 pin 1 int line 10 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:18.0, targ_dev PCI: 00:18.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:18.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:18.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:1a.0, targ_dev PCI: 00:1a.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:1a.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:1a.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:1a.1, targ_dev PCI: 00:1a.1: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:1a.1 from B to B [DEBUG] INT_LINE : 10 [DEBUG] pch_pirq_init: 00:1a.1 pin 2 int line 10 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:1a.2, targ_dev PCI: 00:1a.2: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:1a.2 from C to C [DEBUG] INT_LINE : 6 [DEBUG] pch_pirq_init: 00:1a.2 pin 3 int line 6 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:1c.0, targ_dev PCI: 00:1c.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:1c.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 00:1c.0 pin 1 int line 11 [DEBUG] INT_LINE : 255 [DEBUG] pch_pirq_init: 00:1f.0 pin 0 int line 255 [DEBUG] INT_LINE : 255 [DEBUG] pch_pirq_init: 00:1f.2 pin 0 int line 255 [DEBUG] dnv_get_int_line: irq_dev PCI: 00:1f.4, targ_dev PCI: 00:1f.4: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:1f.4 from A to A [DEBUG] INT_LINE : 15 [DEBUG] pch_pirq_init: 00:1f.4 pin 1 int line 15 [DEBUG] INT_LINE : 255 [DEBUG] pch_pirq_init: 00:1f.5 pin 0 int line 255 [DEBUG] dnv_get_int_line: irq_dev PCI: 01:00.0, targ_dev PCI: 01:00.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:06.0 from A to A [DEBUG] INT_LINE : 6 [DEBUG] pch_pirq_init: 01:00.0 pin 1 int line 6 [DEBUG] dnv_get_int_line: irq_dev PCI: 05:00.0, targ_dev PCI: 05:00.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:16.0 from A to A [DEBUG] INT_LINE : 11 [DEBUG] pch_pirq_init: 05:00.0 pin 1 int line 11 [DEBUG] dnv_get_int_line: irq_dev PCI: 05:00.1, targ_dev PCI: 05:00.1: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:16.0 from B to B [DEBUG] INT_LINE : 10 [DEBUG] pch_pirq_init: 05:00.1 pin 2 int line 10 [DEBUG] dnv_get_int_line: irq_dev PCI: 06:00.0, targ_dev PCI: 06:00.0: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:17.0 from A to A [DEBUG] INT_LINE : 10 [DEBUG] pch_pirq_init: 06:00.0 pin 1 int line 10 [DEBUG] dnv_get_int_line: irq_dev PCI: 06:00.1, targ_dev PCI: 06:00.1: [DEBUG] dnv_get_int_line: std swizzle PCI: 00:17.0 from B to B [DEBUG] INT_LINE : 10 [DEBUG] pch_pirq_init: 06:00.1 pin 2 int line 10 [DEBUG] PCI: 00:1f.0 init finished in 515 msecs [DEBUG] PCI: 00:1f.2 init [DEBUG] pch: pmc_soc_init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:1f.2 init finished in 9 msecs [DEBUG] PCI: 00:1f.4 init [DEBUG] PCI: 00:1f.4 init finished in 0 msecs [DEBUG] PCI: 00:1f.5 init [DEBUG] PCI: 00:1f.5 init finished in 0 msecs [DEBUG] PCI: 01:00.0 init [DEBUG] PCI: 01:00.0 init finished in 0 msecs [DEBUG] PCI: 05:00.0 init [DEBUG] PCI: 05:00.0 init finished in 0 msecs [DEBUG] PCI: 05:00.1 init [DEBUG] PCI: 05:00.1 init finished in 0 msecs [DEBUG] PCI: 06:00.0 init [DEBUG] PCI: 06:00.0 init finished in 0 msecs [DEBUG] PCI: 06:00.1 init [DEBUG] PCI: 06:00.1 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 147 / 1273 ms [DEBUG] FMAP: area SMMSTORE found @ 810000 (262144 bytes) [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [DEBUG] smm store: 4 # blocks with size 0x10000 [INFO ] SMMSTORE: Setting up SMI handler [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 0 / 22 ms [INFO ] Finalize devices... [DEBUG] PCI: 00:1f.2 final [INFO ] Devices finalized [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 10 ms [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x1e340 size 0x1e48 [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 7f739000. [DEBUG] ACPI: * FACS [DEBUG] ACPI: * DSDT [DEBUG] ACPI: * FADT [DEBUG] SCI is IRQ9 [DEBUG] ACPI: added table 1/32, length now 40 [DEBUG] ACPI: * SSDT [DEBUG] Found 1 CPU(s) with 4/4 physical/logical core(s) each. [DEBUG] PSS: 2400MHz power 17000 control 0x1800 status 0x1800 [DEBUG] PSS: 2200MHz power 15213 control 0x1600 status 0x1600 [DEBUG] PSS: 2000MHz power 13509 control 0x1400 status 0x1400 [DEBUG] PSS: 1800MHz power 11883 control 0x1200 status 0x1200 [DEBUG] PSS: 1600MHz power 10314 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 8810 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 7378 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 5989 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 4675 control 0x800 status 0x800 [DEBUG] PSS: 2400MHz power 17000 control 0x1800 status 0x1800 [DEBUG] PSS: 2200MHz power 15213 control 0x1600 status 0x1600 [DEBUG] PSS: 2000MHz power 13509 control 0x1400 status 0x1400 [DEBUG] PSS: 1800MHz power 11883 control 0x1200 status 0x1200 [DEBUG] PSS: 1600MHz power 10314 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 8810 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 7378 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 5989 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 4675 control 0x800 status 0x800 [DEBUG] PSS: 2400MHz power 17000 control 0x1800 status 0x1800 [DEBUG] PSS: 2200MHz power 15213 control 0x1600 status 0x1600 [DEBUG] PSS: 2000MHz power 13509 control 0x1400 status 0x1400 [DEBUG] PSS: 1800MHz power 11883 control 0x1200 status 0x1200 [DEBUG] PSS: 1600MHz power 10314 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 8810 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 7378 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 5989 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 4675 control 0x800 status 0x800 [DEBUG] PSS: 2400MHz power 17000 control 0x1800 status 0x1800 [DEBUG] PSS: 2200MHz power 15213 control 0x1600 status 0x1600 [DEBUG] PSS: 2000MHz power 13509 control 0x1400 status 0x1400 [DEBUG] PSS: 1800MHz power 11883 control 0x1200 status 0x1200 [DEBUG] PSS: 1600MHz power 10314 control 0x1000 status 0x1000 [DEBUG] PSS: 1400MHz power 8810 control 0xe00 status 0xe00 [DEBUG] PSS: 1200MHz power 7378 control 0xc00 status 0xc00 [DEBUG] PSS: 1000MHz power 5989 control 0xa00 status 0xa00 [DEBUG] PSS: 800MHz power 4675 control 0x800 status 0x800 [DEBUG] ACPI: added table 2/32, length now 44 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 48 [DEBUG] ACPI: * MADT [DEBUG] SCI is IRQ9 [DEBUG] ACPI: added table 4/32, length now 52 [DEBUG] current = 7f73c230 [DEBUG] ACPI: * DMAR [DEBUG] DEFVTBAR:0xfed90000 [DEBUG] ACPI: added table 5/32, length now 56 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 6/32, length now 60 [DEBUG] ACPI: * SSDT2 not generated. [DEBUG] current = 7f73c2e0 [INFO ] ACPI: done. [DEBUG] ACPI tables: 13024 bytes. [DEBUG] smbios_write_tables: 7f738000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.15-1686-gaade40c3f6' [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [DEBUG] SMBIOS tables: 617 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum b068 [DEBUG] Writing coreboot table at 0x7f75d000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-000000007f737fff: RAM [DEBUG] 4. 000000007f738000-000000007f78ffff: CONFIGURATION TABLES [DEBUG] 5. 000000007f790000-000000007f7d1fff: RAMSTAGE [DEBUG] 6. 000000007f7d2000-000000007fbfffff: CONFIGURATION TABLES [DEBUG] 7. 000000007fc00000-000000007fffffff: RESERVED [DEBUG] 8. 00000000e0000000-00000000efffffff: RESERVED [DEBUG] 9. 00000000fe000000-00000000fe00ffff: RESERVED [DEBUG] 10. 00000000fed10000-00000000fed17fff: RESERVED [DEBUG] 11. 0000000100000000-000000027fffffff: RAM [INFO ] Board ID: 82 [DEBUG] Wrote coreboot table at: 0x7f75d000, 0x424 bytes, checksum 6a5e [DEBUG] coreboot table: 1084 bytes. [DEBUG] IMD ROOT 0. 0x7fbff000 0x00001000 [DEBUG] IMD SMALL 1. 0x7fbfe000 0x00001000 [DEBUG] FSP MEMORY 2. 0x7f7fe000 0x00400000 [DEBUG] CONSOLE 3. 0x7f7de000 0x00020000 [DEBUG] TIME STAMP 4. 0x7f7dd000 0x00000910 [DEBUG] ROMSTG STCK 5. 0x7f7dc000 0x00001000 [DEBUG] AFTER CAR 6. 0x7f7d2000 0x0000a000 [DEBUG] RAMSTAGE 7. 0x7f78f000 0x00043000 [DEBUG] REFCODE 8. 0x7f776000 0x00019000 [DEBUG] MEM INFO 9. 0x7f775000 0x000003b8 [DEBUG] SMM COMBUFFER10. 0x7f765000 0x00010000 [DEBUG] COREBOOT 11. 0x7f75d000 0x00008000 [DEBUG] ACPI 12. 0x7f739000 0x00024000 [DEBUG] SMBIOS 13. 0x7f738000 0x00001000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x7fbfec00 0x00000400 [DEBUG] FSP RUNTIME 1. 0x7fbfebe0 0x00000004 [DEBUG] FMAP 2. 0x7fbfeac0 0x0000010a [DEBUG] POWER STATE 3. 0x7fbfea80 0x00000040 [DEBUG] ROMSTAGE 4. 0x7fbfea60 0x00000004 [DEBUG] ACPI GNVS 5. 0x7fbfe960 0x00000100 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 548 ms [INFO ] CBFS: Found 'fallback/payload' @0xce540 size 0xb458c [DEBUG] Checking segment from ROM address 0xff91e76c [DEBUG] Checking segment from ROM address 0xff91e788 [DEBUG] Loading segment from ROM address 0xff91e76c [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xff91e7a4 filesize 0xb4554 [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000b4554 [DEBUG] using LZMA [DEBUG] Loading segment from ROM address 0xff91e788 [DEBUG] Entry Point 0x008015e9 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 268 / 56 ms NotifyPhaseApi() - Begin [Phase: 00000040] FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: FF8AC2F3 [SPS] SpsFspReadyToBootEvent Start [SPS] Looking for SPS HOB info .. [SPS] HOB: flow 1, feature set 0x9B8004, pwr opt boot 0, cores2disable 0 [SPS] SpsFspSendHmrfpoLockRequest Start [SPS] Sending HMRFPO_LOCK to ME [HECI] Send msg: 80040007 00000205 [HECI] Got msg: 80180007 00008205 ... [SPS] SpsFspSendHmrfpoLockRequest End (Success) [SPS] SpsFspSendEndOfPost Start [SPS] Sending END_OF_POST to ME [HECI] Send msg: 80040007 00000CFF [HECI] Got msg: 80080007 00008CFF ... [SPS] SpsFspSendEndOfPost End [SPS] Disabling Global Reset capability [SPS] SpsFspReadyToBootEvent End Success Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7FBA5444 SaEndOfDxeCallback() Start SaEndOfDxeCallback() End Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7FB962FB Fsp PchFspOnEndOfDxe() Start Common PchOnEndOfDxe() Start GC = 0xFDCF000C Value = 0x00000002 Protected range 0: 0x80000000 Protected range 1: 0x80000000 Protected range 2: 0x80000000 Protected range 3: 0x80000000 Protected range 4: 0x80000000 Set LPC EISS Set SPI EISS Set LPC bios lock Set SPI bios lock PM_CFG = 0xFE000018 Value = 0x29C0002C ConfigureP2sbOnEndOfDxe() Start PCH Revision ID: 0x11 ConfigureP2sbOnEndOfDxe() End Common PchOnEndOfDxe() End Fsp PchFspOnEndOfDxe() End NotifyPhaseApi() - End [Status: 0x00000000] NotifyPhaseApi() - Begin [Phase: 000000F0] FSP End of Firmware ... Install PPI: BD44F629-EAE7-4198-87F1-39FAB0FD717E NotifyPhaseApi() - End [Status: 0x00000000] [DEBUG] HIDING HSUARTs. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 496 / 10 ms [DEBUG] Jumping to boot code at 0x008015e9(0x7f75d000) [=3h[01;01[=3h F2 or Down to enter Boot Manager Menu. ENTER to boot directly. Welcome to GRUB! erreur: aucun mode vido appropri disponible. GNU GRUB version2.04 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴커��������������������������������������읕컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴켸 Utilisez les touches ^ et v pour slectionner une entre. Appuyez sur Entre pour dmarrer le systme slectionn, e pour diter les commandes avant de dmarrer ou c pour obtenir une invite de commandes. [05;:0H *Arch Linux  Advanced options for Arch Linux                  [23;:0H  L'entre slectionne sera excute automatiquement dans 5s.  L'entre slectionne sera excute automatiquement dans 4s.  L'entre slectionne sera excute automatiquement dans 3s.  L'entre slectionne sera excute automatiquement dans 2s.  L'entre slectionne sera excute automatiquement dans 1s.  L'entre slectionne sera excute automatiquement dans 0s.  Dmarrage de Arch Linux Loading Linux linux ... Loading initial ramdisk ... erreur: aucun mode vido appropri disponible. Dmarrage en mode aveugle