coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0.19 18:39:40 UTC 2020 smm starting (log level: 7)... FMAP: base = 0xffe00000 size = 0x200000 #areas = 3 FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/romstage'croll_lock (CR)scroll_unlock CBFS: Found @ offset 80 size c39c BS: bootblock times (exec / console): total (unknown) / 29 ms PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe00000, size: 0x00010000 coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 romstage starting (log level: 7)... SMBus controller enabled Setting up static southbridge registers... done. Disabling Watchdog reboot... done. Mobile Intel(R) 82945PM Express Chipset (G)MCH capable of up to FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static northbridge registers...FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 38b80 size 680 done. Waiting for MCHBAR to come up...ok Setting up RAM controller. This mainboard supports Dual Channel Operation. Reading SPD using i2c block operation. DDR II Channel 0 Socket 0: x8DDS DIMM 0 side 0 = 512 MB DIMM 0 side 1 = 512 MB DDR II Channel 0 Socket 1: N/A DDR II Channel 1 Socket 0: N/A DDR II Channel 1 Socket 1: N/A Memory will be driven at 667MT with CAS=5 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles tWR = 5 cycles tRFC = 35 cycles Refresh: 7.8us Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz Setting Memory Frequency... CLKCFG = 0x00010043, ok (unchanged) Setting mode of operation for memory channels...Single Channel 0 only. Programming Clock Crossing...MEM=667 FSB=667... ok Setting RAM size... C0DRB = 0x20202010 C1DRB = 0x00000000 TOLUD = 0x0040 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0000 one dimm per channel config.. Initializing System Memory IO... Programming Dual Channel RCOMP Table Index: 19 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from bank size of rank 0 RAM initialization finished. Setting up Egress Port RCRB Loading port arbitration table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait for VC1 negotiation ...done.. Internal graphics: enabled Waiting for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: 0048 PCIe link training ... Detected PCIe device 1002:7149 PCIe x16 link training succeeded. PCIe device class: 030000 PCIe device is VGA. Disabling IGD. Setting up Root Complex Topology CBMEM: IMD: root @ 0x3fbff000 254 entries. IMD: root @ 0x3fbfec00 62 entries. External stage cache: IMD: root @ 0x3ffff000 254 entries. IMD: root @ 0x3fffec00 62 entries. SMM Memory Map SMRAM : 0x3fe00000 0x200000 Subregion 0: 0x3fe00000 0x100000 Subregion 1: 0x3ff00000 0x100000 Subregion 2: 0x40000000 0x0 MTRR Range: Start=3f400000 End=3f800000 (Size 400000) MTRR Range: Start=3f800000 End=3fc00000 (Size 400000) MTRR Range: Start=3fe00000 End=40000000 (Size 200000) MTRR Range: Start=ffe00000 End=0 (Size 200000) FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 48ec0 size 4c0c Decompressing stage fallback/postcar @ 0x3fbd2fc0 (35856 bytes) Loading module at 0x3fbd3000 with entry 0x3fbd3000. filesize: 0x48d0 memsize: 0x8bd0 Processing 184 relocs. Offset value of 0x3dbd3000 BS: romstage times (exec / console): total (unknown) / 271 ms coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 postcar starting (log level: 7)... FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 21500 size 13e85 Decompressing stage fallback/ramstage @ 0x3fb97fc0 (237040 bytes) Loading module at 0x3fb98000 with entry 0x3fb98000. filesize: 0x2b090 memsize: 0x39db0 Processing 2814 relocs. Offset value of 0x3ed98000 BS: postcar times (exec / console): total (unknown) / 38 ms coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 ramstage starting (log level: 7)... Normal boot Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/27a0] enabled PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/27a1] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. PCI: Static device PCI: 00:02.1 not found, disabling it. PCI: 00:1b.0 [8086/27d8] enabled PCI: 00:1c.0 [8086/27d0] enabled PCI: 00:1c.1 [8086/27d2] enabled PCI: 00:1c.2 [8086/27d4] enabled PCI: 00:1c.3 [8086/27d6] enabled PCI: 00:1c.4: Disabling device PCI: 00:1c.5: Disabling device PCI: 00:1d.0 [8086/27c8] enabled PCI: 00:1d.1 [8086/27c9] enabled PCI: 00:1d.2 [8086/27ca] enabled PCI: 00:1d.3 [8086/27cb] enabled PCI: 00:1d.7 [8086/27cc] enabled PCI: 00:1e.0 [8086/2448] enabled PCI: 00:1e.2: Disabling device PCI: 00:1e.2: Disabling device PCI: 00:1e.2 [8086/27de] disabled PCI: 00:1e.3: Disabling device PCI: 00:1e.3: Disabling device PCI: 00:1e.3 [8086/27dd] disabled PCI: 00:1f.0 [8086/27b9] enabled PCI: 00:1f.1 [8086/27df] enabled Set SATA mode early Set SATA mode early PCI: 00:1f.2 [8086/27c5] enabled PCI: 00:1f.3 [8086/27da] enabled PCI: Leftover static devices: PCI: 00:02.0 PCI: 00:02.1 PCI: 00:1c.4 PCI: 00:1c.5 PCI: Check your devicetree.cb. PCI: 00:01.0 scanning... PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/7149] enabled PCIe: Max_Payload_Size adjusted to 128 Failed to enable LTR for dev = PCI: 01:00.0 scan_bus: bus PCI: 00:01.0 finished in 13 msecs PCI: 00:1c.0 scanning... PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [8086/109a] enabled scan_bus: bus PCI: 00:1c.0 finished in 5 msecs PCI: 00:1c.1 scanning... PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/4227] enabled scan_bus: bus PCI: 00:1c.1 finished in 5 msecs PCI: 00:1c.2 scanning... PCI: pci_scan_bus for bus 04 scan_bus: bus PCI: 00:1c.2 finished in 2 msecs PCI: 00:1c.3 scanning... PCI: pci_scan_bus for bus 05 scan_bus: bus PCI: 00:1c.3 finished in 2 msecs PCI: 00:1e.0 scanning... PCI: pci_scan_bus for bus 06 PCI: 06:00.0 [104c/ac56] enabled scan_bus: bus PCI: 00:1e.0 finished in 5 msecs PCI: 00:1f.0 scanning... PMH7: ID 03 Revision 10 PNP: 00ff.1 enabled H8: EC Firmware ID 79HT50WW-3.4, Version 7.01A No CMOS option 'usb_always_on'. H8: BDC installed H8: WWAN detection not implemented. Assuming WWAN installed No CMOS option 'fn_ctrl_swap'. PNP: 00ff.2 enabled PNP: 164e.2 enabled PNP: 164e.3 disabled PNP: 164e.7 enabled PNP: 164e.19 enabled PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.7 enabled PNP: 002e.a disabled scan_bus: bus PCI: 00:1f.0 finished in 51 msecs PCI: 00:1f.3 scanning... bus: PCI: 00:1f.3[0]->I2C: 01:69 enabled bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled scan_bus: bus PCI: 00:1f.3 finished in 33 msecs scan_bus: bus DOMAIN: 0000 finished in 279 msecs scan_bus: bus Root Device finished in 290 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 289 ms found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... pci_tolm: 0xffffffff TSEG decoded, subtracting 2M Unused RAM between cbmem_top and TOM: 0x800K Available memory: 1044480K (1020M) Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. read_res: after pci_get_resource: bridge_ctrl f000ff53 read_res: after compact_resources: bridge_ctrl f000ff53 PNP: 00ff.1 missing read_resources PNP: 00ff.2 missing read_resources Done reading resources. skipping PNP: 00ff.2@60 fixed resource, size=0! skipping PNP: 00ff.2@62 fixed resource, size=0! skipping PNP: 00ff.2@64 fixed resource, size=0! skipping PNP: 00ff.2@66 fixed resource, size=0! Setting resources... DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem DOMAIN: 0000 04 <- [0x00000c0000 - 0x003fffffff] size 0x3ff40000 gran 0x00 mem DOMAIN: 0000 06 <- [0x003fe00000 - 0x003fffffff] size 0x00200000 gran 0x00 mem DOMAIN: 0000 07 <- [0x003fc00000 - 0x003fdfffff] size 0x00200000 gran 0x00 mem PCI: 00:01.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00e0000000 - 0x00e7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00ec100000 - 0x00ec1fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x00e0000000 - 0x00e7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 01:00.0 14 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 18 <- [0x00ec120000 - 0x00ec12ffff] size 0x00010000 gran 0x10 mem PCI: 01:00.0 30 <- [0x00ec100000 - 0x00ec11ffff] size 0x00020000 gran 0x11 romem PCI: 00:1b.0 10 <- [0x00ec400000 - 0x00ec403fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1c.0 20 <- [0x00ec200000 - 0x00ec2fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x00ec200000 - 0x00ec21ffff] size 0x00020000 gran 0x11 mem PCI: 02:00.0 18 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:1c.1 20 <- [0x00ec300000 - 0x00ec3fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00ec300000 - 0x00ec300fff] size 0x00001000 gran 0x0c mem PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:1d.0 20 <- [0x0000006000 - 0x000000601f] size 0x00000020 gran 0x05 io PCI: 00:1d.1 20 <- [0x0000006020 - 0x000000603f] size 0x00000020 gran 0x05 io PCI: 00:1d.2 20 <- [0x0000006040 - 0x000000605f] size 0x00000020 gran 0x05 io PCI: 00:1d.3 20 <- [0x0000006060 - 0x000000607f] size 0x00000020 gran 0x05 io PCI: 00:1d.7 10 <- [0x00ec404000 - 0x00ec4043ff] size 0x00000400 gran 0x0a mem PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 06 io PCI: 00:1e.0 24 <- [0x00ea100000 - 0x00ec0fffff] size 0x02000000 gran 0x14 bus 06 prefmem PCI: 00:1e.0 20 <- [0x00e8000000 - 0x00ea0fffff] size 0x02100000 gran 0x14 bus 06 mem PCI: 06:00.0 10 <- [0x00ea000000 - 0x00ea000fff] size 0x00001000 gran 0x0c mem PCI: 06:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io PCI: 06:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io PCI: 06:00.0 1c <- [0x00ea100000 - 0x00ec0fffff] size 0x02000000 gran 0x0c prefmem PCI: 06:00.0 24 <- [0x00e8000000 - 0x00e9ffffff] size 0x02000000 gran 0x0c mem PNP: 00ff.1 missing set_resources PNP: 00ff.2 missing set_resources PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned in devicetree ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned in devicetree ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned in devicetree PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned in devicetree PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.1 60 <- [0x00000003bc - 0x00000003c3] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned in devicetree PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned in devicetree PCI: 00:1f.1 10 <- [0x00000060b0 - 0x00000060b7] size 0x00000008 gran 0x03 io PCI: 00:1f.1 14 <- [0x00000060d0 - 0x00000060d3] size 0x00000004 gran 0x02 io PCI: 00:1f.1 18 <- [0x00000060b8 - 0x00000060bf] size 0x00000008 gran 0x03 io PCI: 00:1f.1 1c <- [0x00000060d4 - 0x00000060d7] size 0x00000004 gran 0x02 io PCI: 00:1f.1 20 <- [0x00000060a0 - 0x00000060af] size 0x00000010 gran 0x04 io PCI: 00:1f.2 10 <- [0x00000060c0 - 0x00000060c7] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x00000060d8 - 0x00000060db] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x00000060c8 - 0x00000060cf] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x00000060dc - 0x00000060df] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000006080 - 0x000000609f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00ec405000 - 0x00ec4053ff] size 0x00000400 gran 0x0a mem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 2 / 562 ms Enabling resources... PCI: 00:00.0 subsystem <- 17aa/2015 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001b PCI: 00:01.0 cmd <- 07 PCI: 00:1b.0 subsystem <- 17aa/2010 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0013 PCI: 00:1c.0 subsystem <- 17aa/2001 PCI: 00:1c.0 cmd <- 107 PCI: 00:1c.1 bridge ctrl <- 0013 PCI: 00:1c.1 subsystem <- 8086/27d2 PCI: 00:1c.1 cmd <- 106 PCI: 00:1c.2 bridge ctrl <- 0013 PCI: 00:1c.2 subsystem <- 8086/27d4 PCI: 00:1c.2 cmd <- 100 PCI: 00:1c.3 bridge ctrl <- 0013 PCI: 00:1c.3 subsystem <- 8086/27d6 PCI: 00:1c.3 cmd <- 100 PCI: 00:1d.0 subsystem <- 17aa/200a PCI: 00:1d.0 cmd <- 01 PCI: 00:1d.1 subsystem <- 17aa/200a PCI: 00:1d.1 cmd <- 01 PCI: 00:1d.2 subsystem <- 17aa/200a PCI: 00:1d.2 cmd <- 01 PCI: 00:1d.3 subsystem <- 17aa/200a PCI: 00:1d.3 cmd <- 01 PCI: 00:1d.7 subsystem <- 17aa/200b PCI: 00:1d.7 cmd <- 102 PCI: 00:1e.0 bridge ctrl <- 0013 PCI: 00:1e.0 subsystem <- 8086/2448 PCI: 00:1e.0 cmd <- 107 PCI: 00:1f.0 subsystem <- 8086/27b9 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.1 subsystem <- 17aa/200c PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 subsystem <- 17aa/200d PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 subsystem <- 8086/27da PCI: 00:1f.3 cmd <- 101 PCI: 01:00.0 subsystem <- 17aa/20a4 PCI: 01:00.0 cmd <- 03 PCI: 02:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 02 PCI: 06:00.0 bridge ctrl <- 0143 bridge_ctrl f000ff53 PCI: 06:00.0 subsystem <- 17aa/2012 PCI: 06:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 130 ms Initializing devices... Root Device init Root Device init finished in 0 msecs CPU_CLUSTER: 0 init FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset c480 size 15000 microcode: sig=0x6f2 pf=0x20 revision=0x0 microcode: updated to revision 0x5c date=2010-10-02 MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000003fc00000 size 0x3fb40000 type 6 0x000000003fc00000 - 0x00000000e0000000 size 0xa0400000 type 0 0x00000000e0000000 - 0x00000000e8000000 size 0x08000000 type 1 0x00000000e8000000 - 0x0000000100000000 size 0x18000000 type 0 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 7/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6 MTRR: 1 base 0x000000003fc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff8000000 type 1 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU has 2 cores. Setting up SMI for CPU Will perform SMM setup. CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. Waiting for 2nd SIPI to complete...done. AP: slot 1 apic_id 1. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 Unable to locate Global NVS SMM Module: stub loaded at 0x00038000. Will call 0x3fbab893(0x00000000) Installing SMM handler to 0x3fe00000 Loading module at 0x3fe10000 with entry 0x3fe1168f. filesize: 0x3c58 memsize: 0x7cc8 Processing 238 relocs. Offset value of 0x3fe10000 Loading module at 0x3fe08000 with entry 0x3fe08000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x3fe08000 SMM Module: placing jmp sequence at 0x3fe07c00 rel16 0x03fd Unable to locate Global NVS SMM Module: stub loaded at 0x3fe08000. Will call 0x3fe1168f(0x00000000) Initializing southbridge SMI... New SMBASE 0x3fe00000 In relocation handler: cpu 0 New SMBASE=0x3fe00000 Relocation complete. IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked New SMBASE 0x3fdffc00 In relocation handler: cpu 1 New SMBASE=0x3fdffc00 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 6f2 CPU: family 06, model 0f, stepping 02 Enabling cache CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. Setting up local APIC... apic_id: 0x00 done. CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device 6f2 CPU: family 06, model 0f, stepping 02 Enabling cache CPU: Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz. Setting up local APIC... apic_id: 0x01 done. CPU #1 initialized CPU 1 going down... bsp_do_flight_plan done after 160 msecs. Initializing southbridge SMI... SMI_STS: GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO0 ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 TCO_STS: Locking SMM. CPU_CLUSTER: 0 init finished in 367 msecs PCI: 00:1b.0 init Azalia: codec type: Azalia Azalia: base = ec400000 Azalia: codec_mask = 03 Azalia: Initializing codec #1 Azalia: codec viddid: 14f12bfa Azalia: No verb! Azalia: Initializing codec #0 Azalia: codec viddid: 11d41981 Azalia: verb_size: 44 Azalia: verb loaded. PCI: 00:1b.0 init finished in 28 msecs PCI: 00:1c.0 init Initializing ICH7 PCIe bridge. PCI: 00:1c.0 init finished in 2 msecs PCI: 00:1c.1 init Initializing ICH7 PCIe bridge. PCI: 00:1c.1 init finished in 2 msecs PCI: 00:1c.2 init Initializing ICH7 PCIe bridge. PCI: 00:1c.2 init finished in 2 msecs PCI: 00:1c.3 init Initializing ICH7 PCIe bridge. PCI: 00:1c.3 init finished in 2 msecs PCI: 00:1d.0 init UHCI: Setting up controller.. done. PCI: 00:1d.0 init finished in 3 msecs PCI: 00:1d.1 init UHCI: Setting up controller.. done. PCI: 00:1d.1 init finished in 3 msecs PCI: 00:1d.2 init UHCI: Setting up controller.. done. PCI: 00:1d.2 init finished in 3 msecs PCI: 00:1d.3 init UHCI: Setting up controller.. done. PCI: 00:1d.3 init finished in 3 msecs PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1d.7 init finished in 3 msecs PCI: 00:1e.0 init PCI: 00:1e.0 init finished in 0 msecs PCI: 00:1f.0 init i82801gx: lpc_init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 No CMOS option 'power_on_after_fail'. Set power on after power failure. NMI sources enabled. rtc_failed = 0x0 RTC Init Disabling ACPI via APMC. coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... SMI#: ACPI disabled. APMC done. PCI: 00:1f.0 init finished in 40 msecs PCI: 00:1f.1 init i82801gx_ide: initializing... PCI: 00:1f.1 init finished in 2 msecs PCI: 00:1f.2 init i82801gx_sata: initializing... SATA controller in AHCI mode. PCI: 00:1f.2 init finished in 5 msecs PCI: 01:00.0 init PCI: 01:00.0 init finished in 0 msecs PCI: 02:00.0 init PCI: 02:00.0 init finished in 0 msecs PCI: 03:00.0 init PCI: 03:00.0 init finished in 0 msecs PCI: 06:00.0 init Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller PCI: 06:00.0 init finished in 5 msecs PNP: 00ff.2 init PNP: 00ff.2 init finished in 0 msecs PNP: 164e.2 init PNP: 164e.2 init finished in 0 msecs PNP: 164e.7 init PNP: 164e.7 init finished in 0 msecs PNP: 164e.19 init PNP: 164e.19 init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:69 init Changing 12 of the 12 ck505 config bytes. I2C: 01:69 init finished in 30 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:54 init I2C: 01:54 init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:55 init I2C: 01:55 init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:56 init I2C: 01:56 init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:57 init I2C: 01:57 init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:5c init Locking EEPROM RFID init EEPROM done I2C: 01:5c init finished in 25 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:5d init I2C: 01:5d init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:5e init I2C: 01:5e init finished in 0 msecs smbus: PCI: 00:1f.3[0]->I2C: 01:5f init I2C: 01:5f init finished in 0 msecs Devices initialized BS: BS_DEV_INIT run times (exec / console): 143 / 581 ms Finalize devices... PCI: 00:1f.0 final Manufacturer: ef SF: Detected ef 3015 with sector size 0x1000, total 0x200000 Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 12 ms Wrote the mp table end at: 0x000f0010 - 0x000f01bc Wrote the mp table end at: 0x3fb7e010 - 0x3fb7e1bc MP table: 444 bytes. FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 358c0 size 3138 FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 3fb5a000. ACPI: * FACS ACPI: * DSDT coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 2 core(s) each. clocks between 1000 and 1833 MHz. adding 3 P-States between busratio 6 and b, incl. P0 PSS: 1833MHz power 35000 control 0xb25 status 0xb25 PSS: 1333MHz power 30000 control 0x81c status 0x81c PSS: 1000MHz power 25000 control 0x613 status 0x613 clocks between 1000 and 1833 MHz. adding 3 P-States between busratio 6 and b, incl. P0 PSS: 1833MHz power 35000 control 0xb25 status 0xb25 PSS: 1333MHz power 30000 control 0x81c status 0x81c PSS: 1000MHz power 25000 control 0x613 status 0x613 Generating ACPI PIRQ entries FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'pci1002,7149.rom' CBFS: Found @ offset 39240 size fc00 In CBFS, ROM address for PCI: 01:00.0 = 0xffe39488 PCI: 01:00.0: Missing ACPI scope ACPI: * H8 H8: BDC installed H8: WWAN detection not implemented. Assuming WWAN installed ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * MADT ACPI: added table 4/32, length now 52 current = 3fb5dc70 ACPI: * HPET ACPI: added table 5/32, length now 56 FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'pci1002,7149.rom' CBFS: Found @ offset 39240 size fc00 In CBFS, ROM address for PCI: 01:00.0 = 0xffe39488 Copying VBIOS image from 0xffe39488 ACPI: * VFCT at 3fb5dcb0 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 80160 bytes. smbios_write_tables: 3fb59000 coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 smm starting (log level: 7)... GPI (mask 1000) SMBIOS tables: 610 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d026 Writing coreboot table at 0x3fb7f000 FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 38b80 size 680 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000003fb58fff: RAM 3. 000000003fb59000-000000003fb97fff: CONFIGURATION TABLES 4. 000000003fb98000-000000003fbd1fff: RAMSTAGE 5. 000000003fbd2000-000000003fbfffff: CONFIGURATION TABLES 6. 000000003fc00000-000000003fffffff: RESERVED 7. 00000000f0000000-00000000f3ffffff: RESERVED FMAP: area COREBOOT found @ 200 (2096640 bytes) Wrote coreboot table at: 0x3fb7f000, 0x9a0 bytes, checksum f776 coreboot table: 2488 bytes. IMD ROOT 0. 0x3fbff000 0x00001000 IMD SMALL 1. 0x3fbfe000 0x00001000 CONSOLE 2. 0x3fbde000 0x00020000 TIME STAMP 3. 0x3fbdd000 0x00000910 ROMSTG STCK 4. 0x3fbdc000 0x00001000 AFTER CAR 5. 0x3fbd2000 0x0000a000 RAMSTAGE 6. 0x3fb97000 0x0003b000 SMM BACKUP 7. 0x3fb87000 0x00010000 COREBOOT 8. 0x3fb7f000 0x00008000 SMP TABLE 9. 0x3fb7e000 0x00001000 ACPI 10. 0x3fb5a000 0x00024000 SMBIOS 11. 0x3fb59000 0x00000800 IMD small region: IMD ROOT 0. 0x3fbfec00 0x00000400 FMAP 1. 0x3fbfeb40 0x000000b6 ROMSTAGE 2. 0x3fbfeb20 0x00000004 ACPI GNVS 3. 0x3fbfea20 0x00000100 BS: BS_WRITE_TABLES run times (exec / console): 420 / 306 ms FMAP: area COREBOOT found @ 200 (2096640 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 6b640 size 1112a Checking segment from ROM address 0xffe6b878 Checking segment from ROM address 0xffe6b894 Loading segment from ROM address 0xffe6b878 code (compression=1) New segment dstaddr 0x000df980 memsize 0x20680 srcaddr 0xffe6b8b0 filesize 0x110f2 Loading Segment: addr: 0x000df980 memsz: 0x0000000000020680 filesz: 0x00000000000110f2 using LZMA Loading segment from ROM address 0xffe6b894 Entry Point 0x000fd26a BS: BS_PAYLOAD_LOAD run times (exec / console): 42 / 48 ms ICH-NM10-PCH: watchdog disabled Jumping to boot code at 0x000fd26a(0x3fb7f000) SeaBIOS (version rel-1.13.0-45-g6ada228) BUILD: gcc: (coreboot toolchain v5b7b7c2cc2 2020-06-24) 8.3.0 binutils: (GNU Binutils) 2.33.1 SeaBIOS (version rel-1.13.0-45-g6ada228) BUILD: gcc: (coreboot toolchain v5b7b7c2cc2 2020-06-24) 8.3.0 binutils: (GNU Binutils) 2.33.1 Found coreboot cbmem console @ 3fbde000 Found mainboard LENOVO ThinkPad T60 Relocating init from 0x000e10a0 to 0x3fb0bc20 (size 54080) Found CBFS header at 0xffe00238 multiboot: eax=3fbc29a0, ebx=3fbc2964 Found 21 PCI devices (max PCI bus is 06) Copying SMBIOS entry point from 0x3fb59000 to 0x000f6280 Copying ACPI RSDP from 0x3fb5a000 to 0x000f6250 Copying MPTABLE from 0x3fb7e000/3fb7e010 to 0x000f6090 table(50434146)=0x3fb5d3d0 (via xsdt) Using pmtimer, ioport 0x508 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.13.0-45-g6ada228) Machine UUID a0a8ed00-48ef-11cb-ae8e-ee12dbd8e760 EHCI init on dev 00:1d.7 (regs=0xec404020) UHCI init on dev 00:1d.0 (io=6000) UHCI init on dev 00:1d.1 (io=6020) UHCI init on dev 00:1d.2 (io=6040) UHCI init on dev 00:1d.3 (io=6060) ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9) ATA controller 2 at 170/374/0 (irq 15 dev f9) AHCI controller at 00:1f.2, iobase 0xec405000, irq 0 Searching bootorder for: HALT Found 0 lpt ports Found 2 serial ports Searching bootorder for: /rom@img/memtest Searching bootorder for: /rom@img/tint Searching bootorder for: /rom@img/nvramcui Searching bootorder for: /rom@img/coreinfo Initialized USB HUB (0 ports used) PS2 keyboard initialized All threads complete. Scan for option roms Press ESC for boot menu. Select boot device: 1. Payload [memtest] 2. Payload [tint] 3. Payload [nvramcui] 4. Payload [coreinfo] Searching bootorder for: HALT Space available for UMB: d0000-ed000, f5aa0-f6030 Returned 262144 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000003fb59000 = 1 RAM 4: 000000003fb59000 - 0000000040000000 = 2 RESERVED 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED enter handle_19: NULL Booting from CBFS... Run img/memtest Calling addr 0x00010000 INE_SCROLL;24r Memtest86+ 5.01 coreboot 002| Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz CLK: 1829 MHz (X64 Mode) | Pass 0% L1 Cache: 32K 25757 MB/s | Test 23% ######## L2 Cache: 2048K 11952 MB/s | Test #3 [Moving inversions, 1s & 0s Parallel] L3 Cache: None | Testing: 0K - 32M Halting... 1019M Memory : 1019M 2320 MB/s | Pattern: ffffffff R | Time: 0:00:02 coreboot-4.12-1535-g4aac953665 Sun Jul 19 18:39:40 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0.| RAM: 332 MHz (DDR2-665) - BCLK: 166 FMAP: base = 0xffe00000 size = 0x200000 #areas = 3CAS 5-5-5-15 @ 64-bit Mode FMAP: area COREBOOT found @ 200 (2096640 bytes) 0 Errors: 0 CBFS: Locating 'fallback/romstage'-------------------------------------------- CBFS: Found @ offset 80 size c39c BS: bootblock times (exec / console): total (unknown) / 29 ms PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe00000, size: 0x00010000 - Slot 0 : 1024 MB DDR2-666 - SK Hynix HYMP512S64EP8-Y5