coreboot-4.12-406-g87e36c442e Mon Jun  1 19:06:28 UTC 2020 bootblock starting (log level: 8)...
FMAP: Found "FLASH" version 1.1 at 0x0.
FMAP: base = 0xffe00000 size = 0x200000 #areas = 3
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'coreboot-stages'
CBFS: 'coreboot-stages' not found.
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size c39c
BS: bootblock times (exec / console): total (unknown) / 39 ms
PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe00000, size: 0x00010000


coreboot-4.12-406-g87e36c442e Mon Jun  1 19:06:28 UTC 2020 romstage starting (log level: 8)...
SMBus controller enabled
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.

Mobile Intel(R) 82945PM Express Chipset
(G)MCH capable of up to FSB 800 MHz
(G)MCH capable of up to DDR2-667
Setting up static northbridge registers...FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 38380 size 680
 done.
Waiting for MCHBAR to come up...ok
Setting up RAM controller.
This mainboard supports Dual Channel Operation.
Reading SPD using i2c block operation.
DDR II Channel 0 Socket 0: x8DDS
DIMM 0 side 0 = 512 MB
DIMM 0 side 1 = 512 MB
DDR II Channel 0 Socket 1: N/A
Reading SPD using i2c block operation.
DDR II Channel 1 Socket 0: x8DDS
DIMM 2 side 0 = 1024 MB
DIMM 2 side 1 = 1024 MB
DDR II Channel 1 Socket 1: N/A
Memory will be driven at 667MT with CAS=5 clocks
tRAS = 15 cycles
tRP  = 5 cycles
tRCD = 5 cycles
tWR  = 5 cycles
tRFC = 43 cycles
Refresh: 7.8us
Setting Graphics Frequency...
FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz
Setting Memory Frequency... CLKCFG = 0x00010023, CLKCFG = 0x00010043, ok
Setting mode of operation for memory channels...Dual Channel Asymmetric.
Programming Clock Crossing...MEM=667 FSB=667... ok
Setting RAM size...
C0DRB = 0x20202010
C1DRB = 0x60606040
TOLUD = 0x00c0
Setting row attributes...
C0DRA = 0x0033
C1DRA = 0x0033
DIMM2 has 8 banks.
one dimm per channel config..
Initializing System Memory IO...
Programming Dual Channel RCOMP
Table Index: 18
Programming DLL Timings...
Enabling System Memory IO...
jedec enable sequence: bank 0
jedec enable sequence: bank 1
bankaddr from bank size of rank 0
jedec enable sequence: bank 4
bankaddr from bank size of rank 1
jedec enable sequence: bank 5
bankaddr from bank size of rank 4
receive_enable_autoconfig() for channel 0
  find_strobes_low()
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  find_strobes_edge()
    set_receive_enable() medium=0x1, coarse=0x5
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  add_quarter_clock() mediumcoarse=15 fine=f2
    set_receive_enable() medium=0x3, coarse=0x5
  find_preamble()
    set_receive_enable() medium=0x3, coarse=0x4
    set_receive_enable() medium=0x3, coarse=0x3
  add_quarter_clock() mediumcoarse=0f fine=72
  normalize()
    set_receive_enable() medium=0x0, coarse=0x4
receive_enable_autoconfig() for channel 1
  find_strobes_low()
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  find_strobes_edge()
    set_receive_enable() medium=0x1, coarse=0x5
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  add_quarter_clock() mediumcoarse=15 fine=f1
    set_receive_enable() medium=0x3, coarse=0x5
  find_preamble()
    set_receive_enable() medium=0x3, coarse=0x4
    set_receive_enable() medium=0x3, coarse=0x3
  add_quarter_clock() mediumcoarse=0f fine=71
  normalize()
    set_receive_enable() medium=0x0, coarse=0x4
RAM initialization finished.
Setting up Egress Port RCRB
Loading port arbitration table ...ok
Wait for VC1 negotiation ...ok
Setting up DMI RCRB
Wait for VC1 negotiation ...done..
Internal graphics: enabled
Waiting for DMI hardware...ok
Enabling PCI Express x16 Link
SLOTSTS: 0048
PCIe link training ... Detected PCIe device 1002:7149
PCIe x16 link training succeeded.
PCIe device class: 030000
PCIe device is VGA. Disabling IGD.
Setting up Root Complex Topology
CBMEM:
IMD: root @ 0xbfbff000 254 entries.
IMD: root @ 0xbfbfec00 62 entries.
External stage cache:
IMD: root @ 0xbffff000 254 entries.
IMD: root @ 0xbfffec00 62 entries.
SMM Memory Map
SMRAM       : 0xbfe00000 0x200000
 Subregion 0: 0xbfe00000 0x100000
 Subregion 1: 0xbff00000 0x100000
 Subregion 2: 0xc0000000 0x0
MTRR Range: Start=bf400000 End=bf800000 (Size 400000)
MTRR Range: Start=bf800000 End=bfc00000 (Size 400000)
MTRR Range: Start=bfe00000 End=c0000000 (Size 200000)
MTRR Range: Start=ffe00000 End=0 (Size 200000)
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 486c0 size 4ca0
Decompressing stage fallback/postcar @ 0xbfbd2fc0 (35920 bytes)
Loading module at 0xbfbd3000 with entry 0xbfbd3000. filesize: 0x4910 memsize: 0x8c10
Processing 205 relocs. Offset value of 0xbdbd3000
BS: romstage times (exec / console): total (unknown) / 410 ms


coreboot-4.12-406-g87e36c442e Mon Jun  1 19:06:28 UTC 2020 postcar starting (log level: 7)...
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 21500 size 135c3
Decompressing stage fallback/ramstage @ 0xbfb9afc0 (224784 bytes)
Loading module at 0xbfb9b000 with entry 0xbfb9b000. filesize: 0x28050 memsize: 0x36dd0
Processing 2835 relocs. Offset value of 0xbed9b000
BS: postcar times (exec / console): total (unknown) / 38 ms


coreboot-4.12-406-g87e36c442e Mon Jun  1 19:06:28 UTC 2020 ramstage starting (log level: 7)...
Normal boot
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/27a0] enabled
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/27a1] enabled
PCI: Static device PCI: 00:02.0 not found, disabling it.
PCI: Static device PCI: 00:02.1 not found, disabling it.
PCI: 00:1b.0 [8086/27d8] enabled
PCI: 00:1c.0 [8086/27d0] enabled
PCI: 00:1c.1 [8086/27d2] enabled
PCI: 00:1c.2 [8086/27d4] enabled
PCI: 00:1c.3 [8086/27d6] enabled
PCI: 00:1c.4: Disabling device
PCI: 00:1c.5: Disabling device
PCI: 00:1d.0 [8086/27c8] enabled
PCI: 00:1d.1 [8086/27c9] enabled
PCI: 00:1d.2 [8086/27ca] enabled
PCI: 00:1d.3 [8086/27cb] enabled
PCI: 00:1d.7 [8086/27cc] enabled
PCI: 00:1e.0 [8086/2448] enabled
PCI: 00:1e.2: Disabling device
PCI: 00:1e.2: Disabling device
PCI: 00:1e.2 [8086/27de] disabled
PCI: 00:1e.3: Disabling device
PCI: 00:1e.3: Disabling device
PCI: 00:1e.3 [8086/27dd] disabled
PCI: 00:1f.0 [8086/27b9] enabled
PCI: 00:1f.1 [8086/27df] enabled
Set SATA mode early
Set SATA mode early
PCI: 00:1f.2 [8086/27c5] enabled
PCI: 00:1f.3 [8086/27da] enabled
PCI: Leftover static devices:
PCI: 00:02.0
PCI: 00:02.1
PCI: 00:1c.4
PCI: 00:1c.5
PCI: Check your devicetree.cb.
PCI: 00:01.0 scanning...
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1002/7149] enabled
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
Failed to enable LTR for dev = PCI: 01:00.0
scan_bus: bus PCI: 00:01.0 finished in 19 msecs
PCI: 00:1c.0 scanning...
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/109a] enabled
scan_bus: bus PCI: 00:1c.0 finished in 5 msecs
PCI: 00:1c.1 scanning...
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [8086/4227] enabled
scan_bus: bus PCI: 00:1c.1 finished in 5 msecs
PCI: 00:1c.2 scanning...
PCI: pci_scan_bus for bus 04
scan_bus: bus PCI: 00:1c.2 finished in 2 msecs
PCI: 00:1c.3 scanning...
PCI: pci_scan_bus for bus 05
scan_bus: bus PCI: 00:1c.3 finished in 2 msecs
PCI: 00:1e.0 scanning...
PCI: pci_scan_bus for bus 06
PCI: 06:00.0 [104c/ac56] enabled
scan_bus: bus PCI: 00:1e.0 finished in 5 msecs
PCI: 00:1f.0 scanning...
PMH7: ID 03 Revision 10
PNP: 00ff.1 enabled
H8: EC Firmware ID 79HT50WW-3.4, Version 7.01A
No CMOS option 'usb_always_on'.
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
No CMOS option 'fn_ctrl_swap'.
PNP: 00ff.2 enabled
PNP: 164e.2 enabled
PNP: 164e.3 disabled
PNP: 164e.7 enabled
PNP: 164e.19 enabled
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 enabled
PNP: 002e.7 enabled
PNP: 002e.a disabled
scan_bus: bus PCI: 00:1f.0 finished in 55 msecs
PCI: 00:1f.3 scanning...
bus: PCI: 00:1f.3[0]->I2C: 01:69 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_bus: bus PCI: 00:1f.3 finished in 33 msecs
scan_bus: bus DOMAIN: 0000 finished in 290 msecs
scan_bus: bus Root Device finished in 300 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 299 ms
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 01:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
pci_tolm: 0xffffffff
TSEG decoded, subtracting 2M
Unused RAM between cbmem_top and TOM: 0x800K
Available memory: 3141632K (3068M)
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
Done reading resources.
==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
 PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 01:00.0 14 *  [0x0 - 0xff] io
 PCI: 00:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
  PCI: 01:00.0 18 *  [0x20000 - 0x2ffff] mem
 PCI: 00:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 01:00.0 10 *  [0x0 - 0x7ffffff] prefmem
 PCI: 00:01.0 prefmem: size: 8000000 align: 27 gran: 20 limit: ffffffff done
 PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 02:00.0 18 *  [0x0 - 0x1f] io
 PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 02:00.0 10 *  [0x0 - 0x1ffff] mem
 PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 03:00.0 10 *  [0x0 - 0xfff] mem
 PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 06:00.0 2c *  [0x0 - 0xfff] io
  PCI: 06:00.0 34 *  [0x1000 - 0x1fff] io
 PCI: 00:1e.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
 PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 06:00.0 24 *  [0x0 - 0x1ffffff] mem
  PCI: 06:00.0 10 *  [0x2000000 - 0x2000fff] mem
 PCI: 00:1e.0 mem: size: 2100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 06:00.0 1c *  [0x0 - 0x1ffffff] prefmem
 PCI: 00:1e.0 prefmem: size: 2000000 align: 20 gran: 20 limit: ffffffff done
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
 update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
 update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed)
 update_constraints: PCI: 00:1f.0 10000400 base 00001680 limit 0000169b io (fixed)
 update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
 update_constraints: PNP: 164e.2 60 base 000002f8 limit 000002ff io (fixed)
 update_constraints: PNP: 164e.3 60 base 000003f8 limit 000003ff io (fixed)
 update_constraints: PNP: 164e.7 60 base 00001680 limit 0000168f io (fixed)
 update_constraints: PNP: 164e.19 60 base 0000164c limit 0000164d io (fixed)
 update_constraints: PNP: 002e.1 60 base 000003bc limit 000003c3 io (fixed)
 update_constraints: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed)
 update_constraints: PNP: 002e.3 60 base 000003f8 limit 000003ff io (fixed)
 update_constraints: PNP: 002e.7 60 base 00001620 limit 0000162f io (fixed)
 update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 1000, Size: 5e0, Tag: 100
 * Base: 15f0, Size: 10, Tag: 100
 * Base: 167c, Size: 4, Tag: 100
 * Base: 169c, Size: e964, Tag: 100
  PCI: 00:1e.0 1c *  [0x2000 - 0x3fff] limit: 3fff io
  PCI: 00:01.0 1c *  [0x4000 - 0x4fff] limit: 4fff io
  PCI: 00:1c.0 1c *  [0x5000 - 0x5fff] limit: 5fff io
  PCI: 00:1d.0 20 *  [0x1000 - 0x101f] limit: 101f io
  PCI: 00:1d.1 20 *  [0x1020 - 0x103f] limit: 103f io
  PCI: 00:1d.2 20 *  [0x1040 - 0x105f] limit: 105f io
  PCI: 00:1d.3 20 *  [0x1060 - 0x107f] limit: 107f io
  PCI: 00:1f.2 20 *  [0x1080 - 0x109f] limit: 109f io
  PCI: 00:1f.1 20 *  [0x10a0 - 0x10af] limit: 10af io
  PCI: 00:1f.1 10 *  [0x10b0 - 0x10b7] limit: 10b7 io
  PCI: 00:1f.1 18 *  [0x10b8 - 0x10bf] limit: 10bf io
  PCI: 00:1f.2 10 *  [0x10c0 - 0x10c7] limit: 10c7 io
  PCI: 00:1f.2 18 *  [0x10c8 - 0x10cf] limit: 10cf io
  PCI: 00:1f.1 14 *  [0x10d0 - 0x10d3] limit: 10d3 io
  PCI: 00:1f.1 1c *  [0x10d4 - 0x10d7] limit: 10d7 io
  PCI: 00:1f.2 14 *  [0x10d8 - 0x10db] limit: 10db io
  PCI: 00:1f.2 1c *  [0x10dc - 0x10df] limit: 10df io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
 update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed)
 update_constraints: DOMAIN: 0000 04 base 000c0000 limit bfffffff mem (fixed)
 update_constraints: DOMAIN: 0000 06 base bfe00000 limit bfffffff mem (fixed)
 update_constraints: DOMAIN: 0000 07 base bfc00000 limit bfdfffff mem (fixed)
 update_constraints: DOMAIN: 0000 08 base 000a0000 limit 000bffff mem (fixed)
 update_constraints: PCI: 00:00.0 48 base f0000000 limit f3ffffff mem (fixed)
 update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
 update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: c0000000, Size: 30000000, Tag: 200
 * Base: f4000000, Size: ac00000, Tag: 200
 * Base: fec01000, Size: bff000, Tag: 200
 * Base: 100000000, Size: f00000000, Tag: 100200
  PCI: 00:01.0 24 *  [0xc0000000 - 0xc7ffffff] limit: c7ffffff prefmem
  PCI: 00:1e.0 20 *  [0xc8000000 - 0xca0fffff] limit: ca0fffff mem
  PCI: 00:1e.0 24 *  [0xca100000 - 0xcc0fffff] limit: cc0fffff prefmem
  PCI: 00:01.0 20 *  [0xcc100000 - 0xcc1fffff] limit: cc1fffff mem
  PCI: 00:1c.0 20 *  [0xcc200000 - 0xcc2fffff] limit: cc2fffff mem
  PCI: 00:1c.1 20 *  [0xcc300000 - 0xcc3fffff] limit: cc3fffff mem
  PCI: 00:1b.0 10 *  [0xcc400000 - 0xcc403fff] limit: cc403fff mem
  PCI: 00:1d.7 10 *  [0xcc404000 - 0xcc4043ff] limit: cc4043ff mem
  PCI: 00:1f.2 24 *  [0xcc405000 - 0xcc4053ff] limit: cc4053ff mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
PCI: 00:01.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff
 PCI: 00:01.0: Resource ranges:
 * Base: 4000, Size: 1000, Tag: 100
  PCI: 01:00.0 14 *  [0x4000 - 0x40ff] limit: 40ff io
PCI: 00:01.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff done
PCI: 00:01.0 prefmem: base: c0000000 size: 8000000 align: 27 gran: 20 limit: c7ffffff
 PCI: 00:01.0: Resource ranges:
 * Base: c0000000, Size: 8000000, Tag: 1200
  PCI: 01:00.0 10 *  [0xc0000000 - 0xc7ffffff] limit: c7ffffff prefmem
PCI: 00:01.0 prefmem: base: c0000000 size: 8000000 align: 27 gran: 20 limit: c7ffffff done
PCI: 00:01.0 mem: base: cc100000 size: 100000 align: 20 gran: 20 limit: cc1fffff
 PCI: 00:01.0: Resource ranges:
 * Base: cc100000, Size: 100000, Tag: 200
  PCI: 01:00.0 30 *  [0xcc100000 - 0xcc11ffff] limit: cc11ffff mem
  PCI: 01:00.0 18 *  [0xcc120000 - 0xcc12ffff] limit: cc12ffff mem
PCI: 00:01.0 mem: base: cc100000 size: 100000 align: 20 gran: 20 limit: cc1fffff done
PCI: 00:1c.0 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff
 PCI: 00:1c.0: Resource ranges:
 * Base: 5000, Size: 1000, Tag: 100
  PCI: 02:00.0 18 *  [0x5000 - 0x501f] limit: 501f io
PCI: 00:1c.0 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff done
PCI: 00:1c.0 mem: base: cc200000 size: 100000 align: 20 gran: 20 limit: cc2fffff
 PCI: 00:1c.0: Resource ranges:
 * Base: cc200000, Size: 100000, Tag: 200
  PCI: 02:00.0 10 *  [0xcc200000 - 0xcc21ffff] limit: cc21ffff mem
PCI: 00:1c.0 mem: base: cc200000 size: 100000 align: 20 gran: 20 limit: cc2fffff done
PCI: 00:1c.1 mem: base: cc300000 size: 100000 align: 20 gran: 20 limit: cc3fffff
 PCI: 00:1c.1: Resource ranges:
 * Base: cc300000, Size: 100000, Tag: 200
  PCI: 03:00.0 10 *  [0xcc300000 - 0xcc300fff] limit: cc300fff mem
PCI: 00:1c.1 mem: base: cc300000 size: 100000 align: 20 gran: 20 limit: cc3fffff done
PCI: 00:1e.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
 PCI: 00:1e.0: Resource ranges:
 * Base: 2000, Size: 2000, Tag: 100
  PCI: 06:00.0 2c *  [0x2000 - 0x2fff] limit: 2fff io
  PCI: 06:00.0 34 *  [0x3000 - 0x3fff] limit: 3fff io
PCI: 00:1e.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
PCI: 00:1e.0 prefmem: base: ca100000 size: 2000000 align: 20 gran: 20 limit: cc0fffff
 PCI: 00:1e.0: Resource ranges:
 * Base: ca100000, Size: 2000000, Tag: 1200
  PCI: 06:00.0 1c *  [0xca100000 - 0xcc0fffff] limit: cc0fffff prefmem
PCI: 00:1e.0 prefmem: base: ca100000 size: 2000000 align: 20 gran: 20 limit: cc0fffff done
PCI: 00:1e.0 mem: base: c8000000 size: 2100000 align: 20 gran: 20 limit: ca0fffff
 PCI: 00:1e.0: Resource ranges:
 * Base: c8000000, Size: 2100000, Tag: 200
  PCI: 06:00.0 24 *  [0xc8000000 - 0xc9ffffff] limit: c9ffffff mem
  PCI: 06:00.0 10 *  [0xca000000 - 0xca000fff] limit: ca000fff mem
PCI: 00:1e.0 mem: base: c8000000 size: 2100000 align: 20 gran: 20 limit: ca0fffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem
DOMAIN: 0000 04 <- [0x00000c0000 - 0x00bfffffff] size 0xbff40000 gran 0x00 mem
DOMAIN: 0000 06 <- [0x00bfe00000 - 0x00bfffffff] size 0x00200000 gran 0x00 mem
DOMAIN: 0000 07 <- [0x00bfc00000 - 0x00bfdfffff] size 0x00200000 gran 0x00 mem
DOMAIN: 0000 08 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem
PCI: 00:01.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00c7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00cc100000 - 0x00cc1fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 01:00.0 10 <- [0x00c0000000 - 0x00c7ffffff] size 0x08000000 gran 0x1b prefmem
PCI: 01:00.0 14 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x00cc120000 - 0x00cc12ffff] size 0x00010000 gran 0x10 mem
PCI: 01:00.0 30 <- [0x00cc100000 - 0x00cc11ffff] size 0x00020000 gran 0x11 romem
PCI: 00:1b.0 10 <- [0x00cc400000 - 0x00cc403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x0000005000 - 0x0000005fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00cc200000 - 0x00cc2fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 02:00.0 10 <- [0x00cc200000 - 0x00cc21ffff] size 0x00020000 gran 0x11 mem
PCI: 02:00.0 18 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.1 20 <- [0x00cc300000 - 0x00cc3fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 03:00.0 10 <- [0x00cc300000 - 0x00cc300fff] size 0x00001000 gran 0x0c mem
PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1c.2 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 04 mem
PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:1c.3 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:1d.0 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
PCI: 00:1d.3 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00cc404000 - 0x00cc4043ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 06 io
PCI: 00:1e.0 24 <- [0x00ca100000 - 0x00cc0fffff] size 0x02000000 gran 0x14 bus 06 prefmem
PCI: 00:1e.0 20 <- [0x00c8000000 - 0x00ca0fffff] size 0x02100000 gran 0x14 bus 06 mem
PCI: 06:00.0 10 <- [0x00ca000000 - 0x00ca000fff] size 0x00001000 gran 0x0c mem
PCI: 06:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io
PCI: 06:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io
PCI: 06:00.0 1c <- [0x00ca100000 - 0x00cc0fffff] size 0x02000000 gran 0x0c prefmem
PCI: 06:00.0 24 <- [0x00c8000000 - 0x00c9ffffff] size 0x02000000 gran 0x0c mem
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned in devicetree
ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned in devicetree
ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned in devicetree
PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io
ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned in devicetree
PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io
ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned in devicetree
PNP: 002e.1 60 <- [0x00000003bc - 0x00000003c3] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned in devicetree
PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.7 60 <- [0x0000001620 - 0x000000162f] size 0x00000010 gran 0x04 io
ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned in devicetree
PCI: 00:1f.1 10 <- [0x00000010b0 - 0x00000010b7] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 14 <- [0x00000010d0 - 0x00000010d3] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 18 <- [0x00000010b8 - 0x00000010bf] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 1c <- [0x00000010d4 - 0x00000010d7] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 20 <- [0x00000010a0 - 0x00000010af] size 0x00000010 gran 0x04 io
PCI: 00:1f.2 10 <- [0x00000010c0 - 0x00000010c7] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x00000010d8 - 0x00000010db] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x00000010c8 - 0x00000010cf] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x00000010dc - 0x00000010df] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001080 - 0x000000109f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00cc405000 - 0x00cc4053ff] size 0x00000400 gran 0x0a mem
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 2 / 1367 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/2015
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 001b
PCI: 00:01.0 cmd <- 07
PCI: 00:1b.0 subsystem <- 17aa/2010
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 17aa/2001
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 bridge ctrl <- 0013
PCI: 00:1c.1 subsystem <- 8086/27d2
PCI: 00:1c.1 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0013
PCI: 00:1c.2 subsystem <- 8086/27d4
PCI: 00:1c.2 cmd <- 100
PCI: 00:1c.3 bridge ctrl <- 0013
PCI: 00:1c.3 subsystem <- 8086/27d6
PCI: 00:1c.3 cmd <- 100
PCI: 00:1d.0 subsystem <- 17aa/200a
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 subsystem <- 17aa/200a
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 subsystem <- 17aa/200a
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.3 subsystem <- 17aa/200a
PCI: 00:1d.3 cmd <- 01
PCI: 00:1d.7 subsystem <- 17aa/200b
PCI: 00:1d.7 cmd <- 102
PCI: 00:1e.0 bridge ctrl <- 0013
PCI: 00:1e.0 subsystem <- 8086/2448
PCI: 00:1e.0 cmd <- 107
PCI: 00:1f.0 subsystem <- 8086/27b9
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.1 subsystem <- 17aa/200c
PCI: 00:1f.1 cmd <- 01
PCI: 00:1f.2 subsystem <- 17aa/200d
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 8086/27da
PCI: 00:1f.3 cmd <- 101
PCI: 01:00.0 subsystem <- 17aa/20a4
PCI: 01:00.0 cmd <- 03
PCI: 02:00.0 cmd <- 03
PCI: 03:00.0 cmd <- 02
PCI: 06:00.0 bridge ctrl <- 016b
PCI: 06:00.0 subsystem <- 17aa/2012
PCI: 06:00.0 cmd <- 03
done.
BS: BS_DEV_ENABLE run times (exec / console): 1 / 128 ms
Initializing devices...
Root Device init
Root Device init finished in 0 msecs
CPU_CLUSTER: 0 init
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset c480 size 15000
microcode: sig=0x6f2 pf=0x20 revision=0x0
microcode: updated to revision 0x5c date=2010-10-02
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000bfc00000 size 0xbfb40000 type 6
0x00000000bfc00000 - 0x00000000c0000000 size 0x00400000 type 0
0x00000000c0000000 - 0x00000000c8000000 size 0x08000000 type 1
0x00000000c8000000 - 0x0000000100000000 size 0x38000000 type 0
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 5/4.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6
MTRR: 2 base 0x00000000bfc00000 mask 0x0000000fffc00000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000000ff8000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU has 2 cores.
Setting up SMI for CPU
Will perform SMM setup.
CPU: Intel(R) Core(TM)2 CPU         T5600  @ 1.83GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 1 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...done.
AP: slot 1 apic_id 1.
Waiting for 2nd SIPI to complete...done.
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 0x00038000. Will call 0xbfbae89d(0x00000000)
Installing SMM handler to 0xbfe00000
Loading module at 0xbfe10000 with entry 0xbfe10605. filesize: 0x1690 memsize: 0x56e8
Processing 70 relocs. Offset value of 0xbfe10000
Loading module at 0xbfe08000 with entry 0xbfe08000. filesize: 0x1b0 memsize: 0x1b0
Processing 13 relocs. Offset value of 0xbfe08000
SMM Module: placing jmp sequence at 0xbfe07c00 rel16 0x03fd
SMM Module: stub loaded at 0xbfe08000. Will call 0xbfe10605(0x00000000)
Initializing Southbridge SMI...

New SMBASE 0xbfe00000
In relocation handler: cpu 0
New SMBASE=0xbfe00000
Relocation complete.
VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
New SMBASE 0xbfdffc00
In relocation handler: cpu 1
New SMBASE=0xbfdffc00
Relocation complete.
Initializing CPU #0
CPU: vendor Intel device 6f2
CPU: family 06, model 0f, stepping 02
Enabling cache
CPU: Intel(R) Core(TM)2 CPU         T5600  @ 1.83GHz.
Setting up local APIC...
 apic_id: 0x00 done.
CPU #0 initialized
Initializing CPU #1
CPU: vendor Intel device 6f2
CPU: family 06, model 0f, stepping 02
Enabling cache
CPU: Intel(R) Core(TM)2 CPU         T5600  @ 1.83GHz.
Setting up local APIC...
 apic_id: 0x01 done.
CPU #1 initialized
CPU 1 going down...
bsp_do_flight_plan done after 129 msecs.
Initializing southbridge SMI...
SMI_STS:
GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO1 GPIO0
ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
TCO_STS:
Locking SMM.
CPU_CLUSTER: 0 init finished in 344 msecs
PCI: 00:1b.0 init
Azalia: codec type: Azalia
Azalia: base = cc400000
Azalia: codec_mask = 03
Azalia: Initializing codec #1
Azalia: codec viddid: 14f12bfa
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 11d41981
Azalia: verb_size: 44
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 28 msecs
PCI: 00:1c.0 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.0 init finished in 2 msecs
PCI: 00:1c.1 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.1 init finished in 2 msecs
PCI: 00:1c.2 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.2 init finished in 2 msecs
PCI: 00:1c.3 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.3 init finished in 2 msecs
PCI: 00:1d.0 init
UHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 3 msecs
PCI: 00:1d.1 init
UHCI: Setting up controller.. done.
PCI: 00:1d.1 init finished in 3 msecs
PCI: 00:1d.2 init
UHCI: Setting up controller.. done.
PCI: 00:1d.2 init finished in 3 msecs
PCI: 00:1d.3 init
UHCI: Setting up controller.. done.
PCI: 00:1d.3 init finished in 3 msecs
PCI: 00:1d.7 init
EHCI: Setting up controller.. done.
PCI: 00:1d.7 init finished in 3 msecs
PCI: 00:1e.0 init
PCI: 00:1e.0 init finished in 0 msecs
PCI: 00:1f.0 init
i82801gx: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
No CMOS option 'power_on_after_fail'.
Set power on after power failure.
NMI sources enabled.
rtc_failed = 0x0
RTC Init
Disabling ACPI via APMC:
done.
PCI: 00:1f.0 init finished in 27 msecs
PCI: 00:1f.1 init
i82801gx_ide: initializing... IDE0
PCI: 00:1f.1 init finished in 3 msecs
PCI: 00:1f.2 init
i82801gx_sata: initializing...
SATA controller in AHCI mode.
PCI: 00:1f.2 init finished in 5 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PCI: 03:00.0 init
PCI: 03:00.0 init finished in 0 msecs
PCI: 06:00.0 init
Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller
PCI: 06:00.0 init finished in 5 msecs
PNP: 00ff.2 init
PNP: 00ff.2 init finished in 0 msecs
PNP: 164e.2 init
PNP: 164e.2 init finished in 0 msecs
PNP: 164e.7 init
PNP: 164e.7 init finished in 0 msecs
PNP: 164e.19 init
PNP: 164e.19 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:69 init
Changing 12 of the 12 ck505 config bytes.
I2C: 01:69 init finished in 30 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
I2C: 01:54 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
I2C: 01:55 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
I2C: 01:56 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
I2C: 01:57 init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 25 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
I2C: 01:5d init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
I2C: 01:5e init finished in 0 msecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
I2C: 01:5f init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 109 / 580 ms
Finalize devices...
PCI: 00:1f.0 final
Manufacturer: c2
SF: Detected c2 2015 with sector size 0x1000, total 0x200000
Devices finalized
BS: BS_POST_DEVICE run times (exec / console): 0 / 12 ms
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 350c0 size 3138
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at bfb5e000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 1 CPU(s) with 2 core(s) each.
clocks between 1000 and 1833 MHz.
adding 3 P-States between busratio 6 and b, incl. P0
PSS: 1833MHz power 35000 control 0xb25 status 0xb25
PSS: 1333MHz power 30000 control 0x81c status 0x81c
PSS: 1000MHz power 25000 control 0x613 status 0x613
clocks between 1000 and 1833 MHz.
adding 3 P-States between busratio 6 and b, incl. P0
PSS: 1833MHz power 35000 control 0xb25 status 0xb25
PSS: 1333MHz power 30000 control 0x81c status 0x81c
PSS: 1000MHz power 25000 control 0x613 status 0x613
Generating ACPI PIRQ entries
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'pci1002,7149.rom'
CBFS: Found @ offset 38a40 size fc00
In CBFS, ROM address for PCI: 01:00.0 = 0xffe38c88
PCI: 01:00.0: Missing ACPI scope
ACPI:    * H8
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * MADT
ACPI: added table 4/32, length now 52
current = bfb61c70
ACPI:    * HPET
ACPI: added table 5/32, length now 56
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'pci1002,7149.rom'
CBFS: Found @ offset 38a40 size fc00
In CBFS, ROM address for PCI: 01:00.0 = 0xffe38c88
           Copying VBIOS image from 0xffe38c88
ACPI:    * VFCT at bfb61cb0
ACPI: added table 6/32, length now 60
ACPI: done.
ACPI tables: 80160 bytes.
smbios_write_tables: bfb5d000
SMBIOS tables: 609 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 2026
Writing coreboot table at 0xbfb82000
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 38380 size 680
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000bffff: RESERVED
 3. 00000000000c0000-00000000bfb5cfff: RAM
 4. 00000000bfb5d000-00000000bfb9afff: CONFIGURATION TABLES
 5. 00000000bfb9b000-00000000bfbd1fff: RAMSTAGE
 6. 00000000bfbd2000-00000000bfbfffff: CONFIGURATION TABLES
 7. 00000000bfc00000-00000000bfffffff: RESERVED
 8. 00000000f0000000-00000000f3ffffff: RESERVED
FMAP: area COREBOOT found @ 200 (2096640 bytes)
Wrote coreboot table at: 0xbfb82000, 0x99c bytes, checksum 85cf
coreboot table: 2484 bytes.
IMD ROOT    0. 0xbfbff000 0x00001000
IMD SMALL   1. 0xbfbfe000 0x00001000
CONSOLE     2. 0xbfbde000 0x00020000
TIME STAMP  3. 0xbfbdd000 0x00000910
ROMSTG STCK 4. 0xbfbdc000 0x00001000
AFTER CAR   5. 0xbfbd2000 0x0000a000
RAMSTAGE    6. 0xbfb9a000 0x00038000
SMM BACKUP  7. 0xbfb8a000 0x00010000
COREBOOT    8. 0xbfb82000 0x00008000
ACPI        9. 0xbfb5e000 0x00024000
SMBIOS     10. 0xbfb5d000 0x00000800
IMD small region:
  IMD ROOT    0. 0xbfbfec00 0x00000400
  FMAP        1. 0xbfbfeb40 0x000000b6
  ROMSTAGE    2. 0xbfbfeb20 0x00000004
  ACPI GNVS   3. 0xbfbfea20 0x00000100
BS: BS_WRITE_TABLES run times (exec / console): 206 / 300 ms
FMAP: area COREBOOT found @ 200 (2096640 bytes)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 4d3c0 size 11109
Checking segment from ROM address 0xffe4d5f8
Checking segment from ROM address 0xffe4d614
Loading segment from ROM address 0xffe4d5f8
  code (compression=1)
  New segment dstaddr 0x000dfac0 memsize 0x20540 srcaddr 0xffe4d630 filesize 0x110d1
Loading Segment: addr: 0x000dfac0 memsz: 0x0000000000020540 filesz: 0x00000000000110d1
using LZMA