coreboot-4.6-1040-gabc69cd Thu Aug 10 16:41:16 UTC 2017 romstage starting... running main(bist = 0) Stepping B3 2 CPU cores iTPM enabled ME enabled AMT enabled capable of DDR2 of 800 MHz or lower VT-d enabled GMCH: GS45, using high-power mode TXT enabled Render frequency: 533 MHz IGD enabled PCIe-to-GMCH enabled GMCH supports DDR3 with 1067 MT or less GMCH supports FSB with up to 1067 MHz SMBus controller enabled. 0:50:b 2:51:ff DDR mask 1, DDR 3 Bank 0 populated: Raw card type: D Row addr bits: 15 Col addr bits: 10 byte width: 1 page size: 1024 banks: 8 ranks: 2 tAAmin: 105 tCKmin: 15 Max clock: 533 MHz CAS: 0x01c0 Trying CAS 7, tCK 15. Found compatible clock / CAS pair: 533 / 7. Timing values: tCLK: 15 tRAS: 20 tRP: 7 tRCD: 7 tRFC: 104 tWR: 8 tRD: 11 tRRD: 4 tFAW: 20 tWL: 6 Changing memory frequency: old 3, new 6. Setting IGD memory frequencies for VCO #1. Memory configured in single-channel mode. Memory map: TOM = 256MB TOLUD = 256MB TOUUD = 256MB REMAP: base = 65535MB limit = 0MB usedMEsize: 0MB JEDEC init @0x00000000 JEDEC init @0x08000000 group 0, ch 0: 7.0.0.1.4 group 1, ch 0: 7.0.0.2.5 group 2, ch 0: 7.0.2.2.7 group 3, ch 0: 7.0.2.1.0 byte lane 0, ch 0: 4.6 byte lane 1, ch 0: 5.7 byte lane 2, ch 0: 5.1 byte lane 3, ch 0: 5.1 Timing overflow during read training. Read training failure: lower bound.