^C root@lede:/# cat /dev/ttyGS0 USB coreboot-4.6-890-g3dcbb4541b-dirty Thu Jul 27 21:33:23 UTC 2017 romstage starting... Setting up static southbridge registers... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Initializing Graphics... CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 19d80 size 7fc Back from sandybridge_early_initialization() SMBus controller enabled. CPU id(206a7): Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz AES supported, TXT supported, VT supported PCH type: QM67, device id: 1c4f, rev id 5 Intel ME early init Intel ME firmware is ready ME: Requested 32MB UMA Starting native Platform init CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0) CBFS: Locating 'mrc.cache' CBFS: Found @ offset 1fec0 size 10000 find_current_mrc_cache_local: No valid MRC cache found. Row addr bits : 16 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 8192 MB CAS latencies : 5 6 7 8 9 10 11 12 tCKmin : 1.070 ns tAAmin : 10.699 ns tWRmin : 15.000 ns tRCDmin : 10.699 ns tRRDmin : 5.000 ns tRPmin : 10.699 ns tRASmin : 34.000 ns tRCmin : 44.699 ns tRFCmin : 300.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 27.000 ns channel[0] rankmap = 0x3 Row addr bits : 16 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 8192 MB CAS latencies : 5 6 7 8 9 10 11 12 tCKmin : 1.070 ns tAAmin : 10.699 ns tWRmin : 15.000 ns tRCDmin : 10.699 ns tRRDmin : 5.000 ns tRPmin : 10.699 ns tRASmin : 34.000 ns tRCmin : 44.699 ns tRFCmin : 300.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 27.000 ns channel[1] rankmap = 0x3 Starting SandyBridge RAM training (0). Trying CAS 10, tCK 274. Found compatible clock, CAS pair. Selected DRAM frequency: 934 MHz Selected CAS latency : 10T PLL busy... done in 10 us MCU frequency is set at : 934 MHz Selected CWL latency : 9T Selected tRCD : 10T Selected tRP : 10T Selected tRAS : 32T Selected tWR : 15T Selected tFAW : 26T Selected tRRD : 5T Selected tRTP : 8T Selected tWTR : 8T Selected tRFC : 282T Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 4 PCI(0, 0, 0)[bc] = c2a00000 PCI(0, 0, 0)[a8] = 3b600000 PCI(0, 0, 0)[ac] = 4 PCI(0, 0, 0)[b8] = c0000000 PCI(0, 0, 0)[b0] = c0a00000 PCI(0, 0, 0)[b4] = c0800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = fe000000 PCI(0, 0, 0)[74] = 3 PCI(0, 0, 0)[78] = fe000c00 Done memory map Done io registers Done jedec reset Done MRS commands edge write discovery failed: 0, 0, 0 RAM training failed, trying fallback. Row addr bits : 16 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 8192 MB CAS latencies : 5 6 7 8 9 10 11 12 tCKmin : 1.070 ns tAAmin : 10.699 ns tWRmin : 15.000 ns tRCDmin : 10.699 ns tRRDmin : 5.000 ns tRPmin : 10.699 ns tRASmin : 34.000 ns tRCmin : 44.699 ns tRFCmin : 300.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 27.000 ns channel[0] rankmap = 0x3 Row addr bits : 16 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 8192 MB CAS latencies : 5 6 7 8 9 10 11 12 tCKmin : 1.070 ns tAAmin : 10.699 ns tWRmin : 15.000 ns tRCDmin : 10.699 ns tRRDmin : 5.000 ns tRPmin : 10.699 ns tRASmin : 34.000 ns tRCmin : 44.699 ns tRFCmin : 300.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 27.000 ns channel[1] rankmap = 0x3 Starting SandyBridge RAM training (0). Trying CAS 10, tCK 274. Found compatible clock, CAS pair. Selected DRAM frequency: 934 MHz Selected CAS latency : 10T Selected CWL latency : 9T Selected tRCD : 10T Selected tRP : 10T Selected tRAS : 32T Selected tWR : 15T Selected tFAW : 26T Selected tRRD : 5T Selected tRTP : 8T Selected tWTR : 8T Selected tRFC : 282T Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 2 PCI(0, 0, 0)[bc] = c2a00000 PCI(0, 0, 0)[a8] = 3b600000 PCI(0, 0, 0)[ac] = 2 PCI(0, 0, 0)[b8] = c0000000 PCI(0, 0, 0)[b0] = c0a00000 PCI(0, 0, 0)[b4] = c0800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = fe000000 PCI(0, 0, 0)[74] = 1 PCI(0, 0, 0)[78] = fe000c00 Done memory map Done io registers Done jedec reset Done MRS commands edge discovery failed: 1, 0, 0