|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x10000.
|
|
[DEBUG] FMAP: base = 0x0 size = 0x800000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 11000 (8318976 bytes)
|
|
[INFO ] Booting from COREBOOT region
|
|
[INFO ] CBFS: mcache @0xfeffae00 built for 20 files, used 0x404 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x2ff80 size 0xf3d0 in mcache @0xfeffafd4
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 59 ms
|
|
[DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xff840000, size: 0x00020000
|
|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[DEBUG] Setting up static southbridge registers... done.
|
|
[DEBUG] Disabling Watchdog reboot... done.
|
|
[DEBUG] Needs reset to configure CPU BSEL straps
|
|
[INFO ] full_reset() called!
|
|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x10000.
|
|
[DEBUG] FMAP: base = 0x0 size = 0x800000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 11000 (8318976 bytes)
|
|
[INFO ] Booting from COREBOOT region
|
|
[INFO ] CBFS: mcache @0xfeffae00 built for 20 files, used 0x404 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x2ff80 size 0xf3d0 in mcache @0xfeffafd4
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 59 ms
|
|
[DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xff840000, size: 0x00020000
|
|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[DEBUG] Setting up static southbridge registers... done.
|
|
[DEBUG] Disabling Watchdog reboot... done.
|
|
[DEBUG] Setting up RAM controller.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] Dimms per channel: 1
|
|
[WARN ] 2 CPU cores
|
|
[DEBUG] Decoding dimm 0
|
|
[DEBUG] Decoding dimm 2
|
|
[DEBUG] Selected timings:
|
|
[DEBUG] FSB: 1067MHz
|
|
[DEBUG] DDR: 1067MHz
|
|
[DEBUG] CAS: 8
|
|
[DEBUG] tRAS: 20
|
|
[DEBUG] tRP: 8
|
|
[DEBUG] tRCD: 8
|
|
[DEBUG] tWR: 8
|
|
[DEBUG] tRFC: 86
|
|
[DEBUG] tWTR: 4
|
|
[DEBUG] tRRD: 4
|
|
[DEBUG] tRTP: 4
|
|
[DEBUG] Config[CH0] : 2
|
|
[DEBUG] Config[CH1] : 2
|
|
[DEBUG] Done clk crossing
|
|
[DEBUG] Done I/O clk
|
|
[DEBUG] Done launch
|
|
[DEBUG] Done timings
|
|
[DEBUG] RCOMP
|
|
[DEBUG] Done ODT
|
|
[DEBUG] Done RCOMP update
|
|
[DEBUG] DDR3 Reset.
|
|
[DEBUG] Done pre-jedec
|
|
[DEBUG] MRS...
|
|
[DEBUG] CH0: Found Rank 0
|
|
[DEBUG] CH0: Found Rank 1
|
|
[DEBUG] CH1: Found Rank 0
|
|
[DEBUG] CH1: Found Rank 1
|
|
[DEBUG] MRS done
|
|
[DEBUG] Done jedec steps
|
|
[DEBUG] Starting write levelling.
|
|
[DEBUG] CH0
|
|
[DEBUG] final WL DQS settings on CH0
|
|
[DEBUG] lane0: 0.1.2.6:0.0
|
|
[DEBUG] lane1: 0.1.4.4:0.0
|
|
[DEBUG] lane2: 0.1.4.6:0.0
|
|
[DEBUG] lane3: 0.1.6.2:0.0
|
|
[DEBUG] lane4: 0.1.6.2:0.0
|
|
[DEBUG] lane5: 0.1.8.3:0.0
|
|
[DEBUG] lane6: 0.1.10.1:1.0
|
|
[DEBUG] lane7: 0.2.0.0:1.1
|
|
[DEBUG] CH1
|
|
[DEBUG] final WL DQS settings on CH1
|
|
[DEBUG] lane0: 0.1.3.3:0.0
|
|
[DEBUG] lane1: 0.1.3.5:0.0
|
|
[DEBUG] lane2: 0.1.4.4:0.0
|
|
[DEBUG] lane3: 0.1.4.6:0.0
|
|
[DEBUG] lane4: 0.1.6.5:0.0
|
|
[DEBUG] lane5: 0.1.8.5:0.0
|
|
[DEBUG] lane6: 0.1.10.2:1.0
|
|
[DEBUG] lane7: 1.0.0.2:1.1
|
|
[DEBUG] Done write levelling.
|
|
[DEBUG] Software initiated DDR3 reset.
|
|
[DEBUG] MRS...
|
|
[DEBUG] CH0: Found Rank 0
|
|
[DEBUG] CH0: Found Rank 1
|
|
[DEBUG] CH1: Found Rank 0
|
|
[DEBUG] CH1: Found Rank 1
|
|
[DEBUG] MRS done
|
|
[DEBUG] Done post-jedec
|
|
[DEBUG] Done dummy reads
|
|
[DEBUG] Starting DQS receiver enable calibration
|
|
[DEBUG] Channel 0, Lane 0 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 1 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 2 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 3 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 4 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 5 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 6 addr=0x00000000
|
|
[DEBUG] Channel 0, Lane 7 addr=0x00000000
|
|
[DEBUG] Found min coarse value = 8
|
|
[DEBUG] Receive enable, final timings:
|
|
[DEBUG] ch 0 lane 0: coarse offset: 0;medium: 1; tap: 5
|
|
[DEBUG] ch 0 lane 1: coarse offset: 0;medium: 1; tap: 7
|
|
[DEBUG] ch 0 lane 2: coarse offset: 0;medium: 2; tap: 2
|
|
[DEBUG] ch 0 lane 3: coarse offset: 0;medium: 2; tap: 4
|
|
[DEBUG] ch 0 lane 4: coarse offset: 0;medium: 2; tap: 9
|
|
[DEBUG] ch 0 lane 5: coarse offset: 0;medium: 2; tap: 9
|
|
[DEBUG] ch 0 lane 6: coarse offset: 0;medium: 3; tap: 7
|
|
[DEBUG] ch 0 lane 7: coarse offset: 0;medium: 3; tap: 9
|
|
[DEBUG] Channel 1, Lane 0 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 1 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 2 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 3 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 4 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 5 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 6 addr=0x20000000
|
|
[DEBUG] Channel 1, Lane 7 addr=0x20000000
|
|
[DEBUG] Found min coarse value = 8
|
|
[DEBUG] Receive enable, final timings:
|
|
[DEBUG] ch 1 lane 0: coarse offset: 0;medium: 1; tap: 9
|
|
[DEBUG] ch 1 lane 1: coarse offset: 0;medium: 1; tap: 10
|
|
[DEBUG] ch 1 lane 2: coarse offset: 0;medium: 3; tap: 0
|
|
[DEBUG] ch 1 lane 3: coarse offset: 0;medium: 2; tap: 10
|
|
[DEBUG] ch 1 lane 4: coarse offset: 0;medium: 3; tap: 6
|
|
[DEBUG] ch 1 lane 5: coarse offset: 1;medium: 0; tap: 2
|
|
[DEBUG] ch 1 lane 6: coarse offset: 1;medium: 0; tap: 4
|
|
[DEBUG] ch 1 lane 7: coarse offset: 1;medium: 0; tap: 8
|
|
[DEBUG] Done rcven
|
|
[DEBUG] Starting DQ write training
|
|
[DEBUG] Doing DQ write training on CH0
|
|
[DEBUG] Final DQ timings on CH0
|
|
[DEBUG] lane0: 0.1.8.5:0.0
|
|
[DEBUG] lane1: 0.1.10.1:1.0
|
|
[DEBUG] lane2: 0.1.10.1:1.0
|
|
[DEBUG] lane3: 0.2.0.4:1.1
|
|
[DEBUG] lane4: 0.2.0.5:1.1
|
|
[DEBUG] lane5: 0.2.2.6:0.0
|
|
[DEBUG] lane6: 0.2.4.4:0.0
|
|
[DEBUG] lane7: 0.2.5.5:0.0
|
|
[DEBUG] Doing DQ write training on CH1
|
|
[DEBUG] Final DQ timings on CH1
|
|
[DEBUG] lane0: 0.1.9.2:1.0
|
|
[DEBUG] lane1: 0.1.9.4:1.0
|
|
[DEBUG] lane2: 0.1.10.3:1.0
|
|
[DEBUG] lane3: 0.1.10.4:1.0
|
|
[DEBUG] lane4: 0.2.1.1:1.1
|
|
[DEBUG] lane5: 0.2.3.2:0.0
|
|
[DEBUG] lane6: 0.2.4.2:0.0
|
|
[DEBUG] lane7: 1.0.6.1:0.0
|
|
[DEBUG] Done DQ write training
|
|
[DEBUG] Starting DQS read training
|
|
[DEBUG] Final timings on CH0:
|
|
[DEBUG] lane0: 4.7
|
|
[DEBUG] lane1: 4.7
|
|
[DEBUG] lane2: 4.5
|
|
[DEBUG] lane3: 4.7
|
|
[DEBUG] lane4: 4.7
|
|
[DEBUG] lane5: 4.6
|
|
[DEBUG] lane6: 5.1
|
|
[DEBUG] lane7: 4.7
|
|
[DEBUG] Final timings on CH1:
|
|
[DEBUG] lane0: 5.1
|
|
[DEBUG] lane1: 4.7
|
|
[DEBUG] lane2: 4.3
|
|
[DEBUG] lane3: 5.0
|
|
[DEBUG] lane4: 5.1
|
|
[DEBUG] lane5: 4.1
|
|
[DEBUG] lane6: 5.0
|
|
[DEBUG] lane7: 4.5
|
|
[DEBUG] Done DQS read training
|
|
[DEBUG] Total memory: 4096 + 4096 = 8192MiB
|
|
[DEBUG] Done DRADRB
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done enhanced mode
|
|
[DEBUG] Done PRCOMP
|
|
[DEBUG] Done power settings
|
|
[DEBUG] Done raminit
|
|
[DEBUG] RAM initialization finished.
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7f7ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7f7fec00 62 entries.
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] FMAP: area COREBOOT found @ 11000 (8318976 bytes)
|
|
[INFO ] Booting from COREBOOT region
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x7fbff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fbfec00 62 entries.
|
|
[DEBUG] Memory initialized
|
|
[DEBUG] Done Egress Port
|
|
[DEBUG] Done DMI setup
|
|
[DEBUG] x4x late init complete
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x7fa00000 0x200000
|
|
[DEBUG] Subregion 0: 0x7fa00000 0x100000
|
|
[DEBUG] Subregion 2: 0x7fb00000 0x100000
|
|
[DEBUG] Subregion 3: 0x7fc00000 0x0
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x65ac0 size 0x5a6c in mcache @0xfeffb0fc
|
|
[DEBUG] Loading module at 0x7f7d0000 with entry 0x7f7d0031. filesize: 0x5688 memsize: 0xb9d8
|
|
[DEBUG] Processing 233 relocs. Offset value of 0x7d7d0000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 695 ms
|
|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] FMAP: area COREBOOT found @ 11000 (8318976 bytes)
|
|
[INFO ] Booting from COREBOOT region
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x3f400 size 0x161f8 in mcache @0x7f7dd254
|
|
[DEBUG] Loading module at 0x7f697000 with entry 0x7f697000. filesize: 0x2a960 memsize: 0x137410
|
|
[DEBUG] Processing 3131 relocs. Offset value of 0x7b697000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 53 ms
|
|
|
|
|
|
[NOTE ] coreboot-26.06-216-gb4ebd461d9f4-dirty Sat Jul 11 01:15:17 UTC 2026 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/2e30] enabled
|
|
[DEBUG] PCI: 00:00:01.0 subordinate bus PCI Express
|
|
[DEBUG] PCI: 00:00:01.0 [8086/2e31] enabled
|
|
[DEBUG] PCI: 00:00:02.0 [8086/2e32] enabled
|
|
[DEBUG] PCI: 00:00:02.1 [8086/2e33] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/27d8] enabled
|
|
[DEBUG] PCI: 00:00:1c.0 [8086/27d0] enabled
|
|
[DEBUG] PCI: 00:00:1c.1 [8086/27d2] enabled
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2 [8086/27d4] disabled
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3 [8086/27d6] disabled
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/27c8] enabled
|
|
[DEBUG] PCI: 00:00:1d.1 [8086/27c9] enabled
|
|
[DEBUG] PCI: 00:00:1d.2 [8086/27ca] enabled
|
|
[DEBUG] PCI: 00:00:1d.3 [8086/27cb] enabled
|
|
[DEBUG] PCI: 00:00:1d.7 [8086/27cc] enabled
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/244e] enabled
|
|
[DEBUG] PCI: 00:00:1e.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.2 [8086/27de] disabled
|
|
[DEBUG] PCI: 00:00:1e.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.3 [8086/27dd] disabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/27b8] enabled
|
|
[DEBUG] PCI: 00:00:1f.1 [8086/27df] enabled
|
|
[DEBUG] Set SATA mode early
|
|
[DEBUG] AHCI not supported, falling back to plain mode.
|
|
[DEBUG] Set SATA mode early
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/27c0] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/27da] enabled
|
|
[DEBUG] PCI: 00:00:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[INFO ] PCI: 00:00:01.0: ASPM enabled L0s and L1 (no endpoint)
|
|
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 20 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 5 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[INFO ] PCI: Static device PCI: 00:03:00.0 not found, disabling it.
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 12 msecs
|
|
[DEBUG] PCI: 00:00:1e.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 04
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1e.0 finished in 5 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[DEBUG] PNP: 002e.0 disabled
|
|
[DEBUG] PNP: 002e.1 enabled
|
|
[DEBUG] PNP: 002e.2 enabled
|
|
[DEBUG] PNP: 002e.3 disabled
|
|
[DEBUG] PNP: 002e.5 enabled
|
|
[DEBUG] PNP: 002e.6 disabled
|
|
[DEBUG] PNP: 002e.7 enabled
|
|
[DEBUG] PNP: 002e.8 disabled
|
|
[DEBUG] PNP: 002e.9 enabled
|
|
[DEBUG] PNP: 002e.109 disabled
|
|
[DEBUG] PNP: 002e.209 enabled
|
|
[DEBUG] PNP: 002e.309 enabled
|
|
[DEBUG] PNP: 002e.a enabled
|
|
[DEBUG] PNP: 002e.b enabled
|
|
[DEBUG] PNP: 002e.c enabled
|
|
[DEBUG] PNP: 002e.307 enabled
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 54 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 329 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 347 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 362 ms
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[INFO ] Manufacturer: ef
|
|
[INFO ] SF: Detected ef 4017 with sector size 0x1000, total 0x800000
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 42 ms
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] TOUUD 0x27c000000 TOLUD 0x84000000 TOM 0x200000000
|
|
[INFO ] Available memory above 4GB: 6080M
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000.
|
|
[ERROR] PNP: 002e.7 missing read_resources
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: f000, Tag: 100
|
|
[DEBUG] PCI: 00:00:1d.0 20 * [0xffe0 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:1d.1 20 * [0xffc0 - 0xffdf] limit: ffdf io
|
|
[DEBUG] PCI: 00:00:1d.2 20 * [0xffa0 - 0xffbf] limit: ffbf io
|
|
[DEBUG] PCI: 00:00:1d.3 20 * [0xff80 - 0xff9f] limit: ff9f io
|
|
[DEBUG] PCI: 00:00:1f.1 20 * [0xff70 - 0xff7f] limit: ff7f io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xff60 - 0xff6f] limit: ff6f io
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0xff58 - 0xff5f] limit: ff5f io
|
|
[DEBUG] PCI: 00:00:1f.1 10 * [0xff50 - 0xff57] limit: ff57 io
|
|
[DEBUG] PCI: 00:00:1f.1 18 * [0xff48 - 0xff4f] limit: ff4f io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xff40 - 0xff47] limit: ff47 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xff38 - 0xff3f] limit: ff3f io
|
|
[DEBUG] PCI: 00:00:1f.1 14 * [0xff34 - 0xff37] limit: ff37 io
|
|
[DEBUG] PCI: 00:00:1f.1 1c * [0xff30 - 0xff33] limit: ff33 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xff2c - 0xff2f] limit: ff2f io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xff28 - 0xff2b] limit: ff2b io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: febfffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 04 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 05 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 06 base 00100000 limit 7f7fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 07 base 100000000 limit 27bffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 08 base 7fa00000 limit 83ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 09 base 7f800000 limit 7f9fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0a base fed10000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0b base e0000000 limit efffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 84000000, Size: 5c000000, Tag: 200
|
|
[INFO ] * Base: f0000000, Size: ec00000, Tag: 200
|
|
[INFO ] * Base: 27c000000, Size: d84000000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0xfe800000 - 0xfebfffff] limit: febfffff mem
|
|
[DEBUG] PCI: 00:00:02.1 10 * [0xfe700000 - 0xfe7fffff] limit: fe7fffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xfe6fc000 - 0xfe6fffff] limit: fe6fffff mem
|
|
[DEBUG] PCI: 00:00:1d.7 10 * [0xfe6fb000 - 0xfe6fb3ff] limit: fe6fb3ff mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: febfffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] DOMAIN: 00000000 03 <- [0x0000000000000000 - 0x000000000009ffff] size 0x000a0000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 04 <- [0x00000000000a0000 - 0x00000000000bffff] size 0x00020000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 05 <- [0x00000000000c0000 - 0x00000000000fffff] size 0x00040000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 06 <- [0x0000000000100000 - 0x000000007f7fffff] size 0x7f700000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 07 <- [0x0000000100000000 - 0x000000027bffffff] size 0x17c000000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 08 <- [0x000000007fa00000 - 0x0000000083ffffff] size 0x04600000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 09 <- [0x000000007f800000 - 0x000000007f9fffff] size 0x00200000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 0a <- [0x00000000fed10000 - 0x00000000ffffffff] size 0x012f0000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 00000000 0b <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x00 mem
|
|
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000fe800000 - 0x00000000febfffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000d0000000 - 0x00000000dfffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ff58 - 0x000000000000ff5f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:02.1 10 <- [0x00000000fe700000 - 0x00000000fe7fffff] size 0x00100000 gran 0x14 mem64
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000fe6fc000 - 0x00000000fe6fffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:00:1d.0 20 <- [0x000000000000ffe0 - 0x000000000000ffff] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1d.1 20 <- [0x000000000000ffc0 - 0x000000000000ffdf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1d.2 20 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1d.3 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1d.7 10 <- [0x00000000fe6fb000 - 0x00000000fe6fb3ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 04 io
|
|
[DEBUG] PCI: 00:00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
|
|
[DEBUG] PCI: 00:00:1e.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 mem
|
|
[DEBUG] PNP: 002e.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.1 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 74 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
|
|
[ERROR] PNP: 002e.7 missing set_resources
|
|
[DEBUG] PNP: 002e.209 e2 <- [0x0000000000000020 - 0x000000000000001f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.209 e9 <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 f3 <- [0x0000000000000009 - 0x0000000000000008] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 f4 <- [0x0000000000000064 - 0x0000000000000063] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 f5 <- [0x00000000000000ce - 0x00000000000000cd] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 f6 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 f9 <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 fa <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.309 fe <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e0 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e2 <- [0x00000000000000f7 - 0x00000000000000f6] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e3 <- [0x0000000000000025 - 0x0000000000000024] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e5 <- [0x0000000000000002 - 0x0000000000000001] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e6 <- [0x000000000000009c - 0x000000000000009b] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e7 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e8 <- [0x0000000000000009 - 0x0000000000000008] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a e9 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.a f2 <- [0x000000000000007d - 0x000000000000007c] size 0x00000000 gran 0x00 irq
|
|
[NOTE ] PNP: 002e.a 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.b 60 <- [0x0000000000000290 - 0x0000000000000291] size 0x00000002 gran 0x01 io
|
|
[DEBUG] PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.b f1 <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.b f2 <- [0x0000000000000083 - 0x0000000000000082] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c e0 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c e1 <- [0x0000000000000064 - 0x0000000000000063] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c e8 <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c e9 <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c fe <- [0x00000000000000f0 - 0x00000000000000ef] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.c ff <- [0x0000000000000080 - 0x000000000000007f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PCI: 00:00:1f.1 10 <- [0x000000000000ff50 - 0x000000000000ff57] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.1 14 <- [0x000000000000ff34 - 0x000000000000ff37] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.1 18 <- [0x000000000000ff48 - 0x000000000000ff4f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.1 1c <- [0x000000000000ff30 - 0x000000000000ff33] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.1 20 <- [0x000000000000ff70 - 0x000000000000ff7f] size 0x00000010 gran 0x04 io
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff40 - 0x000000000000ff47] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff2c - 0x000000000000ff2f] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff38 - 0x000000000000ff3f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff28 - 0x000000000000ff2b] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff60 - 0x000000000000ff6f] size 0x00000010 gran 0x04 io
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1296 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:01.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:02.1 cmd <- 02
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 100
|
|
[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.1 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1c.1 cmd <- 100
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1d.1 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1d.1 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1d.2 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1d.2 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1d.3 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1d.3 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1d.7 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1d.7 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1e.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1e.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1e.0 cmd <- 100
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.1 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1f.1 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 01
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 1043/836d
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 101
|
|
[INFO ] done.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 166 ms
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[DEBUG] microcode: sig=0x1067a pf=0x1 revision=0xa0b
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] FMAP: area COREBOOT found @ 11000 (8318976 bytes)
|
|
[INFO ] Booting from COREBOOT region
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x2c000 in mcache @0x7f7dd02c
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007f9fffff size 0x7f940000 type 6
|
|
[DEBUG] 0x000000007fa00000 - 0x00000000cfffffff size 0x50600000 type 0
|
|
[DEBUG] 0x00000000d0000000 - 0x00000000dfffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000e0000000 - 0x00000000ffffffff size 0x20000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000027bffffff size 0x17c000000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 6/6.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x000000007fa00000 mask 0x0000000fffe00000 type 0
|
|
[DEBUG] MTRR: 2 base 0x000000007fc00000 mask 0x0000000fffc00000 type 0
|
|
[DEBUG] MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6
|
|
[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000000f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[INFO ] CPU: Pentium(R) Dual-Core CPU E6500 @ 2.93GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 1 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000a0b
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1d8 memsize: 0x1d8
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7fa00800
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f6ac667
|
|
[DEBUG] Installing permanent SMM handler to 0x7fa00000
|
|
[DEBUG] HANDLER [0x7faff000-0x7faff64f]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x7fafec00-0x7fafefff]
|
|
[DEBUG] stub0 [0x7faf7000-0x7faf71d7]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x7fafe800-0x7fafebff]
|
|
[DEBUG] stub1 [0x7faf6c00-0x7faf6dd7]
|
|
|
|
[DEBUG] stacks [0x7fa00000-0x7fa007ff]
|
|
[DEBUG] Loading module at 0x7faff000 with entry 0x7faff026. filesize: 0x640 memsize: 0x650
|
|
[DEBUG] Processing 27 relocs. Offset value of 0x7faff000
|
|
[DEBUG] Loading module at 0x7faf7000 with entry 0x7faf7000. filesize: 0x1d8 memsize: 0x1d8
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x7faf7000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7fa00800
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x100000
|
|
[DEBUG] SMM Module: placing smm entry code at 7faf6c00, cpu # 0x1
|
|
[DEBUG] SMM Module: stub loaded at 7faf7000. Will call 0x7faff026
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faef000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x7faef000
|
|
[WARN ] SMRR not enabled, skip writing SMRR...
|
|
[DEBUG] Relocation complete.
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeec00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x7faeec00
|
|
[DEBUG] Writing SMRR. base = 0x7fa00000, mask=0xffe00800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 1067a
|
|
[DEBUG] CPU: family 06, model 17, stepping 0a
|
|
[INFO ] CPU: Pentium(R) Dual-Core CPU E6500 @ 2.93GHz.
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 1: 0, 0, 8, 0x1d, 25000; encoded: 0x081d
|
|
[DEBUG] writing P-State 0: 0, 0, 11, 0x24, 35000; encoded: 0x0b24
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[DEBUG] CPU: vendor Intel device 1067a
|
|
[DEBUG] CPU: family 06, model 17, stepping 0a
|
|
[INFO ] CPU: Pentium(R) Dual-Core CPU E6500 @ 2.93GHz.
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x16, 15000; encoded: 0x0616
|
|
[DEBUG] writing P-State 1: 0, 0, 8, 0x1d, 25000; encoded: 0x081d
|
|
[DEBUG] writing P-State 0: 0, 0, 11, 0x24, 35000; encoded: 0x0b24
|
|
[INFO ] CPU #1 initialized
|
|
[DEBUG] CPU 1 going down...
|
|
[INFO ] bsp_do_flight_plan done after 320 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO15 GPIO12 GPIO9 GPIO6 GPIO1 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI15 GPI13 GPI12 GPI11 GPI10 GPI9 GPI8 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 682 msecs
|
|
[DEBUG] DOMAIN: 00000000 init
|
|
[DEBUG] DOMAIN: 00000000 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x2f940 size 0x321 in mcache @0x7f7dd12c
|
|
[INFO ] Found a VBT of 1899 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 23 msecs
|
|
[DEBUG] PCI: 00:00:02.1 init
|
|
[DEBUG] PCI: 00:00:02.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: codec type: Azalia
|
|
[DEBUG] Azalia: base = fe6fc000
|
|
[DEBUG] Azalia: codec_mask = 01
|
|
[WARN ] azalia_audio: cannot find verbs for codec with vendor ID: 0x11060397 (address 0)
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 23 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing ICH7 PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 init
|
|
[DEBUG] Initializing ICH7 PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.1 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] UHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.1 init
|
|
[DEBUG] UHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.1 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.2 init
|
|
[DEBUG] UHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.2 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.3 init
|
|
[DEBUG] UHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.3 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.7 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.7 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1e.0 init
|
|
[DEBUG] PCI: 00:00:1e.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] i82801gx: lpc_init
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power on after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] rtc_failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 45 msecs
|
|
[DEBUG] PCI: 00:00:1f.1 init
|
|
[DEBUG] i82801gx_ide: initializing... IDE0
|
|
[DEBUG] PCI: 00:00:1f.1 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] i82801gx_sata: initializing...
|
|
[DEBUG] SATA controller in plain mode.
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 8 msecs
|
|
[DEBUG] PNP: 002e.1 init
|
|
[DEBUG] PNP: 002e.1 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.2 init
|
|
[DEBUG] PNP: 002e.2 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.5 init
|
|
[DEBUG] PNP: 002e.5 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.9 init
|
|
[DEBUG] PNP: 002e.9 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.209 init
|
|
[DEBUG] PNP: 002e.209 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.309 init
|
|
[DEBUG] PNP: 002e.309 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.a init
|
|
[DEBUG] PNP: 002e.a init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.b init
|
|
[DEBUG] PNP: 002e.b init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.c init
|
|
[DEBUG] PNP: 002e.c init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.307 init
|
|
[DEBUG] PNP: 002e.307 init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 125 / 931 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[INFO ] Devices finalized
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 10 ms
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x2d180 size 0x2729 in mcache @0x7f7dd0d4
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7f657000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 2 core(s) each.
|
|
[DEBUG] clocks between 1600 and 2933 MHz.
|
|
[DEBUG] adding 3 P-States between busratio 6 and b, incl. P0
|
|
[DEBUG] PSS: 2933MHz power 35000 control 0xb24 status 0xb24
|
|
[DEBUG] PSS: 2133MHz power 25000 control 0x81d status 0x81d
|
|
[DEBUG] PSS: 1600MHz power 15000 control 0x616 status 0x616
|
|
[DEBUG] clocks between 1600 and 2933 MHz.
|
|
[DEBUG] adding 3 P-States between busratio 6 and b, incl. P0
|
|
[DEBUG] PSS: 2933MHz power 35000 control 0xb24 status 0xb24
|
|
[DEBUG] PSS: 2133MHz power 25000 control 0x81d status 0x81d
|
|
[DEBUG] PSS: 1600MHz power 15000 control 0x616 status 0x616
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[WARN ] CBFS: 'pci8086,2e33.rom' not found.
|
|
[DEBUG] PCI Option ROM loading disabled for PCI: 00:00:02.1
|
|
[WARN ] PCI: 00:00:02.1: Missing PCI Option ROM
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] ACPI: * SPCR
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] current = 7f65a0c0
|
|
[DEBUG] current = 7f65a0c0
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 12544 bytes.
|
|
[DEBUG] smbios_write_tables: 7f64f000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '26.06-216-gb4ebd461d9f4-dirty'
|
|
[DEBUG] SMBIOS tables: 551 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d076
|
|
[DEBUG] Writing coreboot table at 0x7f67b000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007f64efff: RAM
|
|
[DEBUG] 6. 000000007f64f000-000000007f696fff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007f697000-000000007f7cefff: RAMSTAGE
|
|
[DEBUG] 8. 000000007f7cf000-000000007f7fffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 000000007f800000-0000000083ffffff: RESERVED
|
|
[DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
|
|
[DEBUG] 11. 00000000fed10000-00000000ffffffff: RESERVED
|
|
[DEBUG] 12. 0000000100000000-000000027bffffff: RAM
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[DEBUG] Wrote coreboot table at: 0x7f67b000, 0x3d4 bytes, checksum a304
|
|
[DEBUG] coreboot table: 1004 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7f7de000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7f7dd000 0x00000404
|
|
[DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910
|
|
[DEBUG] AFTER CAR 5. 0x7f7cf000 0x0000d000
|
|
[DEBUG] RAMSTAGE 6. 0x7f696000 0x00139000
|
|
[DEBUG] SMM BACKUP 7. 0x7f686000 0x00010000
|
|
[DEBUG] IGD OPREGION 8. 0x7f683000 0x00002800
|
|
[DEBUG] COREBOOT 9. 0x7f67b000 0x00008000
|
|
[DEBUG] ACPI 10. 0x7f657000 0x00024000
|
|
[DEBUG] SMBIOS 11. 0x7f64f000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7f7feb20 0x000000e0
|
|
[DEBUG] MRC DATA 2. 0x7f7fe900 0x00000208
|
|
[DEBUG] ROMSTAGE 3. 0x7f7fe8e0 0x00000004
|
|
[DEBUG] ROMSTG STCK 4. 0x7f7fe840 0x00000088
|
|
[DEBUG] ACPI GNVS 5. 0x7f7fe740 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 6 / 400 ms
|
|
[DEBUG] Starting cbfs_boot_device
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x6b580 size 0x11bf2 in mcache @0x7f7dd340
|
|
[DEBUG] Checking segment from ROM address 0xff87c5ac
|
|
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
|
|
[DEBUG] Checking segment from ROM address 0xff87c5c8
|
|
[DEBUG] Loading segment from ROM address 0xff87c5ac
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x000de0c0 memsize 0x21f40 srcaddr 0xff87c5e4 filesize 0x11bba
|
|
[DEBUG] Loading Segment: addr: 0x000de0c0 memsz: 0x0000000000021f40 filesz: 0x0000000000011bba
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xff87c5c8
|
|
[DEBUG] Entry Point 0x000fd253
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 38 / 71 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x000fd253(0x7f67b000)
|
|
SeaBIOS (version rel-1.17.0-0-gb52ca86e)
|
|
BUILD: gcc: (coreboot toolchain v2026-07-03_5761e7af80) 15.2.0 binutils: (GNU Binutils) 2.46.1
|
|
SeaBIOS (version rel-1.17.0-0-gb52ca86e)
|
|
BUILD: gcc: (coreboot toolchain v2026-07-03_5761e7af80) 15.2.0 binutils: (GNU Binutils) 2.46.1
|
|
Found coreboot cbmem console @ 7f7de000
|
|
Found mainboard ASUS P5G41C-M LX
|
|
Relocating init from 0x000df840 to 0x7e641b40 (size 54304)
|
|
Found CBFS header at 0xff81102c
|
|
multiboot: eax=7f6c1078, ebx=7f6c1044
|
|
Found 18 PCI devices (max PCI bus is 04)
|
|
Copying SMBIOS from 0x7f64f000 to 0x000f5b00
|
|
Copying SMBIOS 3.0 from 0x7f64f020 to 0x000f5ae0
|
|
Copying ACPI RSDP from 0x7f657000 to 0x000f5ab0
|
|
table(50434146)=0x7f6599c0 (via xsdt)
|
|
Using pmtimer, ioport 0x508
|
|
EHCI init on dev 00:1d.7 (regs=0xfe6fb020)
|
|
UHCI init on dev 00:1d.0 (io=ffe0)
|
|
UHCI init on dev 00:1d.1 (io=ffc0)
|
|
UHCI init on dev 00:1d.2 (io=ffa0)
|
|
UHCI init on dev 00:1d.3 (io=ff80)
|
|
ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9)
|
|
ATA controller 2 at 170/374/0 (irq 15 dev f9)
|
|
ATA controller 3 at ff40/ff2c/0 (irq 0 dev fa)
|
|
ATA controller 4 at ff38/ff28/0 (irq 0 dev fa)
|
|
Got ps2 nak (status=51)
|
|
Searching bootorder for: HALT
|
|
Found 1 lpt ports
|
|
Found 1 serial ports
|
|
Scan for VGA option rom
|
|
ata2-0: Samsung SSD 850 EVO 250GB ATA-9 Hard-Disk (232 GiBytes)
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
Running option rom at c000:0003
|
|
sercon: using ioport 0x3f8
|
|
sercon: configuring in splitmode (vgabios c000:0014)
|
|
Turning on vga text mode console
|
|
cAll threads complete.
|
|
SeaBIOS (version rel-1.17.0-0-gb52ca86eScan for option roms
|
|
)
|
|
Running option rom at cc80:0003
|
|
|
|
|
|
iPXE (https://ipxe.org) 03:00.0 CC80 PCI2.10 PnP PMpmm call arg1=1
|
|
pmm call arg1=0
|
|
M+7E62B48pmm call arg1=1
|
|
pmm call arg1=0
|
|
0+7E56B480 CC80
|
|
Searching bootorder for: /pci@i0cf8/pci-bridge@1c,1/*@0
|
|
|
|
|
|
|
|
|
|
Press ESC for boot menu.
|
|
|
|
Select boot device:
|
|
|
|
1. ata2-0: Samsung SSD 850 EVO 250GB ATA-9 Hard-Disk (232 GiBytes)
|
|
2. iPXE (PCI 03:00.0)
|
|
Searching bootorder for: HALT
|
|
drive 0x000f59f0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=488397168
|
|
Space available for UMB: cd800-ec000, f5320-f59f0
|
|
Returned 16777216 bytes of ZoneHigh
|
|
e820 map has 8 items:
|
|
0: 0000000000000000 - 000000000009fc00 = 1 RAM
|
|
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
|
|
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
|
|
3: 0000000000100000 - 000000007f64f000 = 1 RAM
|
|
4: 000000007f64f000 - 0000000084000000 = 2 RESERVED
|
|
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
|
|
6: 00000000fed10000 - 0000000100000000 = 2 RESERVED
|
|
7: 0000000100000000 - 000000027c000000 = 1 RAM
|
|
|
|
enter handle_19:
|
|
NULL
|
|
Booting from ROM..Booting from cc80:0386
|
|
.
|
|
iPXE (PCI 03:00.0) starting execution...ok
|
|
iPXE initialising devices...ok
|
|
|
|
|
|
|
|
iPXE 1.21.1+ (g7099) -- Open Source Network Boot Firmware -- https://ipxe.org
|
|
Features: DNS HTTP TFTP ELF MBOOT PXE bzImage Menu PXEXT
|
|
|
|
Press Ctrl-B for the iPXE command line..No more network devices
|
|
|
|
Press Ctrl-B for the iPXE command line..enter handle_18:
|
|
NULL
|
|
Booting from Hard Disk..Booting from 0000:7c00
|
|
.
|
|
GRUB loading.
|
|
Welcome to GRUB!
|
|
|
|
GNU GRUB version 2.12-9+deb13u2
|
|
|
|
+----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted.
|
|
Press enter to boot the selected OS, `e' to edit the commands
|
|
before booting or `c' for a command-line. *Devuan GNU/Linux Advanced options for Devuan GNU/Linux The highlighted entry will be executed automatically in 5s. Loading Linux 6.12.95+deb13-amd64 ...
|
|
Loading initial ramdisk ...
|
|
/dev/sda1: clean, 60735/15269888 files, 1820549/61049390 blocks
|
|
INIT: version 3.14 booting
|
|
INIT: No inittab.d directory found
|
|
|
|
OpenRC 0.56 is starting up Linux 6.12.95+deb13-amd64 (x86_64)
|
|
|
|
* /proc is already mounted
|
|
* /run/openrc: creating directory
|
|
* /run/lock: creating directory
|
|
* /run/lock: correcting owner
|
|
* Caching service dependencies ...
|
|
Error: udev is the name of a real and virtual service.
|
|
[ ok ]
|
|
Starting hot-plug events dispatcher: udevd.
|
|
Synthesizing the initial hotplug events (subsystems)...done.
|
|
Synthesizing the initial hotplug events (devices)...done.
|
|
Waiting for /dev to be fully populated...done.
|
|
Starting boot logger: bootlogdSetting up keyboard layout...done.
|
|
Activating swap...done.
|
|
Checking file systems...done.
|
|
Cleaning up temporary files... /tmp.
|
|
Mounting local filesystems...done.
|
|
Activating swapfile swap, if any...done.
|
|
Cleaning up temporary files....
|
|
Starting: AppArmorLoading AppArmor profiles...done.
|
|
.
|
|
Starting Setting kernel variables: sysctl.
|
|
Configuring network interfaces...Starting RPC port mapper daemon: rpcbind.
|
|
Starting NFS common utilities: statd idmapd.
|
|
done.
|
|
Already running: rpcbind.
|
|
Starting NFS common utilities: statd idmapd.
|
|
Cleaning up temporary files....
|
|
Starting Write boot and shutdown times into wtmpdb: wtmpdb-update-boot.
|
|
Setting up X socket directories... /tmp/.X11-unix /tmp/.ICE-unix.
|
|
INIT: Entering runlevel: 2
|
|
Setting up console font and keymap...done.
|
|
Starting enhanced syslogd: rsyslogd.
|
|
Starting periodic command scheduler: cron.
|
|
Starting system message bus: dbus.
|
|
Starting OpenBSD Secure Shell server: sshd.
|
|
|
|
Devuan GNU/Linux excalibur devuan ttyS0
|
|
|
|
devuan login: root
|
|
Password:
|
|
Linux devuan 6.12.95+deb13-amd64 #1 SMP PREEMPT_DYNAMIC Debian 6.12.95-1 (2026-07-04) x86_64
|
|
|
|
The programs included with the Devuan GNU/Linux system are free software;
|
|
the exact distribution terms for each program are described in the
|
|
individual files in /usr/share/doc/*/copyright.
|
|
|
|
Devuan GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
|
|
permitted by applicable law.
|
|
COLUMNS=119;
|
|
LINES=27;
|
|
export COLUMNS LINES;
|
|
root@devuan:~# etip addr
|
|
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000
|
|
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
|
|
inet 127.0.0.1/8 scope host lo
|
|
valid_lft forever preferred_lft forever
|
|
inet6 ::1/128 scope host proto kernel_lo
|
|
valid_lft forever preferred_lft forever
|
|
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc fq_codel state UP group default qlen 1000
|
|
link/ether 00:00:00:00:00:30 brd ff:ff:ff:ff:ff:ff
|
|
inet 192.168.0.29/24 brd 192.168.0.255 scope global eth0
|
|
valid_lft forever preferred_lft forever
|
|
inet6 fe80::200:ff:fe00:30/64 scope link proto kernel_ll
|
|
valid_lft forever preferred_lft forever
|
|
root@devuan:~# ethtool -p eth0
|
|
Cannot identify NIC: Operation not supported
|
|
root@devuan:~# lspci
|
|
|
|
.bash_history hpeltt-6.7.0.7-4.x86_64.rpm jre.zip rom.bin
|
|
.bashrc hpeltt_6.7.0.7-5_amd64.deb .lesshst .ssh/
|
|
.config/ hpe_ltt67_linux_x86_64.tar .local/ superio.1.log
|
|
coreboot.log install_hpeltt .lttreg vga.bios.bin
|
|
hpe_ltt60_win.exe jre/ .profile
|
|
root@devuan:~# lspci -tv
|
|
-[0000:00]-+-00.0 Intel Corporation 4 Series Chipset DRAM Controller
|
|
+-01.0-[01]--
|
|
+-02.0 Intel Corporation 4 Series Chipset Integrated Graphics Controller
|
|
+-02.1 Intel Corporation 4 Series Chipset Integrated Graphics Controller
|
|
+-1b.0 Intel Corporation NM10/ICH7 Family High Definition Audio Controller
|
|
+-1c.0-[02]--
|
|
+-1c.1-[03]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller
|
|
+-1d.0 Intel Corporation NM10/ICH7 Family USB UHCI Controller #1
|
|
+-1d.1 Intel Corporation NM10/ICH7 Family USB UHCI Controller #2
|
|
+-1d.2 Intel Corporation NM10/ICH7 Family USB UHCI Controller #3
|
|
+-1d.3 Intel Corporation NM10/ICH7 Family USB UHCI Controller #4
|
|
+-1d.7 Intel Corporation NM10/ICH7 Family USB2 EHCI Controller
|
|
+-1e.0-[04]--
|
|
+-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge
|
|
+-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller
|
|
+-1f.2 Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode]
|
|
\-1f.3 Intel Corporation NM10/ICH7 Family SMBus Controller
|
|
root@devuan:~# htop
|
|
2206 root 20 0 7824 4020 3272 R 0.7 0.0 0:00.03 htop 1 root 20 0 3492 2068 1920 S 0.0 0.0 0:00.51 init [2]0.00.00.00.00.00.00.00.00.00.00.0M21 /usr/sbin/rsyslogd2037 root20 0 6856 2008 1764 S N/A 0.0 0:00.00 /usr/sbin/cron[Main] [I/O]
|
|
2206 root 20 0 7824 4020 3272 R 0.7 0.0 0:00.04 htop 1 root 20 0 3492 2068 1920 S 0.0 0.0 0:00.51 init [2] tty6|4M|2 0.065
|
|
2206 root 20 0 7824 4020 3272 R 0.7 0.0 0:00.05 htop 1 root 20 0 3492 2068 1920 S 0.0 0.0 0:00.51 init [2] 0306M|78
|
|
2206 root 20 0 7824 4020 3272 R 0.7 0.0 0:00.07 htop 1 root 20 0 3492 2068 1920 S 0.0 0.0 0:00.51 init [2] tty6|73M|4
|
|
>root@devuan:~# lspci 0 7824 4020 3272 R 0.7 0.0 0:00.08 htop 1 root 20 0 3492 2068 1920 S 0.0 0.0 0:00.51 init [2] tty6M|77
|
|
00:00.0 Host bridge: Intel Corporation 4 Series Chipset DRAM Controller (rev 03)
|
|
00:01.0 PCI bridge: Intel Corporation 4 Series Chipset PCI Express Root Port (rev 03)
|
|
00:02.0 VGA compatible controller: Intel Corporation 4 Series Chipset Integrated Graphics Controller (rev 03)
|
|
00:02.1 Display controller: Intel Corporation 4 Series Chipset Integrated Graphics Controller (rev 03)
|
|
00:1b.0 Audio device: Intel Corporation NM10/ICH7 Family High Definition Audio Controller (rev 01)
|
|
00:1c.0 PCI bridge: Intel Corporation NM10/ICH7 Family PCI Express Port 1 (rev 01)
|
|
00:1c.1 PCI bridge: Intel Corporation NM10/ICH7 Family PCI Express Port 2 (rev 01)
|
|
00:1d.0 USB controller: Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 (rev 01)
|
|
00:1d.1 USB controller: Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 (rev 01)
|
|
00:1d.2 USB controller: Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 (rev 01)
|
|
00:1d.3 USB controller: Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 (rev 01)
|
|
00:1d.7 USB controller: Intel Corporation NM10/ICH7 Family USB2 EHCI Controller (rev 01)
|
|
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1)
|
|
00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge (rev 01)
|
|
00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 01)
|
|
00:1f.2 IDE interface: Intel Corporation NM10/ICH7 Family SATA Controller [IDE mode] (rev 01)
|
|
00:1f.3 SMBus: Intel Corporation NM10/ICH7 Family SMBus Controller (rev 01)
|
|
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller (rev 03)
|
|
root@devuan:~# cbmem -c | l
|