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Bug #659 ยป latitude_7480_cbmem.log

Gabriel Turlea, 07/20/2026 12:00 AM

 


[NOTE ] coreboot-25.12-408-gf0678e3639e2-dirty Sun Feb 08 00:30:33 UTC 2026 x86_32 bootblock starting (log level: 8)...
[DEBUG] CPU: Intel(R) Core(TM) i7-7600U CPU @ 2.80GHz
[DEBUG] CPU: ID 806e9, Kabylake H0, ucode: 000000f5
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 5904 (rev 02) is Kabylake-U
[DEBUG] PCH: device id 9d4e (rev 21) is Kabylake-U iHDCP 2.2 Premium
[DEBUG] IGD: device id 5916 (rev 02) is Kaby Lake ULT GT2
[DEBUG] Starting cbfs_boot_device
[DEBUG] Starting cbfs_boot_device
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x760000.
[DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 8
[DEBUG] FMAP: area COREBOOT found @ 761000 (9039872 bytes)
[INFO ] Booting from COREBOOT region
[INFO ] CBFS: mcache @0xfef04e00 built for 22 files, used 0x464 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x67dc0 size 0xf650 in mcache @0xfef04e8c
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 103 ms


[NOTE ] coreboot-25.12-408-gf0678e3639e2-dirty Sun Feb 08 00:30:33 UTC 2026 x86_32 romstage starting (log level: 8)...
[CRIT ] HECI: reset failed
[DEBUG] pm1_sts: 8101 pm1_en: 4100 pm1_cnt: 00001c00
[DEBUG] gpe0_sts[0]: 00000008 gpe0_en[0]: 00000000
[DEBUG] gpe0_sts[1]: 00001000 gpe0_en[1]: 00000000
[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG] gpe0_sts[3]: 00004000 gpe0_en[3]: 00000000
[DEBUG] TCO_STS: 0000 0000
[DEBUG] GEN_PMCON: e0840200 00001800
[DEBUG] GBLRST_CAUSE: 00000000 00000000
[DEBUG] PM1_STS: WAK PWRBTN TMROF
[DEBUG] prev_sleep_state 5 (S5)
[DEBUG] Starting cbfs_boot_device
[DEBUG] FMAP: area COREBOOT found @ 761000 (9039872 bytes)
[INFO ] Booting from COREBOOT region
[INFO ] CBFS: Found 'fspm.bin' @0x97fc0 size 0x63000 in mcache @0xfef05098
[DEBUG] FMAP: area RW_MRC_CACHE found @ 750000 (65536 bytes)
[SPEW ] MRC cache found, size 6248 bytes
[SPEW ] bootmode is set to: 2 (boot assuming no config change)
[DEBUG] MSR_PRMRR_VALID_CONFIG = 0x000000e1
[DEBUG] PRMRR size set to 128 MiB
[INFO ] No memory dimm at address A0
[DEBUG] SPD @ 0x52
[INFO ] SPD: module type is DDR4
[INFO ] SPD: module part number is 16ATF1G64HZ-2G1A2
[INFO ] SPD: banks 16, ranks 2, rows 15, columns 10, density 4096 Mb
[INFO ] SPD: device width 8 bits, bus width 64 bits
[INFO ] SPD: module size is 8192 MB (per channel)
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x6ffff000 254 entries.
[DEBUG] IMD: root @ 0x6fffec00 62 entries.
[DEBUG] Starting cbfs_boot_device
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x783ff000 254 entries.
[DEBUG] IMD: root @ 0x783fec00 62 entries.
[DEBUG] FMAP: area RW_MRC_CACHE found @ 750000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG] 1 DIMMs found
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x78000000 0x800000
[DEBUG] Subregion 0: 0x78000000 0x200000
[DEBUG] Subregion 1: 0x78200000 0x200000
[DEBUG] Subregion 2: 0x78400000 0x400000
[DEBUG] top_of_ram = 0x70000000
[DEBUG] Normal boot
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'fallback/postcar' @0x12f080 size 0x6048 in mcache @0xfef05138
[DEBUG] Loading module at 0x6fbcd000 with entry 0x6fbcd031. filesize: 0x5c88 memsize: 0xbfd8
[DEBUG] Processing 224 relocs. Offset value of 0x6dbcd000
[DEBUG] BS: romstage times (exec / console): total (unknown) / 282 ms


[NOTE ] coreboot-25.12-408-gf0678e3639e2-dirty Sun Feb 08 00:30:33 UTC 2026 x86_32 postcar starting (log level: 8)...
[DEBUG] Normal boot
[DEBUG] Starting cbfs_boot_device
[DEBUG] FMAP: area COREBOOT found @ 761000 (9039872 bytes)
[INFO ] Booting from COREBOOT region
[INFO ] CBFS: Found 'fallback/ramstage' @0x77480 size 0x1bae5 in mcache @0x6fbdd0ec
[DEBUG] Loading module at 0x6fa83000 with entry 0x6fa83000. filesize: 0x38258 memsize: 0x148770
[DEBUG] Processing 4374 relocs. Offset value of 0x6ba83000
[DEBUG] BS: postcar times (exec / console): total (unknown) / 58 ms


[NOTE ] coreboot-25.12-408-gf0678e3639e2-dirty Sun Feb 08 00:30:33 UTC 2026 x86_32 ramstage starting (log level: 8)...
[DEBUG] Normal boot
[DEBUG] Starting cbfs_boot_device
[DEBUG] FMAP: area COREBOOT found @ 761000 (9039872 bytes)
[INFO ] Booting from COREBOOT region
[INFO ] CBFS: Found 'fsps.bin' @0xfb000 size 0x23ff2 in mcache @0x6fbdd2d8
[DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called
[DEBUG] iGPU present - GFXVT_BASE_ADDRESS set
[INFO ] FSPS, status=0x00000000
[DEBUG] Detected 2 core, 4 thread CPU.
[DEBUG] Setting up SMI for CPU
[DEBUG] IED base = 0x78400000
[DEBUG] IED size = 0x00400000
[INFO ] Will perform SMM setup.
[DEBUG] microcode: sig=0x806e9 pf=0x80 revision=0xf6
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x67c00 in mcache @0x6fbdd02c
[INFO ] CPU: Intel(R) Core(TM) i7-7600U CPU @ 2.80GHz.
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] CPU: APIC: 00 enabled
[DEBUG] CPU: APIC: 01 enabled
[DEBUG] CPU: APIC: 02 enabled
[DEBUG] CPU: APIC: 03 enabled
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[SPEW ] APs are ready after 0us
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[INFO ] LAPIC 0x1 in XAPIC mode.
[SPEW ] APs are ready after 0us
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000f6
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] AP: slot 2 apic_id 2, MCU rev: 0x000000f6
[INFO ] AP: slot 3 apic_id 3, MCU rev: 0x000000f6
[SPEW ] APs are ready after 25900us
[SPEW ] smm_setup_relocation_handler: enter
[SPEW ] smm_setup_relocation_handler: exit
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
[DEBUG] smm_module_setup_stub: stack_top = 0x78002000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x6fa9e80e
[DEBUG] Installing permanent SMM handler to 0x78000000
[DEBUG] HANDLER [0x781ff000-0x781ffe5f]

[DEBUG] CPU 0
[DEBUG] ss0 [0x781fec00-0x781fefff]
[DEBUG] stub0 [0x781f7000-0x781f719f]

[DEBUG] CPU 1
[DEBUG] ss1 [0x781fe800-0x781febff]
[DEBUG] stub1 [0x781f6c00-0x781f6d9f]

[DEBUG] CPU 2
[DEBUG] ss2 [0x781fe400-0x781fe7ff]
[DEBUG] stub2 [0x781f6800-0x781f699f]

[DEBUG] CPU 3
[DEBUG] ss3 [0x781fe000-0x781fe3ff]
[DEBUG] stub3 [0x781f6400-0x781f659f]

[DEBUG] stacks [0x78000000-0x78001fff]
[DEBUG] Loading module at 0x781ff000 with entry 0x781ff027. filesize: 0xe50 memsize: 0xe60
[DEBUG] Processing 84 relocs. Offset value of 0x781ff000
[DEBUG] Loading module at 0x781f7000 with entry 0x781f7000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG] Processing 9 relocs. Offset value of 0x781f7000
[DEBUG] smm_module_setup_stub: stack_top = 0x78002000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG] SMM Module: placing smm entry code at 781f6c00, cpu # 0x1
[SPEW ] smm_place_entry_code: copying from 781f7000 to 781f6c00 0x1a0 bytes
[DEBUG] SMM Module: placing smm entry code at 781f6800, cpu # 0x2
[SPEW ] smm_place_entry_code: copying from 781f7000 to 781f6800 0x1a0 bytes
[DEBUG] SMM Module: placing smm entry code at 781f6400, cpu # 0x3
[SPEW ] smm_place_entry_code: copying from 781f7000 to 781f6400 0x1a0 bytes
[DEBUG] SMM Module: stub loaded at 781f7000. Will call 0x781ff027
[DEBUG] Clearing SMI status registers
[DEBUG] SMI_STS: PM1
[DEBUG] PM1_STS: TMROF
[DEBUG] GPE0 STD STS: eSPI
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x781ef000, cpu = 0
[DEBUG] In relocation handler: CPU 0
[DEBUG] New SMBASE=0x781ef000 IEDBASE=0x78400000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x781eec00, cpu = 1
[DEBUG] In relocation handler: CPU 1
[DEBUG] New SMBASE=0x781eec00 IEDBASE=0x78400000
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x781ee800, cpu = 2
[DEBUG] In relocation handler: CPU 2
[DEBUG] New SMBASE=0x781ee800 IEDBASE=0x78400000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xff800800
[DEBUG] Relocation complete.
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x781ee400, cpu = 3
[DEBUG] In relocation handler: CPU 3
[DEBUG] New SMBASE=0x781ee400 IEDBASE=0x78400000
[DEBUG] Relocation complete.
[SPEW ] APs are ready after 75500us
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor Intel device 806e9
[DEBUG] CPU: family 06, model 8e, stepping 09
[INFO ] SGX: prmrr_base = 0x70000000
[INFO ] SGX: prmrr_mask = 0x7ff8000c00
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[INFO ] Turbo is available and visible
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #1
[INFO ] Initializing CPU #2
[INFO ] Initializing CPU #3
[DEBUG] CPU: vendor Intel device 806e9
[DEBUG] CPU: family 06, model 8e, stepping 09
[DEBUG] CPU: vendor Intel device 806e9
[DEBUG] CPU: family 06, model 8e, stepping 09
[INFO ] SGX: prmrr_base = 0x70000000
[INFO ] SGX: prmrr_mask = 0x7ff8000c00
[DEBUG] CPU: vendor Intel device 806e9
[DEBUG] CPU: family 06, model 8e, stepping 09
[DEBUG] Clearing out pending MCEs
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[DEBUG] Clearing out pending MCEs
[DEBUG] cpu: energy policy set to 6
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] CPU #2 initialized
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] CPU #3 initialized
[DEBUG] cpu: energy policy set to 6
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] CPU #1 initialized
[SPEW ] APs are ready after 106800us
[INFO ] bsp_do_flight_plan done after 545 msecs.
[DEBUG] CPU: frequency set to 3900 MHz
[DEBUG] Enabling SMIs.
[DEBUG] Locking SMM.
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
[INFO ] microcode: Update skipped, already up-to-date
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
[INFO ] SGX: MCHECK did not approve SGX PRMRR
[DEBUG] IA32_FEATURE_CONTROL already locked
[INFO ] SGX: MCHECK did not approve SGX PRMRR
[INFO ] microcode: Update skipped, already up-to-date
[INFO ] SGX: MCHECK did not approve SGX PRMRR
[INFO ] SGX: MCHECK did not approve SGX PRMRR
[DEBUG] IA32_FEATURE_CONTROL already locked
[DEBUG] IA32_FEATURE_CONTROL already locked
[INFO ] ITSS IRQ Polarities Before:
[DEBUG] IA32_FEATURE_CONTROL already locked
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000000
[INFO ] IPC3: 0x00000000
[INFO ] ITSS IRQ Polarities After:
[INFO ] IPC0: 0x00ff4000
[INFO ] IPC1: 0x00000007
[INFO ] IPC2: 0x00000002
[INFO ] IPC3: 0x00000000
[INFO ] Found PCIe Root Port #1 at PCI: 00:1c.0.
[INFO ] Found PCIe Root Port #3 at PCI: 00:1c.2.
[INFO ] Found PCIe Root Port #5 at PCI: 00:1c.4.
[INFO ] Found PCIe Root Port #9 at PCI: 00:1d.0.
[NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:00:1c.7) which was enabled in devicetree, removing and disabling.
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 1575 / 609 ms
[INFO ] Enumerating buses...
[SPEW ] Show all devs... Before device enumeration.
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] DOMAIN: 00000000: enabled 1
[SPEW ] GPIO: 0: enabled 1
[SPEW ] PCI: 00:00:00.0: enabled 1
[SPEW ] PCI: 00:00:01.0: enabled 0
[SPEW ] PCI: 00:00:01.1: enabled 0
[SPEW ] PCI: 00:00:01.2: enabled 0
[SPEW ] PCI: 00:00:02.0: enabled 1
[SPEW ] PCI: 00:00:04.0: enabled 1
[SPEW ] PCI: 00:00:05.0: enabled 0
[SPEW ] PCI: 00:00:07.0: enabled 0
[SPEW ] PCI: 00:00:08.0: enabled 0
[SPEW ] PCI: 00:00:13.0: enabled 0
[SPEW ] PCI: 00:00:14.0: enabled 1
[SPEW ] PCI: 00:00:14.1: enabled 0
[SPEW ] PCI: 00:00:14.2: enabled 1
[SPEW ] PCI: 00:00:14.3: enabled 0
[SPEW ] PCI: 00:00:15.0: enabled 1
[SPEW ] PCI: 00:00:15.1: enabled 1
[SPEW ] PCI: 00:00:15.2: enabled 1
[SPEW ] PCI: 00:00:15.3: enabled 0
[SPEW ] PCI: 00:00:16.0: enabled 1
[SPEW ] PCI: 00:00:16.1: enabled 0
[SPEW ] PCI: 00:00:16.2: enabled 0
[SPEW ] PCI: 00:00:16.3: enabled 0
[SPEW ] PCI: 00:00:16.4: enabled 0
[SPEW ] PCI: 00:00:17.0: enabled 1
[SPEW ] PCI: 00:00:19.0: enabled 1
[SPEW ] PCI: 00:00:19.1: enabled 0
[SPEW ] PCI: 00:00:19.2: enabled 0
[SPEW ] PCI: 00:00:1b.0: enabled 0
[SPEW ] PCI: 00:00:1b.1: enabled 0
[SPEW ] PCI: 00:00:1b.2: enabled 0
[SPEW ] PCI: 00:00:1b.3: enabled 0
[SPEW ] PCI: 00:00:1b.4: enabled 0
[SPEW ] PCI: 00:00:1b.5: enabled 0
[SPEW ] PCI: 00:00:1b.6: enabled 0
[SPEW ] PCI: 00:00:1b.7: enabled 0
[SPEW ] PCI: 00:00:1c.0: enabled 1
[SPEW ] PCI: 00:00:1c.1: enabled 0
[SPEW ] PCI: 00:00:1c.2: enabled 1
[SPEW ] PCI: 00:00:1c.3: enabled 0
[SPEW ] PCI: 00:00:1c.4: enabled 1
[SPEW ] PCI: 00:00:1c.5: enabled 0
[SPEW ] PCI: 00:00:1c.6: enabled 0
[SPEW ] PCI: 00:00:1c.7: enabled 0
[SPEW ] PCI: 00:00:1d.0: enabled 1
[SPEW ] PCI: 00:00:1d.1: enabled 0
[SPEW ] PCI: 00:00:1d.2: enabled 0
[SPEW ] PCI: 00:00:1d.3: enabled 0
[SPEW ] PCI: 00:00:1d.4: enabled 0
[SPEW ] PCI: 00:00:1d.5: enabled 0
[SPEW ] PCI: 00:00:1d.6: enabled 0
[SPEW ] PCI: 00:00:1d.7: enabled 0
[SPEW ] PCI: 00:00:1e.0: enabled 0
[SPEW ] PCI: 00:00:1e.1: enabled 0
[SPEW ] PCI: 00:00:1e.2: enabled 0
[SPEW ] PCI: 00:00:1e.3: enabled 0
[SPEW ] PCI: 00:00:1e.4: enabled 0
[SPEW ] PCI: 00:00:1e.5: enabled 0
[SPEW ] PCI: 00:00:1e.6: enabled 0
[SPEW ] PCI: 00:00:1f.0: enabled 1
[SPEW ] PCI: 00:00:1f.1: enabled 1
[SPEW ] PCI: 00:00:1f.2: enabled 1
[SPEW ] PCI: 00:00:1f.3: enabled 1
[SPEW ] PCI: 00:00:1f.4: enabled 1
[SPEW ] PCI: 00:00:1f.5: enabled 0
[SPEW ] PCI: 00:00:1f.6: enabled 1
[SPEW ] PCI: 00:00:1f.7: enabled 0
[SPEW ] USB0 port 0: enabled 0
[SPEW ] PNP: 00ff.0: enabled 1
[SPEW ] USB2 port 0: enabled 0
[SPEW ] USB2 port 1: enabled 0
[SPEW ] USB2 port 2: enabled 0
[SPEW ] USB2 port 3: enabled 0
[SPEW ] USB2 port 4: enabled 0
[SPEW ] USB2 port 5: enabled 0
[SPEW ] USB2 port 6: enabled 0
[SPEW ] USB2 port 7: enabled 0
[SPEW ] USB2 port 8: enabled 0
[SPEW ] USB2 port 9: enabled 0
[SPEW ] USB3 port 0: enabled 0
[SPEW ] USB3 port 1: enabled 0
[SPEW ] USB3 port 2: enabled 0
[SPEW ] USB3 port 3: enabled 0
[SPEW ] USB3 port 4: enabled 0
[SPEW ] USB3 port 5: enabled 0
[SPEW ] APIC: 00: enabled 1
[SPEW ] APIC: 01: enabled 1
[SPEW ] APIC: 02: enabled 1
[SPEW ] APIC: 03: enabled 1
[SPEW ] Compare with tree...
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] APIC: 00: enabled 1
[SPEW ] APIC: 01: enabled 1
[SPEW ] APIC: 02: enabled 1
[SPEW ] APIC: 03: enabled 1
[SPEW ] DOMAIN: 00000000: enabled 1
[SPEW ] GPIO: 0: enabled 1
[SPEW ] PCI: 00:00:00.0: enabled 1
[SPEW ] PCI: 00:00:01.0: enabled 0
[SPEW ] PCI: 00:00:01.1: enabled 0
[SPEW ] PCI: 00:00:01.2: enabled 0
[SPEW ] PCI: 00:00:02.0: enabled 1
[SPEW ] PCI: 00:00:04.0: enabled 1
[SPEW ] PCI: 00:00:05.0: enabled 0
[SPEW ] PCI: 00:00:07.0: enabled 0
[SPEW ] PCI: 00:00:08.0: enabled 0
[SPEW ] PCI: 00:00:13.0: enabled 0
[SPEW ] PCI: 00:00:14.0: enabled 1
[SPEW ] USB0 port 0: enabled 0
[SPEW ] USB2 port 0: enabled 0
[SPEW ] USB2 port 1: enabled 0
[SPEW ] USB2 port 2: enabled 0
[SPEW ] USB2 port 3: enabled 0
[SPEW ] USB2 port 4: enabled 0
[SPEW ] USB2 port 5: enabled 0
[SPEW ] USB2 port 6: enabled 0
[SPEW ] USB2 port 7: enabled 0
[SPEW ] USB2 port 8: enabled 0
[SPEW ] USB2 port 9: enabled 0
[SPEW ] USB3 port 0: enabled 0
[SPEW ] USB3 port 1: enabled 0
[SPEW ] USB3 port 2: enabled 0
[SPEW ] USB3 port 3: enabled 0
[SPEW ] USB3 port 4: enabled 0
[SPEW ] USB3 port 5: enabled 0
[SPEW ] PCI: 00:00:14.1: enabled 0
[SPEW ] PCI: 00:00:14.2: enabled 1
[SPEW ] PCI: 00:00:14.3: enabled 0
[SPEW ] PCI: 00:00:15.0: enabled 1
[SPEW ] PCI: 00:00:15.1: enabled 1
[SPEW ] PCI: 00:00:15.2: enabled 1
[SPEW ] PCI: 00:00:15.3: enabled 0
[SPEW ] PCI: 00:00:16.0: enabled 1
[SPEW ] PCI: 00:00:16.1: enabled 0
[SPEW ] PCI: 00:00:16.2: enabled 0
[SPEW ] PCI: 00:00:16.3: enabled 0
[SPEW ] PCI: 00:00:16.4: enabled 0
[SPEW ] PCI: 00:00:17.0: enabled 1
[SPEW ] PCI: 00:00:19.0: enabled 1
[SPEW ] PCI: 00:00:19.1: enabled 0
[SPEW ] PCI: 00:00:19.2: enabled 0
[SPEW ] PCI: 00:00:1b.0: enabled 0
[SPEW ] PCI: 00:00:1b.1: enabled 0
[SPEW ] PCI: 00:00:1b.2: enabled 0
[SPEW ] PCI: 00:00:1b.3: enabled 0
[SPEW ] PCI: 00:00:1b.4: enabled 0
[SPEW ] PCI: 00:00:1b.5: enabled 0
[SPEW ] PCI: 00:00:1b.6: enabled 0
[SPEW ] PCI: 00:00:1b.7: enabled 0
[SPEW ] PCI: 00:00:1c.0: enabled 1
[SPEW ] PCI: 00:00:1c.2: enabled 1
[SPEW ] PCI: 00:00:1c.4: enabled 1
[SPEW ] PCI: 00:00:1d.0: enabled 1
[SPEW ] PCI: 00:00:1d.4: enabled 0
[SPEW ] PCI: 00:00:1d.5: enabled 0
[SPEW ] PCI: 00:00:1d.6: enabled 0
[SPEW ] PCI: 00:00:1d.7: enabled 0
[SPEW ] PCI: 00:00:1e.0: enabled 0
[SPEW ] PCI: 00:00:1e.1: enabled 0
[SPEW ] PCI: 00:00:1e.2: enabled 0
[SPEW ] PCI: 00:00:1e.3: enabled 0
[SPEW ] PCI: 00:00:1e.4: enabled 0
[SPEW ] PCI: 00:00:1e.5: enabled 0
[SPEW ] PCI: 00:00:1e.6: enabled 0
[SPEW ] PCI: 00:00:1f.0: enabled 1
[SPEW ] PNP: 00ff.0: enabled 1
[SPEW ] PCI: 00:00:1f.1: enabled 1
[SPEW ] PCI: 00:00:1f.2: enabled 1
[SPEW ] PCI: 00:00:1f.3: enabled 1
[SPEW ] PCI: 00:00:1f.4: enabled 1
[SPEW ] PCI: 00:00:1f.5: enabled 0
[SPEW ] PCI: 00:00:1f.6: enabled 1
[SPEW ] PCI: 00:00:1f.7: enabled 0
[DEBUG] Root Device scanning...
[SPEW ] scan_static_bus for Root Device
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 00000000 enabled
[DEBUG] DOMAIN: 00000000 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG] PCI: 00:00:00.0 [8086/5904] enabled
[DEBUG] PCI: 00:00:02.0 [8086/5916] enabled
[DEBUG] PCI: 00:00:04.0 [8086/1903] enabled
[DEBUG] PCI: 00:00:14.0 [8086/9d2f] enabled
[DEBUG] PCI: 00:00:14.2 [8086/9d31] enabled
[INFO ] PCI: Static device PCI: 00:00:15.0 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:00:15.1 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:00:15.2 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:00:16.0 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:00:17.0 not found, disabling it.
[DEBUG] PCI: 00:00:19.0 [8086/9d66] enabled
[DEBUG] PCI: 00:00:1c.0 [8086/9d10] enabled
[DEBUG] PCI: 00:00:1c.2 [8086/9d12] enabled
[DEBUG] PCI: 00:00:1c.4 [8086/9d14] enabled
[DEBUG] PCI: 00:00:1d.0 [8086/9d18] enabled
[DEBUG] PCI: 00:00:1f.0 [8086/9d4e] enabled
[DEBUG] PCI: 00:00:1f.1 [8086/9d20] enabled
[DEBUG] PCI: 00:00:1f.2 [8086/9d21] enabled
[DEBUG] PCI: 00:00:1f.3 [8086/9d71] enabled
[DEBUG] PCI: 00:00:1f.4 [8086/9d23] enabled
[DEBUG] PCI: 00:00:1f.6 [8086/15d7] enabled
[DEBUG] GPIO: 0 enabled
[DEBUG] PCI: 00:00:02.0 scanning...
[SPEW ] scan_generic_bus for PCI: 00:00:02.0
[SPEW ] scan_generic_bus for PCI: 00:00:02.0 done
[DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 11 msecs
[DEBUG] PCI: 00:00:14.0 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:14.0
[DEBUG] USB0 port 0 disabled
[SPEW ] scan_static_bus for PCI: 00:00:14.0 done
[DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 14 msecs
[DEBUG] PCI: 00:00:1c.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG] PCI: 00:01:00.0 [10ec/525a] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] L1 Sub-State supported from root port 28
[INFO ] L1 Sub-State Support = 0xf
[INFO ] CommonModeRestoreTime = 0x3c
[INFO ] Power On Value = 0x6, Power On Scale = 0x1
[INFO ] ASPM: Enabled L0s and L1
[INFO ] PCI: 00:01:00.0: Enabled LTR
[INFO ] PCI: 00:01:00.0: Programmed LTR max latencies
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 69 msecs
[DEBUG] PCI: 00:00:1c.2 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.2
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
[SPEW ] PCI: 00:02:00.0 [8086/0000] ops
[DEBUG] PCI: 00:02:00.0 [8086/24fd] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] L1 Sub-State supported from root port 28
[INFO ] L1 Sub-State Support = 0xf
[INFO ] CommonModeRestoreTime = 0x28
[INFO ] Power On Value = 0x16, Power On Scale = 0x0
[INFO ] ASPM: Enabled L1
[INFO ] PCI: 00:02:00.0: Enabled LTR
[INFO ] PCI: 00:02:00.0: Programmed LTR max latencies
[INFO ] PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.2 finished in 73 msecs
[DEBUG] PCI: 00:00:1c.4 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1c.4
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
[INFO ] PCI: 00:00:1c.4: ASPM enabled L0s and L1 (no endpoint)
[INFO ] PCI: 00:00:1c.4: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1c.4 finished in 28 msecs
[DEBUG] PCI: 00:00:1d.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:00:1d.0
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 04
[DEBUG] PCI: 00:04:00.0 [1179/0115] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] L1 Sub-State supported from root port 29
[INFO ] L1 Sub-State Support = 0x5
[INFO ] CommonModeRestoreTime = 0xff
[INFO ] Power On Value = 0xc, Power On Scale = 0x2
[INFO ] ASPM: Enabled L1
[INFO ] PCI: 00:04:00.0: Enabled LTR
[INFO ] PCI: 00:04:00.0: Programmed LTR max latencies
[INFO ] PCI: 00:00:1d.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG] scan_bus: bus PCI: 00:00:1d.0 finished in 74 msecs
[DEBUG] PCI: 00:00:1f.0 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.0
[DEBUG] PNP: 00ff.0 enabled
[SPEW ] scan_static_bus for PCI: 00:00:1f.0 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 14 msecs
[DEBUG] PCI: 00:00:1f.2 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.2
[SPEW ] scan_static_bus for PCI: 00:00:1f.2 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 10 msecs
[DEBUG] PCI: 00:00:1f.3 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.3
[SPEW ] scan_static_bus for PCI: 00:00:1f.3 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 10 msecs
[DEBUG] PCI: 00:00:1f.4 scanning...
[SPEW ] scan_generic_bus for PCI: 00:00:1f.4
[SPEW ] scan_generic_bus for PCI: 00:00:1f.4 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 564 msecs
[SPEW ] scan_static_bus for Root Device done
[DEBUG] scan_bus: bus Root Device finished in 594 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 1387 ms
[INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG] FMAP: area RW_MRC_CACHE found @ 750000 (65536 bytes)
[INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 19 ms
[DEBUG] found VGA at PCI: 00:00:02.0
[DEBUG] Setting up VGA for PCI: 00:00:02.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[SPEW ] Root Device read_resources segment group 0 bus 0
[SPEW ] CPU_CLUSTER: 0 read_resources segment group 0 bus 0
[SPEW ] CPU_CLUSTER: 0 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0
[DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x0, base: 0xe0000000, size: 0x10000000
[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x1, base: 0xfed10000, size: 0x8000
[DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x2, base: 0xfed18000, size: 0x1000
[DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x3, base: 0xfed19000, size: 0x1000
[DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x4, base: 0xfed84000, size: 0x1000
[DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x5, base: 0xfed80000, size: 0x4000
[DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x6, base: 0xfed90000, size: 0x1000
[DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x7, base: 0xfed91000, size: 0x1000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x8, base: 0x0, size: 0xa0000
[SPEW ] dev: PCI: 00:00:00.0, index: 0x9, base: 0xc0000, size: 0x6ff40000
[SPEW ] dev: PCI: 00:00:00.0, index: 0xa, base: 0x70000000, size: 0xd000000
[INFO ] Available memory above 4GB: 6192M
[SPEW ] dev: PCI: 00:00:00.0, index: 0xb, base: 0x100000000, size: 0x183000000
[SPEW ] dev: PCI: 00:00:00.0, index: 0xc, base: 0xa0000, size: 0x20000
[SPEW ] dev: PCI: 00:00:00.0, index: 0xd, base: 0xc0000, size: 0x40000
[SPEW ] PCI: 00:00:14.0 read_resources segment group 0 bus 0
[SPEW ] PCI: 00:00:14.0 read_resources segment group 0 bus 0 done
[SPEW ] PCI: 00:00:1c.0 read_resources segment group 0 bus 1
[SPEW ] PCI: 00:00:1c.0 read_resources segment group 0 bus 1 done
[SPEW ] PCI: 00:00:1c.2 read_resources segment group 0 bus 2
[SPEW ] PCI: 00:00:1c.2 read_resources segment group 0 bus 2 done
[SPEW ] PCI: 00:00:1c.4 read_resources segment group 0 bus 3
[SPEW ] PCI: 00:00:1c.4 read_resources segment group 0 bus 3 done
[SPEW ] PCI: 00:00:1d.0 read_resources segment group 0 bus 4
[SPEW ] PCI: 00:00:1d.0 read_resources segment group 0 bus 4 done
[SPEW ] PCI: 00:00:1f.0 read_resources segment group 0 bus 0
[SPEW ] PCI: 00:00:1f.0 read_resources segment group 0 bus 0 done
[SPEW ] dev: PCI: 00:00:1f.1, index: 0x10, base: 0xfd000000, size: 0x1000000
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
[SPEW ] Show resources in subtree (Root Device)...After reading.
[DEBUG] Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00
[DEBUG] APIC: 00
[DEBUG] APIC: 01
[DEBUG] APIC: 02
[DEBUG] APIC: 03
[DEBUG] DOMAIN: 00000000 child on link 0 GPIO: 0
[SPEW ] DOMAIN: 00000000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ] DOMAIN: 00000000 resource base 70000000 size 0 align 0 gran 0 limit dfffffff flags 40040200 index 10000100
[SPEW ] DOMAIN: 00000000 resource base 100000000 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000200
[DEBUG] GPIO: 0
[DEBUG] PCI: 00:00:00.0
[SPEW ] PCI: 00:00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
[SPEW ] PCI: 00:00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
[SPEW ] PCI: 00:00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
[SPEW ] PCI: 00:00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
[SPEW ] PCI: 00:00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
[SPEW ] PCI: 00:00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
[SPEW ] PCI: 00:00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ] PCI: 00:00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
[SPEW ] PCI: 00:00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 8
[SPEW ] PCI: 00:00:00.0 resource base c0000 size 6ff40000 align 0 gran 0 limit 0 flags e0004200 index 9
[SPEW ] PCI: 00:00:00.0 resource base 70000000 size d000000 align 0 gran 0 limit 0 flags f0000200 index a
[SPEW ] PCI: 00:00:00.0 resource base 100000000 size 183000000 align 0 gran 0 limit 0 flags e0004200 index b
[SPEW ] PCI: 00:00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
[SPEW ] PCI: 00:00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
[DEBUG] PCI: 00:00:01.0
[DEBUG] PCI: 00:00:01.1
[DEBUG] PCI: 00:00:01.2
[DEBUG] PCI: 00:00:02.0
[SPEW ] PCI: 00:00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
[SPEW ] PCI: 00:00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
[SPEW ] PCI: 00:00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
[DEBUG] PCI: 00:00:04.0
[SPEW ] PCI: 00:00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:00:05.0
[DEBUG] PCI: 00:00:07.0
[DEBUG] PCI: 00:00:08.0
[DEBUG] PCI: 00:00:13.0
[DEBUG] PCI: 00:00:14.0 child on link 0 USB0 port 0
[SPEW ] PCI: 00:00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
[DEBUG] USB0 port 0 child on link 0 USB2 port 0
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] USB2 port 2
[DEBUG] USB2 port 3
[DEBUG] USB2 port 4
[DEBUG] USB2 port 5
[DEBUG] USB2 port 6
[DEBUG] USB2 port 7
[DEBUG] USB2 port 8
[DEBUG] USB2 port 9
[DEBUG] USB3 port 0
[DEBUG] USB3 port 1
[DEBUG] USB3 port 2
[DEBUG] USB3 port 3
[DEBUG] USB3 port 4
[DEBUG] USB3 port 5
[DEBUG] PCI: 00:00:14.1
[DEBUG] PCI: 00:00:14.2
[SPEW ] PCI: 00:00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:00:14.3
[DEBUG] PCI: 00:00:15.0
[DEBUG] PCI: 00:00:15.1
[DEBUG] PCI: 00:00:15.2
[DEBUG] PCI: 00:00:15.3
[DEBUG] PCI: 00:00:16.0
[DEBUG] PCI: 00:00:16.1
[DEBUG] PCI: 00:00:16.2
[DEBUG] PCI: 00:00:16.3
[DEBUG] PCI: 00:00:16.4
[DEBUG] PCI: 00:00:17.0
[DEBUG] PCI: 00:00:19.0
[SPEW ] PCI: 00:00:19.0 resource base fe030000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
[SPEW ] PCI: 00:00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
[DEBUG] PCI: 00:00:19.1
[DEBUG] PCI: 00:00:19.2
[DEBUG] PCI: 00:00:1b.0
[DEBUG] PCI: 00:00:1b.1
[DEBUG] PCI: 00:00:1b.2
[DEBUG] PCI: 00:00:1b.3
[DEBUG] PCI: 00:00:1b.4
[DEBUG] PCI: 00:00:1b.5
[DEBUG] PCI: 00:00:1b.6
[DEBUG] PCI: 00:00:1b.7
[DEBUG] PCI: 00:00:1c.0 child on link 0 PCI: 00:01:00.0
[SPEW ] PCI: 00:00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ] PCI: 00:00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:01:00.0
[SPEW ] PCI: 00:01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
[DEBUG] PCI: 00:00:1c.2 child on link 0 PCI: 00:02:00.0
[SPEW ] PCI: 00:00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ] PCI: 00:00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:02:00.0
[SPEW ] PCI: 00:02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:00:1c.4
[SPEW ] PCI: 00:00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ] PCI: 00:00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:00:1d.0 child on link 0 PCI: 00:04:00.0
[SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:04:00.0
[SPEW ] PCI: 00:04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:00:1d.4
[DEBUG] PCI: 00:00:1d.5
[DEBUG] PCI: 00:00:1d.6
[DEBUG] PCI: 00:00:1d.7
[DEBUG] PCI: 00:00:1e.0
[DEBUG] PCI: 00:00:1e.1
[DEBUG] PCI: 00:00:1e.2
[DEBUG] PCI: 00:00:1e.3
[DEBUG] PCI: 00:00:1e.4
[DEBUG] PCI: 00:00:1e.5
[DEBUG] PCI: 00:00:1e.6
[DEBUG] PCI: 00:00:1f.0 child on link 0 PNP: 00ff.0
[SPEW ] PCI: 00:00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
[SPEW ] PCI: 00:00:1f.0 resource base 680 size 80 align 0 gran 0 limit 0 flags c0000100 index 84
[SPEW ] PCI: 00:00:1f.0 resource base 7e0 size 20 align 0 gran 0 limit 0 flags c0000100 index 88
[SPEW ] PCI: 00:00:1f.0 resource base 900 size 80 align 0 gran 0 limit 0 flags c0000100 index 8c
[SPEW ] PCI: 00:00:1f.0 resource base 80 size 10 align 0 gran 0 limit 0 flags c0000100 index 90
[DEBUG] PNP: 00ff.0
[DEBUG] PCI: 00:00:1f.1
[SPEW ] PCI: 00:00:1f.1 resource base fd000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10
[DEBUG] PCI: 00:00:1f.2
[SPEW ] PCI: 00:00:1f.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
[SPEW ] PCI: 00:00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags d0000200 index 48
[SPEW ] PCI: 00:00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 40
[DEBUG] PCI: 00:00:1f.3
[SPEW ] PCI: 00:00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
[SPEW ] PCI: 00:00:1f.3 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 20
[DEBUG] PCI: 00:00:1f.4
[SPEW ] PCI: 00:00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
[SPEW ] PCI: 00:00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
[DEBUG] PCI: 00:00:1f.5
[DEBUG] PCI: 00:00:1f.6
[SPEW ] PCI: 00:00:1f.6 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
[DEBUG] PCI: 00:00:1f.7
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:01:00.0 14 * [0x0 - 0xfff] mem
[DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0x1fff] mem
[DEBUG] PCI: 00:00:1c.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG] PCI: 00:00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 00:04:00.0 10 * [0x0 - 0x3fff] mem
[DEBUG] PCI: 00:00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000680 limit 000006ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 000007e0 limit 000007ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 8c base 00000900 limit 0000097f io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 90 base 00000080 limit 0000008f io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 1000, Size: 800, Tag: 100
[INFO ] * Base: 1900, Size: d6a0, Tag: 100
[INFO ] * Base: efc0, Size: 1040, Tag: 100
[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 00000000 mem: base: 70000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 6fffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 70000000 limit 7cffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 282ffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:19.0 10 base fe030000 limit fe030fff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed)
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed)
[INFO ] DOMAIN: 00000000: Resource ranges:
[INFO ] * Base: 7d000000, Size: 63000000, Tag: 200
[INFO ] * Base: 283000000, Size: 7d7d000000, Tag: 200
[DEBUG] PCI: 00:00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem
[DEBUG] PCI: 00:00:02.0 10 * [0xcf000000 - 0xcfffffff] limit: cfffffff mem
[DEBUG] PCI: 00:00:1c.0 20 * [0xcef00000 - 0xceffffff] limit: ceffffff mem
[DEBUG] PCI: 00:00:1c.2 20 * [0xcee00000 - 0xceefffff] limit: ceefffff mem
[DEBUG] PCI: 00:00:1d.0 20 * [0xced00000 - 0xcedfffff] limit: cedfffff mem
[DEBUG] PCI: 00:00:1f.6 10 * [0xcece0000 - 0xcecfffff] limit: cecfffff mem
[DEBUG] PCI: 00:00:14.0 10 * [0xcecd0000 - 0xcecdffff] limit: cecdffff mem
[DEBUG] PCI: 00:00:1f.3 20 * [0xcecc0000 - 0xceccffff] limit: ceccffff mem
[DEBUG] PCI: 00:00:04.0 10 * [0xcecb8000 - 0xcecbffff] limit: cecbffff mem
[DEBUG] PCI: 00:00:1f.2 10 * [0xcecb4000 - 0xcecb7fff] limit: cecb7fff mem
[DEBUG] PCI: 00:00:1f.3 10 * [0xcecb0000 - 0xcecb3fff] limit: cecb3fff mem
[DEBUG] PCI: 00:00:14.2 10 * [0xcecaf000 - 0xcecaffff] limit: cecaffff mem
[DEBUG] PCI: 00:00:19.0 18 * [0xcecae000 - 0xcecaefff] limit: cecaefff mem
[DEBUG] PCI: 00:00:1f.4 10 * [0xcecad000 - 0xcecad0ff] limit: cecad0ff mem
[DEBUG] DOMAIN: 00000000 mem: base: 70000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[DEBUG] PCI: 00:01:00.0 14 * [0xcef00000 - 0xcef00fff] limit: cef00fff mem
[DEBUG] PCI: 00:02:00.0 10 * [0xcee00000 - 0xcee01fff] limit: cee01fff mem
[DEBUG] PCI: 00:04:00.0 10 * [0xced00000 - 0xced03fff] limit: ced03fff mem
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
[SPEW ] Root Device assign_resources, segment group 0 bus 0
[SPEW ] DOMAIN: 00000000 assign_resources, segment group 0 bus 0
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000cf000000 - 0x00000000cfffffff] size 0x01000000 gran 0x18 mem64
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000d0000000 - 0x00000000dfffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io
[DEBUG] PCI: 00:00:04.0 10 <- [0x00000000cecb8000 - 0x00000000cecbffff] size 0x00008000 gran 0x0f mem64
[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000cecd0000 - 0x00000000cecdffff] size 0x00010000 gran 0x10 mem64
[SPEW ] PCI: 00:00:14.0 assign_resources, segment group 0 bus 0
[SPEW ] PCI: 00:00:14.0 assign_resources, segment group 0 bus 0 done
[DEBUG] PCI: 00:00:14.2 10 <- [0x00000000cecaf000 - 0x00000000cecaffff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:19.0 18 <- [0x00000000cecae000 - 0x00000000cecaefff] size 0x00001000 gran 0x0c mem64
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000cef00000 - 0x00000000ceffffff] size 0x00100000 gran 0x14 seg 00 bus 01 mem
[SPEW ] PCI: 00:00:1c.0 assign_resources, segment group 0 bus 1
[DEBUG] PCI: 00:01:00.0 14 <- [0x00000000cef00000 - 0x00000000cef00fff] size 0x00001000 gran 0x0c mem
[SPEW ] PCI: 00:00:1c.0 assign_resources, segment group 0 bus 1 done
[DEBUG] PCI: 00:00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
[DEBUG] PCI: 00:00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
[DEBUG] PCI: 00:00:1c.2 20 <- [0x00000000cee00000 - 0x00000000ceefffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem
[SPEW ] PCI: 00:00:1c.2 assign_resources, segment group 0 bus 2
[DEBUG] PCI: 00:02:00.0 10 <- [0x00000000cee00000 - 0x00000000cee01fff] size 0x00002000 gran 0x0d mem64
[SPEW ] PCI: 00:00:1c.2 assign_resources, segment group 0 bus 2 done
[DEBUG] PCI: 00:00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io
[DEBUG] PCI: 00:00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
[DEBUG] PCI: 00:00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem
[DEBUG] PCI: 00:00:1d.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 04 io
[DEBUG] PCI: 00:00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
[DEBUG] PCI: 00:00:1d.0 20 <- [0x00000000ced00000 - 0x00000000cedfffff] size 0x00100000 gran 0x14 seg 00 bus 04 mem
[SPEW ] PCI: 00:00:1d.0 assign_resources, segment group 0 bus 4
[DEBUG] PCI: 00:04:00.0 10 <- [0x00000000ced00000 - 0x00000000ced03fff] size 0x00004000 gran 0x0e mem64
[SPEW ] PCI: 00:00:1d.0 assign_resources, segment group 0 bus 4 done
[SPEW ] PCI: 00:00:1f.0 assign_resources, segment group 0 bus 0
[SPEW ] PCI: 00:00:1f.0 assign_resources, segment group 0 bus 0 done
[DEBUG] PCI: 00:00:1f.2 10 <- [0x00000000cecb4000 - 0x00000000cecb7fff] size 0x00004000 gran 0x0e mem
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000cecb0000 - 0x00000000cecb3fff] size 0x00004000 gran 0x0e mem64
[DEBUG] PCI: 00:00:1f.3 20 <- [0x00000000cecc0000 - 0x00000000ceccffff] size 0x00010000 gran 0x10 mem64
[DEBUG] PCI: 00:00:1f.4 10 <- [0x00000000cecad000 - 0x00000000cecad0ff] size 0x00000100 gran 0x08 mem64
[DEBUG] PCI: 00:00:1f.6 10 <- [0x00000000cece0000 - 0x00000000cecfffff] size 0x00020000 gran 0x11 mem
[SPEW ] DOMAIN: 00000000 assign_resources, segment group 0 bus 0 done
[SPEW ] Root Device assign_resources, segment group 0 bus 0 done
[INFO ] Done setting resources.
[SPEW ] Show resources in subtree (Root Device)...After assigning values.
[DEBUG] Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG] CPU_CLUSTER: 0 child on link 0 APIC: 00
[DEBUG] APIC: 00
[DEBUG] APIC: 01
[DEBUG] APIC: 02
[DEBUG] APIC: 03
[DEBUG] DOMAIN: 00000000 child on link 0 GPIO: 0
[SPEW ] DOMAIN: 00000000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ] DOMAIN: 00000000 resource base 70000000 size 0 align 0 gran 0 limit dfffffff flags 40040200 index 10000100
[SPEW ] DOMAIN: 00000000 resource base 100000000 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000200
[DEBUG] GPIO: 0
[DEBUG] PCI: 00:00:00.0
[SPEW ] PCI: 00:00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
[SPEW ] PCI: 00:00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
[SPEW ] PCI: 00:00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
[SPEW ] PCI: 00:00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
[SPEW ] PCI: 00:00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
[SPEW ] PCI: 00:00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
[SPEW ] PCI: 00:00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ] PCI: 00:00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
[SPEW ] PCI: 00:00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 8
[SPEW ] PCI: 00:00:00.0 resource base c0000 size 6ff40000 align 0 gran 0 limit 0 flags e0004200 index 9
[SPEW ] PCI: 00:00:00.0 resource base 70000000 size d000000 align 0 gran 0 limit 0 flags f0000200 index a
[SPEW ] PCI: 00:00:00.0 resource base 100000000 size 183000000 align 0 gran 0 limit 0 flags e0004200 index b
[SPEW ] PCI: 00:00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
[SPEW ] PCI: 00:00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
[DEBUG] PCI: 00:00:01.0
[DEBUG] PCI: 00:00:01.1
[DEBUG] PCI: 00:00:01.2
[DEBUG] PCI: 00:00:02.0
[SPEW ] PCI: 00:00:02.0 resource base cf000000 size 1000000 align 24 gran 24 limit cfffffff flags 60000201 index 10
[SPEW ] PCI: 00:00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
[SPEW ] PCI: 00:00:02.0 resource base ffc0 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
[DEBUG] PCI: 00:00:04.0
[SPEW ] PCI: 00:00:04.0 resource base cecb8000 size 8000 align 15 gran 15 limit cecbffff flags 60000201 index 10
[DEBUG] PCI: 00:00:05.0
[DEBUG] PCI: 00:00:07.0
[DEBUG] PCI: 00:00:08.0
[DEBUG] PCI: 00:00:13.0
[DEBUG] PCI: 00:00:14.0 child on link 0 USB0 port 0
[SPEW ] PCI: 00:00:14.0 resource base cecd0000 size 10000 align 16 gran 16 limit cecdffff flags 60000201 index 10
[DEBUG] USB0 port 0 child on link 0 USB2 port 0
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] USB2 port 2
[DEBUG] USB2 port 3
[DEBUG] USB2 port 4
[DEBUG] USB2 port 5
[DEBUG] USB2 port 6
[DEBUG] USB2 port 7
[DEBUG] USB2 port 8
[DEBUG] USB2 port 9
[DEBUG] USB3 port 0
[DEBUG] USB3 port 1
[DEBUG] USB3 port 2
[DEBUG] USB3 port 3
[DEBUG] USB3 port 4
[DEBUG] USB3 port 5
[DEBUG] PCI: 00:00:14.1
[DEBUG] PCI: 00:00:14.2
[SPEW ] PCI: 00:00:14.2 resource base cecaf000 size 1000 align 12 gran 12 limit cecaffff flags 60000201 index 10
[DEBUG] PCI: 00:00:14.3
[DEBUG] PCI: 00:00:15.0
[DEBUG] PCI: 00:00:15.1
[DEBUG] PCI: 00:00:15.2
[DEBUG] PCI: 00:00:15.3
[DEBUG] PCI: 00:00:16.0
[DEBUG] PCI: 00:00:16.1
[DEBUG] PCI: 00:00:16.2
[DEBUG] PCI: 00:00:16.3
[DEBUG] PCI: 00:00:16.4
[DEBUG] PCI: 00:00:17.0
[DEBUG] PCI: 00:00:19.0
[SPEW ] PCI: 00:00:19.0 resource base fe030000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
[SPEW ] PCI: 00:00:19.0 resource base cecae000 size 1000 align 12 gran 12 limit cecaefff flags 60000201 index 18
[DEBUG] PCI: 00:00:19.1
[DEBUG] PCI: 00:00:19.2
[DEBUG] PCI: 00:00:1b.0
[DEBUG] PCI: 00:00:1b.1
[DEBUG] PCI: 00:00:1b.2
[DEBUG] PCI: 00:00:1b.3
[DEBUG] PCI: 00:00:1b.4
[DEBUG] PCI: 00:00:1b.5
[DEBUG] PCI: 00:00:1b.6
[DEBUG] PCI: 00:00:1b.7
[DEBUG] PCI: 00:00:1c.0 child on link 0 PCI: 00:01:00.0
[SPEW ] PCI: 00:00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ] PCI: 00:00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:00:1c.0 resource base cef00000 size 100000 align 20 gran 20 limit ceffffff flags 60080202 index 20
[DEBUG] PCI: 00:01:00.0
[SPEW ] PCI: 00:01:00.0 resource base cef00000 size 1000 align 12 gran 12 limit cef00fff flags 60000200 index 14
[DEBUG] PCI: 00:00:1c.2 child on link 0 PCI: 00:02:00.0
[SPEW ] PCI: 00:00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ] PCI: 00:00:1c.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:00:1c.2 resource base cee00000 size 100000 align 20 gran 20 limit ceefffff flags 60080202 index 20
[DEBUG] PCI: 00:02:00.0
[SPEW ] PCI: 00:02:00.0 resource base cee00000 size 2000 align 13 gran 13 limit cee01fff flags 60000201 index 10
[DEBUG] PCI: 00:00:1c.4
[SPEW ] PCI: 00:00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ] PCI: 00:00:1c.4 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:00:1c.4 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG] PCI: 00:00:1d.0 child on link 0 PCI: 00:04:00.0
[SPEW ] PCI: 00:00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ] PCI: 00:00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:00:1d.0 resource base ced00000 size 100000 align 20 gran 20 limit cedfffff flags 60080202 index 20
[DEBUG] PCI: 00:04:00.0
[SPEW ] PCI: 00:04:00.0 resource base ced00000 size 4000 align 14 gran 14 limit ced03fff flags 60000201 index 10
[DEBUG] PCI: 00:00:1d.4
[DEBUG] PCI: 00:00:1d.5
[DEBUG] PCI: 00:00:1d.6
[DEBUG] PCI: 00:00:1d.7
[DEBUG] PCI: 00:00:1e.0
[DEBUG] PCI: 00:00:1e.1
[DEBUG] PCI: 00:00:1e.2
[DEBUG] PCI: 00:00:1e.3
[DEBUG] PCI: 00:00:1e.4
[DEBUG] PCI: 00:00:1e.5
[DEBUG] PCI: 00:00:1e.6
[DEBUG] PCI: 00:00:1f.0 child on link 0 PNP: 00ff.0
[SPEW ] PCI: 00:00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
[SPEW ] PCI: 00:00:1f.0 resource base 680 size 80 align 0 gran 0 limit 0 flags c0000100 index 84
[SPEW ] PCI: 00:00:1f.0 resource base 7e0 size 20 align 0 gran 0 limit 0 flags c0000100 index 88
[SPEW ] PCI: 00:00:1f.0 resource base 900 size 80 align 0 gran 0 limit 0 flags c0000100 index 8c
[SPEW ] PCI: 00:00:1f.0 resource base 80 size 10 align 0 gran 0 limit 0 flags c0000100 index 90
[DEBUG] PNP: 00ff.0
[DEBUG] PCI: 00:00:1f.1
[SPEW ] PCI: 00:00:1f.1 resource base fd000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10
[DEBUG] PCI: 00:00:1f.2
[SPEW ] PCI: 00:00:1f.2 resource base cecb4000 size 4000 align 14 gran 14 limit cecb7fff flags 60000200 index 10
[SPEW ] PCI: 00:00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags d0000200 index 48
[SPEW ] PCI: 00:00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 40
[DEBUG] PCI: 00:00:1f.3
[SPEW ] PCI: 00:00:1f.3 resource base cecb0000 size 4000 align 14 gran 14 limit cecb3fff flags 60000201 index 10
[SPEW ] PCI: 00:00:1f.3 resource base cecc0000 size 10000 align 16 gran 16 limit ceccffff flags 60000201 index 20
[DEBUG] PCI: 00:00:1f.4
[SPEW ] PCI: 00:00:1f.4 resource base cecad000 size 100 align 12 gran 8 limit cecad0ff flags 60000201 index 10
[SPEW ] PCI: 00:00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
[DEBUG] PCI: 00:00:1f.5
[DEBUG] PCI: 00:00:1f.6
[SPEW ] PCI: 00:00:1f.6 resource base cece0000 size 20000 align 17 gran 17 limit cecfffff flags 60000200 index 10
[DEBUG] PCI: 00:00:1f.7
[INFO ] Done allocating resources.
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 3400 ms
[INFO ] LAPIC 0x0 in XAPIC mode.
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000006fffffff size 0x6ff40000 type 6
[DEBUG] 0x0000000070000000 - 0x00000000cfffffff size 0x60000000 type 0
[DEBUG] 0x00000000d0000000 - 0x00000000dfffffff size 0x10000000 type 1
[DEBUG] 0x00000000e0000000 - 0x00000000ffffffff size 0x20000000 type 0
[DEBUG] 0x0000000100000000 - 0x0000000282ffffff size 0x183000000 type 6
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[SPEW ] apic_id 0x0 call enable_fixed_mtrr()
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 5/5.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x0000000070000000 mask 0x0000007ff0000000 type 0
[DEBUG] MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
[DEBUG] MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[DEBUG] MTRR: 4 base 0x0000000200000000 mask 0x0000007f00000000 type 6
[INFO ] LAPIC 0x1 in XAPIC mode.
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] LAPIC 0x2 in XAPIC mode.
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[SPEW ] apic_id 0x1 call enable_fixed_mtrr()
[SPEW ] apic_id 0x2 call enable_fixed_mtrr()
[DEBUG] apic_id 0x1 setup mtrr for CPU physical address size: 39 bits
[DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26f 0x0606060606060606
[SPEW ] apic_id 0x3 call enable_fixed_mtrr()
[DEBUG] apic_id 0x3 setup mtrr for CPU physical address size: 39 bits
[DEBUG] MTRR: TEMPORARY Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000006fffffff size 0x6ff40000 type 6
[DEBUG] 0x0000000070000000 - 0x00000000feffffff size 0x8f000000 type 0
[DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG] 0x0000000100000000 - 0x0000000282ffffff size 0x183000000 type 6
[DEBUG] MTRR: default type WB/UC MTRR counts: 9/5.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG] MTRR: 1 base 0x0000000070000000 mask 0x0000007ff0000000 type 0
[DEBUG] MTRR: 2 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
[DEBUG] MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[DEBUG] MTRR: 4 base 0x0000000200000000 mask 0x0000007f00000000 type 6

[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled

[DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 196 / 320 ms
[INFO ] Enabling resources...
[DEBUG] PCI: 00:00:00.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:00.0 cmd <- 06
[DEBUG] PCI: 00:00:02.0 subsystem <- 8086/5916
[DEBUG] PCI: 00:00:02.0 cmd <- 03
[DEBUG] PCI: 00:00:04.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:04.0 cmd <- 02
[DEBUG] PCI: 00:00:14.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:14.0 cmd <- 02
[DEBUG] PCI: 00:00:14.2 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:14.2 cmd <- 02
[DEBUG] PCI: 00:00:19.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:19.0 cmd <- 06
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:00:1c.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1c.0 cmd <- 06
[DEBUG] PCI: 00:00:1c.2 bridge ctrl <- 0013
[DEBUG] PCI: 00:00:1c.2 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1c.2 cmd <- 06
[DEBUG] PCI: 00:00:1c.4 bridge ctrl <- 0013
[DEBUG] PCI: 00:00:1c.4 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1c.4 cmd <- 00
[DEBUG] PCI: 00:00:1d.0 bridge ctrl <- 0013
[DEBUG] PCI: 00:00:1d.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1d.0 cmd <- 06
[DEBUG] PCI: 00:00:1f.0 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1f.0 cmd <- 407
[DEBUG] PCI: 00:00:1f.2 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1f.2 cmd <- 02
[DEBUG] PCI: 00:00:1f.3 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1f.3 cmd <- 02
[DEBUG] PCI: 00:00:1f.4 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1f.4 cmd <- 03
[DEBUG] PCI: 00:00:1f.6 subsystem <- 1028/07a0
[DEBUG] PCI: 00:00:1f.6 cmd <- 02
[DEBUG] PCI: 00:01:00.0 cmd <- 02
[DEBUG] PCI: 00:02:00.0 cmd <- 02
[DEBUG] PCI: 00:04:00.0 cmd <- 02
[INFO ] done.
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 188 ms
[WARN ] HECI: CSE device 16.0 is disabled
[DEBUG] ME: Version: Unavailable
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 0 / 9 ms
[INFO ] Initializing devices...
[DEBUG] PCI: 00:00:00.0 init
[INFO ] CPU TDP = 15 Watts
[INFO ] CPU PL1 = 20 Watts
[INFO ] CPU PL2 = 30 Watts
[DEBUG] PCI: 00:00:00.0 init finished in 11 msecs
[DEBUG] PCI: 00:00:02.0 init
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'vbt.bin' @0x97280 size 0x499 in mcache @0x6fbdd1e4
[INFO ] Found a VBT of 6144 bytes
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[DEBUG] Starting cbfs_boot_device
[WARN ] CBFS: 'pci8086,0406.rom' not found.
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'pci8086,5916.rom' @0x11f040 size 0x10000 in mcache @0x6fbdd30c
[NOTE ] VGA_BIOS_ID should be the remapped PCI ID 8086,0406 in the VBIOS file
[DEBUG] In CBFS, ROM address for PCI: 00:00:02.0 = 0xff88006c
[SPEW ] PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
[SPEW ] PCI ROM image, vendor ID 8086, device ID 0406,
[SPEW ] PCI ROM image, Class Code 030000, Code Type 00
[DEBUG] Copying VGA ROM Image from 0xff88006c to 0xc0000, 0x10000 bytes
[SPEW ] Real mode stub @0x00000600: 889 bytes
[DEBUG] Calling Option ROM...
[DEBUG] ... Option ROM returned.
[DEBUG] VGA Option ROM was run
[DEBUG] PCI: 00:00:02.0 init finished in 140 msecs
[DEBUG] PCI: 00:00:04.0 init
[DEBUG] PCI: 00:00:04.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.0 init
[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
[DEBUG] PCI: 00:00:14.2 init
[DEBUG] PCI: 00:00:14.2 init finished in 0 msecs
[DEBUG] PCI: 00:00:1c.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
[DEBUG] PCI: 00:00:1c.2 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.2 init finished in 4 msecs
[DEBUG] PCI: 00:00:1c.4 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1c.4 init finished in 4 msecs
[DEBUG] PCI: 00:00:1d.0 init
[DEBUG] Initializing PCH PCIe bridge.
[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs
[DEBUG] PCI: 00:00:1f.0 init
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
[DEBUG] IOAPIC: ID = 0x00
[SPEW ] IOAPIC: Dumping registers
[SPEW ] reg 0x0000: 0x00000000
[SPEW ] reg 0x0001: 0x00770020
[SPEW ] reg 0x0002: 0x00000000
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
[SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x18 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x19 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x20 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x21 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x22 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x23 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x24 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x25 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x26 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x27 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x28 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x29 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x2f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x30 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x31 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x32 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x33 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x34 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x35 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x36 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x37 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x38 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x39 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x3f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x40 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x41 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x42 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x43 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x44 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x45 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x46 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x47 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x48 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x49 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x4f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x50 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x51 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x52 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x53 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x54 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x55 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x56 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x57 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x58 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x59 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x5f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x60 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x61 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x62 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x63 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x64 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x65 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x66 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x67 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x68 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x69 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x6f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x70 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x71 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x72 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x73 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x74 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x75 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x76 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x77 value 0x00000000 0x00010000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700
[DEBUG] PCI: 00:00:1f.0 init finished in 819 msecs
[DEBUG] PCI: 00:00:1f.2 init
[DEBUG] RTC Init
[INFO ] Set power on after power failure.
[DEBUG] apm_control: Disabling ACPI.
[DEBUG] APMC done.
[DEBUG] Disabling Deep S3
[DEBUG] Disabling Deep S3
[DEBUG] Disabling Deep S4
[DEBUG] Disabling Deep S4
[DEBUG] Disabling Deep S5
[DEBUG] Disabling Deep S5
[DEBUG] PCI: 00:00:1f.2 init finished in 36 msecs
[DEBUG] PCI: 00:00:1f.3 init
[DEBUG] azalia_audio: base = 0xcecb0000
[DEBUG] azalia_audio: codec_mask = 0x05
[DEBUG] azalia_audio: initializing codec #2...
[DEBUG] azalia_audio: - vendor/device id: 0x8086280b
[DEBUG] azalia_audio: - verb size: 16
[DEBUG] azalia_audio: - verb loaded
[DEBUG] azalia_audio: initializing codec #0...
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0256
[DEBUG] azalia_audio: - verb size: 44
[DEBUG] azalia_audio: - verb loaded
[DEBUG] PCI: 00:00:1f.3 init finished in 58 msecs
[DEBUG] PCI: 00:00:1f.4 init
[DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs
[DEBUG] PCI: 00:00:1f.6 init
[DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs
[DEBUG] PCI: 00:01:00.0 init
[DEBUG] PCI: 00:01:00.0 init finished in 0 msecs
[DEBUG] PCI: 00:02:00.0 init
[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs
[DEBUG] PCI: 00:04:00.0 init
[DEBUG] PCI: 00:04:00.0 init finished in 0 msecs
[DEBUG] PNP: 00ff.0 init
[DEBUG] Keyboard init...
[ERROR] Keyboard Interface test failed: 0x8
[DEBUG] PS/2 keyboard initialized on primary channel
[DEBUG] PNP: 00ff.0 init finished in 48 msecs
[INFO ] Devices initialized
[SPEW ] Show all devs... After init.
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] DOMAIN: 00000000: enabled 1
[SPEW ] GPIO: 0: enabled 1
[SPEW ] PCI: 00:00:00.0: enabled 1
[SPEW ] PCI: 00:00:01.0: enabled 0
[SPEW ] PCI: 00:00:01.1: enabled 0
[SPEW ] PCI: 00:00:01.2: enabled 0
[SPEW ] PCI: 00:00:02.0: enabled 1
[SPEW ] PCI: 00:00:04.0: enabled 1
[SPEW ] PCI: 00:00:05.0: enabled 0
[SPEW ] PCI: 00:00:07.0: enabled 0
[SPEW ] PCI: 00:00:08.0: enabled 0
[SPEW ] PCI: 00:00:13.0: enabled 0
[SPEW ] PCI: 00:00:14.0: enabled 1
[SPEW ] PCI: 00:00:14.1: enabled 0
[SPEW ] PCI: 00:00:14.2: enabled 1
[SPEW ] PCI: 00:00:14.3: enabled 0
[SPEW ] PCI: 00:00:15.0: enabled 0
[SPEW ] PCI: 00:00:15.1: enabled 0
[SPEW ] PCI: 00:00:15.2: enabled 0
[SPEW ] PCI: 00:00:15.3: enabled 0
[SPEW ] PCI: 00:00:16.0: enabled 0
[SPEW ] PCI: 00:00:16.1: enabled 0
[SPEW ] PCI: 00:00:16.2: enabled 0
[SPEW ] PCI: 00:00:16.3: enabled 0
[SPEW ] PCI: 00:00:16.4: enabled 0
[SPEW ] PCI: 00:00:17.0: enabled 0
[SPEW ] PCI: 00:00:19.0: enabled 1
[SPEW ] PCI: 00:00:19.1: enabled 0
[SPEW ] PCI: 00:00:19.2: enabled 0
[SPEW ] PCI: 00:00:1b.0: enabled 0
[SPEW ] PCI: 00:00:1b.1: enabled 0
[SPEW ] PCI: 00:00:1b.2: enabled 0
[SPEW ] PCI: 00:00:1b.3: enabled 0
[SPEW ] PCI: 00:00:1b.4: enabled 0
[SPEW ] PCI: 00:00:1b.5: enabled 0
[SPEW ] PCI: 00:00:1b.6: enabled 0
[SPEW ] PCI: 00:00:1b.7: enabled 0
[SPEW ] PCI: 00:00:1c.0: enabled 1
[SPEW ] PCI: 00:00:1c.1: enabled 0
[SPEW ] PCI: 00:00:1c.2: enabled 1
[SPEW ] PCI: 00:00:1c.3: enabled 0
[SPEW ] PCI: 00:00:1c.4: enabled 1
[SPEW ] PCI: 00:00:1c.5: enabled 0
[SPEW ] PCI: 00:00:1c.6: enabled 0
[SPEW ] PCI: 00:00:1c.7: enabled 0
[SPEW ] PCI: 00:00:1d.0: enabled 1
[SPEW ] PCI: 00:00:1d.1: enabled 0
[SPEW ] PCI: 00:00:1d.2: enabled 0
[SPEW ] PCI: 00:00:1d.3: enabled 0
[SPEW ] PCI: 00:00:1d.4: enabled 0
[SPEW ] PCI: 00:00:1d.5: enabled 0
[SPEW ] PCI: 00:00:1d.6: enabled 0
[SPEW ] PCI: 00:00:1d.7: enabled 0
[SPEW ] PCI: 00:00:1e.0: enabled 0
[SPEW ] PCI: 00:00:1e.1: enabled 0
[SPEW ] PCI: 00:00:1e.2: enabled 0
[SPEW ] PCI: 00:00:1e.3: enabled 0
[SPEW ] PCI: 00:00:1e.4: enabled 0
[SPEW ] PCI: 00:00:1e.5: enabled 0
[SPEW ] PCI: 00:00:1e.6: enabled 0
[SPEW ] PCI: 00:00:1f.0: enabled 1
[SPEW ] PCI: 00:00:1f.1: enabled 1
[SPEW ] PCI: 00:00:1f.2: enabled 1
[SPEW ] PCI: 00:00:1f.3: enabled 1
[SPEW ] PCI: 00:00:1f.4: enabled 1
[SPEW ] PCI: 00:00:1f.5: enabled 0
[SPEW ] PCI: 00:00:1f.6: enabled 1
[SPEW ] PCI: 00:00:1f.7: enabled 0
[SPEW ] USB0 port 0: enabled 0
[SPEW ] PNP: 00ff.0: enabled 1
[SPEW ] USB2 port 0: enabled 0
[SPEW ] USB2 port 1: enabled 0
[SPEW ] USB2 port 2: enabled 0
[SPEW ] USB2 port 3: enabled 0
[SPEW ] USB2 port 4: enabled 0
[SPEW ] USB2 port 5: enabled 0
[SPEW ] USB2 port 6: enabled 0
[SPEW ] USB2 port 7: enabled 0
[SPEW ] USB2 port 8: enabled 0
[SPEW ] USB2 port 9: enabled 0
[SPEW ] USB3 port 0: enabled 0
[SPEW ] USB3 port 1: enabled 0
[SPEW ] USB3 port 2: enabled 0
[SPEW ] USB3 port 3: enabled 0
[SPEW ] USB3 port 4: enabled 0
[SPEW ] USB3 port 5: enabled 0
[SPEW ] APIC: 00: enabled 1
[SPEW ] APIC: 01: enabled 1
[SPEW ] APIC: 02: enabled 1
[SPEW ] APIC: 03: enabled 1
[SPEW ] PCI: 00:01:00.0: enabled 1
[SPEW ] PCI: 00:02:00.0: enabled 1
[SPEW ] PCI: 00:04:00.0: enabled 1
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 72 / 1651 ms
[INFO ] Finalize devices...
[DEBUG] PCI: 00:00:02.0 final
[DEBUG] PCI: 00:00:1f.2 final
[DEBUG] PCI: 00:00:1f.3 final
[DEBUG] PCI: 00:00:1f.4 final
[INFO ] Devices finalized
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 23 ms
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x94500 size 0x2d50 in mcache @0x6fbdd1b8
[DEBUG] Starting cbfs_boot_device
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 6fa14000.
[DEBUG] ACPI: * FACS
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * FACP
[DEBUG] ACPI: added table 1/32, length now 44
[DEBUG] Found 1 CPU(s) with 2/4 physical/logical core(s) each.
[DEBUG] PSS: 2801MHz power 15000 control 0x2700 status 0x2700
[DEBUG] PSS: 2800MHz power 15000 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 12263 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 9756 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 7434 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 5302 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 3355 control 0x800 status 0x800
[DEBUG] PSS: 400MHz power 1586 control 0x400 status 0x400
[DEBUG] PSS: 2801MHz power 15000 control 0x2700 status 0x2700
[DEBUG] PSS: 2800MHz power 15000 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 12263 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 9756 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 7434 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 5302 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 3355 control 0x800 status 0x800
[DEBUG] PSS: 400MHz power 1586 control 0x400 status 0x400
[DEBUG] PSS: 2801MHz power 15000 control 0x2700 status 0x2700
[DEBUG] PSS: 2800MHz power 15000 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 12263 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 9756 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 7434 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 5302 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 3355 control 0x800 status 0x800
[DEBUG] PSS: 400MHz power 1586 control 0x400 status 0x400
[DEBUG] PSS: 2801MHz power 15000 control 0x2700 status 0x2700
[DEBUG] PSS: 2800MHz power 15000 control 0x1c00 status 0x1c00
[DEBUG] PSS: 2400MHz power 12263 control 0x1800 status 0x1800
[DEBUG] PSS: 2000MHz power 9756 control 0x1400 status 0x1400
[DEBUG] PSS: 1600MHz power 7434 control 0x1000 status 0x1000
[DEBUG] PSS: 1200MHz power 5302 control 0xc00 status 0xc00
[DEBUG] PSS: 800MHz power 3355 control 0x800 status 0x800
[DEBUG] PSS: 400MHz power 1586 control 0x400 status 0x400
[DEBUG] SGX: EPC status = 0 base = 0x0 len = 0x0
[DEBUG] PCI space above 4GB MMIO is at 0x283000000, len = 0x7d7d000000
[DEBUG] Empty min sleep state array returned
[INFO ] Returning default LPI constraint package
[INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ] \_SB.PCI0.RP03.WF00: PCI: 00:02:00.0
[DEBUG] ACPI: * SSDT
[DEBUG] ACPI: added table 2/32, length now 52
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 60
[DEBUG] ACPI: * LPIT
[DEBUG] ACPI: added table 4/32, length now 68
[DEBUG] IOAPIC: 120 interrupts
[DEBUG] SCI is IRQ 9, GSI 9
[DEBUG] ACPI: * APIC
[DEBUG] ACPI: added table 5/32, length now 76
[DEBUG] ACPI: * SPCR
[DEBUG] ACPI: added table 6/32, length now 84
[DEBUG] current = 6fa18230
[DEBUG] ACPI: * DMAR
[DEBUG] ACPI: added table 7/32, length now 92
[DEBUG] ACPI: added table 8/32, length now 100
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 9/32, length now 108
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 17264 bytes.
[DEBUG] smbios_write_tables: 6fa0c000
[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12-408-gf0678e3639e2-dirty'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[INFO ] PCI: 00:02:00.0 (unknown)
[DEBUG] SMBIOS tables: 933 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 103b
[DEBUG] Writing coreboot table at 0x6fa38000
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
[DEBUG] 5. 0000000000100000-000000006fa0bfff: RAM
[DEBUG] 6. 000000006fa0c000-000000006fa82fff: CONFIGURATION TABLES
[DEBUG] 7. 000000006fa83000-000000006fbcbfff: RAMSTAGE
[DEBUG] 8. 000000006fbcc000-000000006fffffff: CONFIGURATION TABLES
[DEBUG] 9. 0000000070000000-000000007cffffff: RESERVED
[DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
[DEBUG] 11. 00000000fd000000-00000000fe00ffff: RESERVED
[DEBUG] 12. 00000000fed10000-00000000fed19fff: RESERVED
[DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED
[DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG] 15. 0000000100000000-0000000282ffffff: RAM
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG] Starting cbfs_boot_device
[DEBUG] Wrote coreboot table at: 0x6fa38000, 0x4a4 bytes, checksum 1065
[DEBUG] coreboot table: 1212 bytes.
[DEBUG] IMD ROOT 0. 0x6ffff000 0x00001000
[DEBUG] IMD SMALL 1. 0x6fffe000 0x00001000
[DEBUG] FSP MEMORY 2. 0x6fbfe000 0x00400000
[DEBUG] CONSOLE 3. 0x6fbde000 0x00020000
[DEBUG] RO MCACHE 4. 0x6fbdd000 0x00000464
[DEBUG] TIME STAMP 5. 0x6fbdc000 0x00000910
[DEBUG] MEM INFO 6. 0x6fbda000 0x000010c8
[DEBUG] AFTER CAR 7. 0x6fbcc000 0x0000e000
[DEBUG] RAMSTAGE 8. 0x6fa82000 0x0014a000
[DEBUG] REFCODE 9. 0x6fa54000 0x0002e000
[DEBUG] SMM BACKUP 10. 0x6fa44000 0x00010000
[DEBUG] IGD OPREGION11. 0x6fa40000 0x00003200
[DEBUG] COREBOOT 12. 0x6fa38000 0x00008000
[DEBUG] ACPI 13. 0x6fa14000 0x00024000
[DEBUG] SMBIOS 14. 0x6fa0c000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x6fffec00 0x00000400
[DEBUG] FSP RUNTIME 1. 0x6fffebe0 0x00000004
[DEBUG] FMAP 2. 0x6fffea40 0x00000188
[DEBUG] POWER STATE 3. 0x6fffea00 0x00000040
[DEBUG] FSPM VERSION 4. 0x6fffe9e0 0x00000004
[DEBUG] ROMSTAGE 5. 0x6fffe9c0 0x00000004
[DEBUG] ROMSTG STCK 6. 0x6fffe900 0x000000a8
[DEBUG] ACPI GNVS 7. 0x6fffe8c0 0x00000038
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 1 / 705 ms
[DEBUG] Starting cbfs_boot_device
[INFO ] CBFS: Found 'fallback/payload' @0x13fdc0 size 0x13075 in mcache @0x6fbdd3a4
[DEBUG] Checking segment from ROM address 0xff8a0dec
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
[DEBUG] Checking segment from ROM address 0xff8a0e08
[DEBUG] Loading segment from ROM address 0xff8a0dec
[DEBUG] code (compression=1)
[DEBUG] New segment dstaddr 0x000dae60 memsize 0x251a0 srcaddr 0xff8a0e24 filesize 0x1303d
[DEBUG] Loading Segment: addr: 0x000dae60 memsz: 0x00000000000251a0 filesz: 0x000000000001303d
[DEBUG] using LZMA
[SPEW ] [ 0x000dae60, 00100000, 0x00100000) <- ff8a0e24
[DEBUG] Loading segment from ROM address 0xff8a0e08
[DEBUG] Entry Point 0x000fcafc
[SPEW ] Loaded segments
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 7 / 88 ms
[DEBUG] Finalizing chipset.
[WARN ] HECI: CSE device 16.0 is disabled
[INFO ] Disabling Heci using PCR
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 21 ms
[DEBUG] mp_park_aps done after 0 msecs.
[DEBUG] Jumping to boot code at 0x000fcafc(0x6fa38000)
[SPEW ] CPU0: stack: 0x6fabb260 - 0x6fabd260, lowest used address 0x6fabcc90, stack used: 1488 bytes
SeaBIOS (version rel-1.17.0-0-gb52ca86e)
BUILD: gcc: (coreboot toolchain v2025-10-19_4a3cc37cbd) 14.2.0 binutils: (GNU Binutils) 2.45
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
SeaBIOS (version rel-1.17.0-0-gb52ca86e)
BUILD: gcc: (coreboot toolchain v2025-10-19_4a3cc37cbd) 14.2.0 binutils: (GNU Binutils) 2.45
Found coreboot cbmem console @ 6fbde000
Found mainboard Dell Inc. Latitude 7480
malloc preinit
Relocating init from 0x000dc860 to 0x6e9fe040 (size 57120)
malloc init
Found CBFS header at 0xff76102c
Add romfile: cbfs_master_header (size=32)
Add romfile: cpu_microcode_blob.bin (size=424960)
Add romfile: intel_fit (size=176)
Add romfile: fallback/romstage (size=63056)
Add romfile: fallback/ramstage (size=113381)
Add romfile: config (size=4322)
Add romfile: revision (size=781)
Add romfile: build_info (size=113)
Add romfile: fallback/dsdt.aml (size=11600)
Add romfile: vbt.bin (size=1177)
Add romfile: payload_config (size=1671)
Add romfile: payload_revision (size=237)
Add romfile: etc/ps2-keyboard-spinup (size=8)
Add romfile: fspm.bin (size=405504)
Add romfile: fsps.bin (size=147442)
Add romfile: pci8086,5916.rom (size=65536)
Add romfile: fallback/postcar (size=24648)
Add romfile: img/coreinfo (size=44085)
Add romfile: fallback/payload (size=77941)
Add romfile: img/memtest (size=137683)
Add romfile: pci8068,15d7.rom (size=96768)
Add romfile: (size=7392484)
Add romfile: bootblock (size=24576)
multiboot: eax=6faba9b8, ebx=6faba984
init ivt
init bda
init bios32
init PMM
init PNPBIOS table
init keyboard
init mouse
init pic
math cp init
PCI probe
PCI device 00:00.0 (vd=8086:5904 c=0600)
PCI device 00:02.0 (vd=8086:5916 c=0300)
PCI device 00:04.0 (vd=8086:1903 c=1180)
PCI device 00:14.0 (vd=8086:9d2f c=0c03)
PCI device 00:14.2 (vd=8086:9d31 c=1180)
PCI device 00:19.0 (vd=8086:9d66 c=1180)
PCI device 00:1c.0 (vd=8086:9d10 c=0604)
PCI device 00:1c.2 (vd=8086:9d12 c=0604)
PCI device 00:1c.4 (vd=8086:9d14 c=0604)
PCI device 00:1d.0 (vd=8086:9d18 c=0604)
PCI device 00:1f.0 (vd=8086:9d4e c=0601)
PCI device 00:1f.2 (vd=8086:9d21 c=0580)
PCI device 00:1f.3 (vd=8086:9d71 c=0403)
PCI device 00:1f.4 (vd=8086:9d23 c=0c05)
PCI device 00:1f.6 (vd=8086:15d7 c=0200)
PCI device 01:00.0 (vd=10ec:525a c=ff00)
PCI device 02:00.0 (vd=8086:24fd c=0280)
PCI device 04:00.0 (vd=1179:0115 c=0108)
Found 18 PCI devices (max PCI bus is 04)
Relocating coreboot bios tables
Copying SMBIOS from 0x6fa0c000 to 0x000f4fa0
Copying SMBIOS 3.0 from 0x6fa0c020 to 0x000f4f80
Copying ACPI RSDP from 0x6fa14000 to 0x000f4f50
rsdp=0x000f4f50
rsdt=0x6fa14030
xsdt=0x6fa140e0
table(50434146)=0x6fa16ff0 (via xsdt)
pm_tmr_blk=1808
Using pmtimer, ioport 0x1808
init timer
rsdp=0x000f4f50
rsdt=0x6fa14030
xsdt=0x6fa140e0
no table 324d5054 found
rsdp=0x000f4f50
rsdt=0x6fa14030
xsdt=0x6fa140e0
no table 41504354 found
Scan for VGA option rom
Attempting to init PCI bdf 00:02.0 (vd 8086:5916)
Copying data 65536@0xff88006c to 65536@0x000c0000
Checking rom 0x000c0000 (sig aa55 size 128)
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.17.0-0-gb52ca86e)
init usb
PCI: XHCI at 00:14.0 (mmio 0xcecd0000)
XHCI init: regs @ 0xcecd0000, 18 ports, 64 slots, 32 byte contexts
XHCI protocol USB 2.00, 12 ports (offset 1), def 3011
XHCI protocol USB 3.00, 6 ports (offset 13), def 3000
XHCI extcap 0xc0 @ 0xcecd8070
XHCI extcap 0x1 @ 0xcecd846c
XHCI extcap 0xc6 @ 0xcecd84f4
XHCI extcap 0xc7 @ 0xcecd8500
XHCI extcap 0xc2 @ 0xcecd8600
XHCI extcap 0xa @ 0xcecd8700
XHCI extcap 0xc3 @ 0xcecd8740
XHCI extcap 0xc4 @ 0xcecd8800
XHCI extcap 0xc5 @ 0xcecd8900
/6e9fb000\ Start thread
|6e9fb000| configure_xhci: resetting
init ps2port
/6e9fa000\ Start thread
|6e9fa000| i8042_flush
|6e9fa000| i8042_command cmd=ad
|6e9fa000| i8042_wait_write
|6e9fa000| i8042_command cmd=a7
|6e9fa000| i8042_wait_write
|6e9fa000| i8042_flush
|6e9fa000| i8042_command cmd=1aa
|6e9fa000| i8042_wait_write
|6e9fa000| i8042_wait_read
|6e9fa000| i8042 param=55
|6e9fa000| i8042_command cmd=1ab
|6e9fa000| i8042_wait_write
|6e9fa000| i8042_wait_read
|6e9fa000| WARNING - Timeout at i8042_wait_read:38!
|6e9fa000| i8042 command 1ab failed
\6e9fa000/ End thread
|6e9fb000| configure_xhci: setup 34 scratch pad buffers
init floppy drives
init hard drives
init ahci
Searching bootorder for: HALT
init megasas
init nvme
/6e9fa000\ Start thread
|6e9fa000| Found NVMe controller with version 1.1.0.
|6e9fa000| Capabilities 000000302803007f
|6e9fa000| q 0x6fa0bbce q_idx 1 dbl 0xced01004
|6e9fa000| q 0x6fa0bbbc q_idx 0 dbl 0xced01000
|6e9fa000| sq 0x6fa0bbbc q_idx 0 sqe 0x6f9e7000
|6e9fa000| admin submission queue: 0x6f9e7000
|6e9fa000| admin completion queue: 0x6f9e8000
/6e9f9000\ Start thread
init lpt
Found 0 lpt ports
init serial
Found 0 serial ports
Searching bootorder for: /rom@img/memtest
Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff8b3e80)
Searching bootorder for: /rom@img/coreinfo
Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff896140)
|6e9fa000| sq 0x6fa0bbbc next_sqe 0
|6e9fa000| sq 0x6fa0bbbc commit_sqe 0
/6e9f7000\ Start thread
|6e9fa000| cq 0x6fa0bbce head 0 -> 1
|6e9fa000| sq 0x6fa0bbbc advanced to 1
|6e9fa000| NVMe has 1 namespace.
|6e9fa000| q 0x6fa0bbf1 q_idx 3 dbl 0xced0100c
|6e9fa000| sq 0x6fa0bbbc next_sqe 1
|6e9fa000| sq 0x6fa0bbbc commit_sqe 1
/6e9f8000\ Start thread
|6e9fa000| cq 0x6fa0bbce head 1 -> 2
|6e9fa000| sq 0x6fa0bbbc advanced to 2
|6e9fa000| q 0x6fa0bbdf q_idx 2 dbl 0xced01008
|6e9fa000| sq 0x6fa0bbdf q_idx 2 sqe 0x6f9e5000
|6e9fa000| sq 0x6fa0bbbc next_sqe 2
|6e9fa000| sq 0x6fa0bbdf create dword10 007f0001 dword11 00010001
|6e9fa000| sq 0x6fa0bbbc commit_sqe 2
/6e9f6000\ Start thread
\6e9f6000/ End thread
\6e9f8000/ End thread
\6e9f7000/ End thread
\6e9f9000/ End thread
|6e9fa000| cq 0x6fa0bbce head 2 -> 3
|6e9fa000| sq 0x6fa0bbbc advanced to 3
|6e9fa000| sq 0x6fa0bbbc next_sqe 3
|6e9fa000| sq 0x6fa0bbbc commit_sqe 3
/6e9f8000\ Start thread
|6e9f8000| xhci_hub_reset port #5: 0x000206e1, powered, pls 7, speed 1 [Full]
|6e9fa000| cq 0x6fa0bbce head 3 -> 4
|6e9fa000| sq 0x6fa0bbbc advanced to 4
|6e9fa000| NVMe NS 1: 488386 MiB (1000215216 512-byte blocks + 0-byte metadata)
|6e9fa000| Searching bootorder for: /pci@i0cf8/pci-bridge@1d/*@0
|6e9fa000| Registering bootable: NVMe NS 1: 488386 MiB (1000215216 512-byte blocks + 0-byte metadata) (type:2 prio:103 data:f4f00)
|6e9fa000| NVMe initialization complete!
\6e9fa000/ End thread
/6e9fa000\ Start thread
\6e9fa000/ End thread
/6e9fa000\ Start thread
/6e9f9000\ Start thread
/6e9f6000\ Start thread
\6e9f6000/ End thread
/6e9f6000\ Start thread
|6e9f8000| XHCI port #5: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
|6e9f8000| set_address 0x6fa0bfb0
/6e9f5000\ Start thread
\6e9f5000/ End thread
/6e9f5000\ Start thread
\6e9f5000/ End thread
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f8000| xhci_alloc_pipe: usbdev 0x6e9fc440, ring 0x6f9e3e00, slotid 0, epid 1
|6e9f8000| xhci_cmd_enable_slot:
|6e9f8000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 1, len 0]
|6e9f8000| xhci_doorbell: slotid 0, epid 0
|6e9f8000| xhci_process_events port #5: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
|6e9f8000| xhci_process_events port #7: 0x000206e1, powered, pls 7, speed 1 [Full]
|6e9f8000| xhci_process_events port #8: 0x000206e1, powered, pls 7, speed 1 [Full]
|6e9f8000| xhci_process_events port #10: 0x000206e1, powered, pls 7, speed 1 [Full]
|6e9f8000| xhci_process_events port #5: 0x00000e03, powered, enabled, pls 0, speed 3 [High]
|6e9f8000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc00, evt 0x6fa0bd00, type 33, eidx 1, cc 1]
|6e9f8000| xhci_alloc_pipe: enable slot: got slotid 1
|6e9f8000| xhci_cmd_address_device: slotid 1
|6e9f8000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 2, len 0]
|6e9f8000| xhci_doorbell: slotid 0, epid 0
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f8000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc10, evt 0x6fa0bd00, type 33, eidx 2, cc 1]
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f8000| xhci_realloc_pipe: usbdev 0x6e9fc440, ring 0x6f9e3e00, slotid 1, epid 1
|6e9f8000| config_usb: 0x6f9e3f20
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 1, len 8]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 2, len 8]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 3, len 0]
|6e9f8000| xhci_doorbell: slotid 1, epid 1
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f6000| xhci_hub_reset port #10: 0x000006e1, powered, pls 7, speed 1 [Full]
|6e9f8000| xhci_process_events: ring 0x6f9e3e00 [trb 0x6f9e3e20, evt 0x6f9e3f00, type 32, eidx 3, cc 1]
|6e9f8000| device rev=0200 cls=ef sub=02 proto=01 size=64
|6e9f8000| xhci_realloc_pipe: usbdev 0x6e9fc440, ring 0x6f9e3e00, slotid 1, epid 1
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 4, len 8]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 5, len 9]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 6, len 0]
|6e9f8000| xhci_doorbell: slotid 1, epid 1
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f8000| xhci_process_events: ring 0x6f9e3e00 [trb 0x6f9e3e50, evt 0x6f9e3f00, type 32, eidx 6, cc 1]
|6e9f8000| xhci_process_events port #10: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 7, len 8]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 8, len 705]
|6e9f8000| xhci_trb_queue: ring 0x6f9e3e00 [nidx 9, len 0]
|6e9f8000| xhci_doorbell: slotid 1, epid 1
/6e9f5000\ Start thread
\6e9f5000/ End thread
|6e9f6000| XHCI port #10: 0x00000603, powered, enabled, pls 0, speed 1 [Full]
|6e9f6000| set_address 0x6fa0bfb0
|6e9f8000| xhci_process_events: ring 0x6f9e3e00 [trb 0x6f9e3e80, evt 0x6f9e3f00, type 32, eidx 9, cc 1]
\6e9f8000/ End thread
|6e9f6000| xhci_alloc_pipe: usbdev 0x6e9f7fe0, ring 0x6f9e3c00, slotid 0, epid 1
|6e9f6000| xhci_cmd_enable_slot:
|6e9f6000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 3, len 0]
|6e9f6000| xhci_doorbell: slotid 0, epid 0
|6e9f6000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc20, evt 0x6fa0bd00, type 33, eidx 3, cc 1]
|6e9f6000| xhci_alloc_pipe: enable slot: got slotid 2
|6e9f6000| xhci_cmd_address_device: slotid 2
|6e9f6000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 4, len 0]
|6e9f6000| xhci_doorbell: slotid 0, epid 0
|6e9f6000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc30, evt 0x6fa0bd00, type 33, eidx 4, cc 1]
|6e9f6000| xhci_realloc_pipe: usbdev 0x6e9f7fe0, ring 0x6f9e3c00, slotid 2, epid 1
|6e9f6000| config_usb: 0x6f9e3d20
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 1, len 8]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 2, len 8]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 3, len 0]
|6e9f6000| xhci_doorbell: slotid 2, epid 1
|6e9f9000| xhci_hub_reset port #8: 0x000006e1, powered, pls 7, speed 1 [Full]
|6e9f6000| xhci_process_events: ring 0x6f9e3c00 [trb 0x6f9e3c20, evt 0x6f9e3d00, type 32, eidx 3, cc 1]
|6e9f6000| device rev=0110 cls=00 sub=00 proto=00 size=64
|6e9f6000| xhci_realloc_pipe: usbdev 0x6e9f7fe0, ring 0x6f9e3c00, slotid 2, epid 1
|6e9f6000| xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
|6e9f6000| xhci_cmd_evaluate_context: slotid 2, add 0x2, del 0x0
|6e9f6000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 5, len 0]
|6e9f6000| xhci_doorbell: slotid 0, epid 0
|6e9f6000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc40, evt 0x6fa0bd00, type 33, eidx 5, cc 1]
|6e9f6000| xhci_process_events port #8: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 4, len 8]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 5, len 9]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 6, len 0]
|6e9f6000| xhci_doorbell: slotid 2, epid 1
|6e9f9000| XHCI port #8: 0x00000603, powered, enabled, pls 0, speed 1 [Full]
|6e9f9000| set_address 0x6fa0bfb0
|6e9f6000| xhci_process_events: ring 0x6f9e3c00 [trb 0x6f9e3c50, evt 0x6f9e3d00, type 32, eidx 6, cc 1]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 7, len 8]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 8, len 139]
|6e9f6000| xhci_trb_queue: ring 0x6f9e3c00 [nidx 9, len 0]
|6e9f6000| xhci_doorbell: slotid 2, epid 1
|6e9f9000| xhci_alloc_pipe: usbdev 0x6e9fc060, ring 0x6f9e3200, slotid 0, epid 1
|6e9f9000| xhci_cmd_enable_slot:
|6e9f9000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 6, len 0]
|6e9f9000| xhci_doorbell: slotid 0, epid 0
|6e9f9000| xhci_process_events: ring 0x6f9e3c00 [trb 0x6f9e3c80, evt 0x6f9e3d00, type 32, eidx 9, cc 1]
|6e9f9000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc50, evt 0x6fa0bd00, type 33, eidx 6, cc 1]
|6e9f9000| xhci_alloc_pipe: enable slot: got slotid 3
|6e9f9000| xhci_cmd_address_device: slotid 3
|6e9f9000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 7, len 0]
|6e9f9000| xhci_doorbell: slotid 0, epid 0
|6e9f6000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc60, evt 0x6fa0bd00, type 33, eidx 7, cc 1]
\6e9f6000/ End thread
|6e9f9000| xhci_realloc_pipe: usbdev 0x6e9fc060, ring 0x6f9e3200, slotid 3, epid 1
|6e9f9000| config_usb: 0x6f9e3320
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 1, len 8]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 2, len 8]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 3, len 0]
|6e9f9000| xhci_doorbell: slotid 3, epid 1
|6e9fa000| xhci_hub_reset port #7: 0x000006e1, powered, pls 7, speed 1 [Full]
|6e9f9000| xhci_process_events: ring 0x6f9e3200 [trb 0x6f9e3220, evt 0x6f9e3300, type 32, eidx 3, cc 1]
|6e9f9000| device rev=0200 cls=00 sub=00 proto=00 size=8
|6e9f9000| xhci_realloc_pipe: usbdev 0x6e9fc060, ring 0x6f9e3200, slotid 3, epid 1
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 4, len 8]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 5, len 9]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 6, len 0]
|6e9f9000| xhci_doorbell: slotid 3, epid 1
|6e9f9000| xhci_process_events: ring 0x6f9e3200 [trb 0x6f9e3250, evt 0x6f9e3300, type 32, eidx 6, cc 1]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 7, len 8]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 8, len 41]
|6e9f9000| xhci_trb_queue: ring 0x6f9e3200 [nidx 9, len 0]
|6e9f9000| xhci_doorbell: slotid 3, epid 1
|6e9f9000| xhci_process_events port #7: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
|6e9f9000| xhci_process_events: ring 0x6f9e3200 [trb 0x6f9e3280, evt 0x6f9e3300, type 32, eidx 9, cc 1]
\6e9f9000/ End thread
|6e9fa000| XHCI port #7: 0x00000603, powered, enabled, pls 0, speed 1 [Full]
|6e9fa000| set_address 0x6fa0bfb0
|6e9fa000| xhci_alloc_pipe: usbdev 0x6e9fc530, ring 0x6f9e3000, slotid 0, epid 1
|6e9fa000| xhci_cmd_enable_slot:
|6e9fa000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 8, len 0]
|6e9fa000| xhci_doorbell: slotid 0, epid 0
|6e9fa000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc70, evt 0x6fa0bd00, type 33, eidx 8, cc 1]
|6e9fa000| xhci_alloc_pipe: enable slot: got slotid 4
|6e9fa000| xhci_cmd_address_device: slotid 4
|6e9fa000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 9, len 0]
|6e9fa000| xhci_doorbell: slotid 0, epid 0
|6e9fa000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc80, evt 0x6fa0bd00, type 33, eidx 9, cc 1]
|6e9fa000| xhci_realloc_pipe: usbdev 0x6e9fc530, ring 0x6f9e3000, slotid 4, epid 1
|6e9fa000| config_usb: 0x6f9e3120
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 1, len 8]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 2, len 8]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 3, len 0]
|6e9fa000| xhci_doorbell: slotid 4, epid 1
|6e9fa000| xhci_process_events: ring 0x6f9e3000 [trb 0x6f9e3020, evt 0x6f9e3100, type 32, eidx 3, cc 1]
|6e9fa000| device rev=0200 cls=e0 sub=01 proto=01 size=64
|6e9fa000| xhci_realloc_pipe: usbdev 0x6e9fc530, ring 0x6f9e3000, slotid 4, epid 1
|6e9fa000| xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
|6e9fa000| xhci_cmd_evaluate_context: slotid 4, add 0x2, del 0x0
|6e9fa000| xhci_trb_queue: ring 0x6fa0bc00 [nidx 10, len 0]
|6e9fa000| xhci_doorbell: slotid 0, epid 0
|6e9fa000| xhci_process_events: ring 0x6fa0bc00 [trb 0x6fa0bc90, evt 0x6fa0bd00, type 33, eidx 10, cc 1]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 4, len 8]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 5, len 9]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 6, len 0]
|6e9fa000| xhci_doorbell: slotid 4, epid 1
|6e9fa000| xhci_process_events: ring 0x6f9e3000 [trb 0x6f9e3050, evt 0x6f9e3100, type 32, eidx 6, cc 1]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 7, len 8]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 8, len 177]
|6e9fa000| xhci_trb_queue: ring 0x6f9e3000 [nidx 9, len 0]
|6e9fa000| xhci_doorbell: slotid 4, epid 1
|6e9fa000| xhci_process_events: ring 0x6f9e3000 [trb 0x6f9e3080, evt 0x6f9e3100, type 32, eidx 9, cc 1]
\6e9fa000/ End thread
|6e9fb000| XHCI no devices found
\6e9fb000/ End thread
All threads complete.
Scan for option roms
Attempting to init PCI bdf 00:00.0 (vd 8086:5904)
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:04.0 (vd 8086:1903)
Attempting to map option rom on dev 00:04.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.2 (vd 8086:9d31)
Attempting to map option rom on dev 00:14.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:19.0 (vd 8086:9d66)
Attempting to map option rom on dev 00:19.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1c.0 (vd 8086:9d10)
Attempting to map option rom on dev 00:1c.0
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:1c.2 (vd 8086:9d12)
Attempting to map option rom on dev 00:1c.2
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:1c.4 (vd 8086:9d14)
Attempting to map option rom on dev 00:1c.4
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:1d.0 (vd 8086:9d18)
Attempting to map option rom on dev 00:1d.0
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:1f.0 (vd 8086:9d4e)
Attempting to map option rom on dev 00:1f.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.2 (vd 8086:9d21)
Attempting to map option rom on dev 00:1f.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.3 (vd 8086:9d71)
Attempting to map option rom on dev 00:1f.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.4 (vd 8086:9d23)
Attempting to map option rom on dev 00:1f.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.6 (vd 8086:15d7)
Attempting to map option rom on dev 00:1f.6
Option rom sizing returned 0 0
Attempting to init PCI bdf 01:00.0 (vd 10ec:525a)
Attempting to map option rom on dev 01:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 02:00.0 (vd 8086:24fd)
Attempting to map option rom on dev 02:00.0
Option rom sizing returned 0 0

Press ESC for boot menu.
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