coreboot

[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 bootblock starting (log level: 6)...

[DEBUG] CPU: Intel(R) N150

[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001e

[DEBUG] CPU: AES supported, TXT supported, VT supported

[INFO ] Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 8192

[INFO ] Cache size = 6 MiB

[DEBUG] MCH: device id 461c (rev 00) is Alderlake-N

[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU

[DEBUG] IGD: device id 46d4 (rev 00) is Alderlake N GT5

[DEBUG] Starting cbfs_boot_device

[DEBUG] Starting cbfs_boot_device

[DEBUG] FMAP: Found "FLASH" version 1.1 at 0xc90000.

[DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 5

[DEBUG] FMAP: area COREBOOT found @ c91000 (3600384 bytes)

[INFO ] Booting from COREBOOT region

[INFO ] CBFS: mcache @0xfef8ca00 built for 15 files, used 0x33c of 0x4000 bytes

[INFO ] CBFS: Found 'fallback/romstage' @0x22140 size 0x154e8 in mcache @0xfef8ca8c

[INFO ] VB2:vb2_digest_init() 87272 bytes, hash algo 2, HW acceleration unsupported

[INFO ] TPM LOG: clearing the log

[DEBUG] FMAP: area FMAP found @ c90000 (512 bytes)

[INFO ] VB2:vb2_digest_init() 512 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `FMAP: FMAP` to PCR 2 logged

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'bootblock' @0x365fc0 size 0x9000 in mcache @0xfef8ccf8

[INFO ] VB2:vb2_digest_init() 36864 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: bootblock` to PCR 2 logged

[DEBUG] CRTM initialized.

[DEBUG] TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged

[DEBUG] BS: bootblock times (exec / console): total (unknown) / 88 ms

[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 romstage starting (log level: 6)...

[DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00

[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000

[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000

[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000

[DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000

[DEBUG] TCO_STS: 0000 0000

[DEBUG] GEN_PMCON: d8a01a38 00002200

[DEBUG] GBLRST_CAUSE: 00000000 00000000

[DEBUG] HPR_CAUSE0: 00000002

[DEBUG] prev_sleep_state 0 (S0)

[INFO ] OC Watchdog: disabling watchdog timer

[INFO ] TXT disabled successfully - Unlocked memory

[DEBUG] Starting cbfs_boot_device

[DEBUG] FMAP: area COREBOOT found @ c91000 (3600384 bytes)

[INFO ] Booting from COREBOOT region

[INFO ] CBFS: Found 'fspm.bin' @0x5dfc0 size 0xc0000 in mcache @0xfef8cbe4

[INFO ] VB2:vb2_digest_init() 786432 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: fspm.bin` to PCR 2 logged

[DEBUG] FMAP: area RW_MRC_CACHE found @ c00000 (65536 bytes)

[INFO ] VB2:vb2_digest_init() 63176 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `MRC: training cache` to PCR 3 logged

[INFO ] SPD: module type is DDR5

[INFO ] SPD: banks 64, ranks 1, rows 16, columns 10, density 16384 Mb

[INFO ] SPD: device width 4 bits, bus width 32 bits

[INFO ] SPD: module size is 16384 MB (8192 MB per channel)

[DEBUG] CBMEM:

[DEBUG] IMD: root @ 0x76fff000 254 entries.

[DEBUG] IMD: root @ 0x76ffec00 62 entries.

[DEBUG] Starting cbfs_boot_device

[DEBUG] External stage cache:

[DEBUG] IMD: root @ 0x7bbff000 254 entries.

[DEBUG] IMD: root @ 0x7bbfec00 62 entries.

[DEBUG] FMAP: area RW_MRC_CACHE found @ c00000 (65536 bytes)

[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.

[DEBUG] MRC: 'RW_MRC_CACHE' does not need update.

[DEBUG] 1 DIMMs found

[DEBUG] SMM Memory Map

[DEBUG] SMRAM : 0x7b800000 0x800000

[DEBUG] Subregion 0: 0x7b800000 0x200000

[DEBUG] Subregion 1: 0x7ba00000 0x200000

[DEBUG] Subregion 2: 0x7bc00000 0x400000

[DEBUG] top_of_ram = 0x77000000

[DEBUG] Normal boot

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'fallback/postcar' @0x168240 size 0x10574 in mcache @0xfef8cc88

[INFO ] VB2:vb2_digest_init() 66932 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: fallback/postcar` to PCR 2 logged

[DEBUG] Loading module at 0x76bf2000 with entry 0x76bf2031. filesize: 0xf710 memsize: 0x15b80

[DEBUG] Processing 905 relocs. Offset value of 0x74bf2000

[DEBUG] BS: romstage times (exec / console): total (unknown) / 99 ms

[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 postcar starting (log level: 6)...

[DEBUG] Normal boot

[DEBUG] Starting cbfs_boot_device

[DEBUG] FMAP: area COREBOOT found @ c91000 (3600384 bytes)

[INFO ] Booting from COREBOOT region

[INFO ] CBFS: Found 'fallback/ramstage' @0x376c0 size 0x22f63 in mcache @0x76c0d0ec

[INFO ] VB2:vb2_digest_init() 143203 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged

[DEBUG] Loading module at 0x76a8e000 with entry 0x76a8e000. filesize: 0x4a368 memsize: 0x162e70

[DEBUG] Processing 5409 relocs. Offset value of 0x72a8e000

[DEBUG] BS: postcar times (exec / console): total (unknown) / 36 ms

[NOTE ] coreboot-25.12-537-gc9578eac246f-dirty Thu Feb 19 19:22:37 UTC 2026 x86_32 ramstage starting (log level: 6)...

[DEBUG] Normal boot

[DEBUG] microcode: sig=0xb06e0 pf=0x8 revision=0x1e

[DEBUG] Starting cbfs_boot_device

[DEBUG] FMAP: area COREBOOT found @ c91000 (3600384 bytes)

[INFO ] Booting from COREBOOT region

[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x22000 in mcache @0x76c0d02c

[INFO ] VB2:vb2_digest_init() 139264 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: cpu_microcode_blob.bin` to PCR 2 logged

[INFO ] microcode: Update skipped, already up-to-date

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'fsps.bin' @0x11e000 size 0x49cb4 in mcache @0x76c0d224

[INFO ] VB2:vb2_digest_init() 302260 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: fsps.bin` to PCR 2 logged

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Setting up SMI for CPU

[DEBUG] IED base = 0x7bc00000

[DEBUG] IED size = 0x00400000

[INFO ] Will perform SMM setup.

[INFO ] CPU: Intel(R) N150.

[INFO ] LAPIC 0x0 switched to X2APIC mode.

[DEBUG] CPU: APIC: 00 enabled

[DEBUG] CPU: APIC: 01 enabled

[DEBUG] CPU: APIC: 02 enabled

[DEBUG] CPU: APIC: 03 enabled

[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178

[DEBUG] Processing 16 relocs. Offset value of 0x00030000

[DEBUG] Attempting to start 3 APs

[DEBUG] Waiting for 10ms after sending INIT.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[DEBUG] Waiting for SIPI to complete...

[DEBUG] done.

[INFO ] LAPIC 0x2 switched to X2APIC mode.

[INFO ] LAPIC 0x6 switched to X2APIC mode.

[INFO ] LAPIC 0x4 switched to X2APIC mode.

[INFO ] AP: slot 3 apic_id 6, MCU rev: 0x0000001e

[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x0000001e

[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x0000001e

[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1c0 memsize: 0x1c0

[DEBUG] Processing 9 relocs. Offset value of 0x00038000

[DEBUG] smm_module_setup_stub: stack_top = 0x7b802000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000

[DEBUG] SMM Module: stub loaded at 38000. Will call 0x76ab1d11

[DEBUG] Installing permanent SMM handler to 0x7b800000

[DEBUG] HANDLER [0x7b9fd000-0x7b9ffea7]

[DEBUG] CPU 0

[DEBUG] ss0 [0x7b9fcc00-0x7b9fcfff]

[DEBUG] stub0 [0x7b9f5000-0x7b9f51bf]

[DEBUG] CPU 1

[DEBUG] ss1 [0x7b9fc800-0x7b9fcbff]

[DEBUG] stub1 [0x7b9f4c00-0x7b9f4dbf]

[DEBUG] CPU 2

[DEBUG] ss2 [0x7b9fc400-0x7b9fc7ff]

[DEBUG] stub2 [0x7b9f4800-0x7b9f49bf]

[DEBUG] CPU 3

[DEBUG] ss3 [0x7b9fc000-0x7b9fc3ff]

[DEBUG] stub3 [0x7b9f4400-0x7b9f45bf]

[DEBUG] stacks [0x7b800000-0x7b801fff]

[DEBUG] Loading module at 0x7b9fd000 with entry 0x7b9fd725. filesize: 0x2d58 memsize: 0x2ea8

[DEBUG] Processing 220 relocs. Offset value of 0x7b9fd000

[DEBUG] FMAP: area SMMSTORE found @ c10000 (524288 bytes)

[DEBUG] smm store: 8 # blocks with size 0x10000

[DEBUG] Loading module at 0x7b9f5000 with entry 0x7b9f5000. filesize: 0x1c0 memsize: 0x1c0

[DEBUG] Processing 9 relocs. Offset value of 0x7b9f5000

[DEBUG] smm_module_setup_stub: stack_top = 0x7b802000

[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800

[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000

[DEBUG] SMM Module: placing smm entry code at 7b9f4c00, cpu # 0x1

[DEBUG] SMM Module: placing smm entry code at 7b9f4800, cpu # 0x2

[DEBUG] SMM Module: placing smm entry code at 7b9f4400, cpu # 0x3

[DEBUG] SMM Module: stub loaded at 7b9f5000. Will call 0x7b9fd725

[DEBUG] Clearing SMI status registers

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9ed000, cpu = 0

[DEBUG] In relocation handler: CPU 0

[DEBUG] New SMBASE=0x7b9ed000 IEDBASE=0x7bc00000

[DEBUG] Writing SMRR. base = 0x7b800006, mask=0xff800c00

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9ec400, cpu = 3

[DEBUG] In relocation handler: CPU 3

[DEBUG] New SMBASE=0x7b9ec400 IEDBASE=0x7bc00000

[DEBUG] Writing SMRR. base = 0x7b800006, mask=0xff800c00

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9ec800, cpu = 2

[DEBUG] In relocation handler: CPU 2

[DEBUG] New SMBASE=0x7b9ec800 IEDBASE=0x7bc00000

[DEBUG] Writing SMRR. base = 0x7b800006, mask=0xff800c00

[DEBUG] Relocation complete.

[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9ecc00, cpu = 1

[DEBUG] In relocation handler: CPU 1

[DEBUG] New SMBASE=0x7b9ecc00 IEDBASE=0x7bc00000

[DEBUG] Writing SMRR. base = 0x7b800006, mask=0xff800c00

[DEBUG] Relocation complete.

[INFO ] Initializing CPU #0

[DEBUG] CPU: vendor Intel device b06e0

[DEBUG] CPU: family 06, model be, stepping 00

[DEBUG] Clearing out pending MCEs

[DEBUG] cpu: energy policy set to 7

[INFO ] Turbo is available but hidden

[INFO ] Turbo is available and visible

[INFO ] microcode: Update skipped, already up-to-date

[INFO ] CPU #0 initialized

[INFO ] Initializing CPU #2

[INFO ] Initializing CPU #3

[DEBUG] CPU: vendor Intel device b06e0

[DEBUG] CPU: family 06, model be, stepping 00

[INFO ] Initializing CPU #1

[DEBUG] Clearing out pending MCEs

[DEBUG] CPU: vendor Intel device b06e0

[DEBUG] CPU: family 06, model be, stepping 00

[DEBUG] CPU: vendor Intel device b06e0

[DEBUG] CPU: family 06, model be, stepping 00

[DEBUG] Clearing out pending MCEs

[DEBUG] Clearing out pending MCEs

[DEBUG] cpu: energy policy set to 7

[DEBUG] cpu: energy policy set to 7

[DEBUG] cpu: energy policy set to 7

[INFO ] microcode: Update skipped, already up-to-date

[INFO ] CPU #2 initialized

[INFO ] microcode: Update skipped, already up-to-date

[INFO ] CPU #3 initialized

[INFO ] microcode: Update skipped, already up-to-date

[INFO ] CPU #1 initialized

[INFO ] bsp_do_flight_plan done after 131 msecs.

[DEBUG] CPU: frequency set to 3600 MHz

[DEBUG] Enabling SMIs.

[DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 155 / 96 ms

[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found

[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found

[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found

[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found

[DEBUG] All HSPHY ports disabled, skipping HSPHY loading

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'vbt.bin' @0x167d00 size 0x4e8 in mcache @0x76c0d258

[INFO ] VB2:vb2_digest_init() 1256 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 logged

[INFO ] Found a VBT of 9216 bytes

[INFO ] PCI 1.0, PIN A, using IRQ #16

[INFO ] PCI 2.0, PIN A, using IRQ #17

[INFO ] PCI 4.0, PIN A, using IRQ #18

[INFO ] PCI 5.0, PIN A, using IRQ #16

[INFO ] PCI 6.0, PIN D, using IRQ #16

[INFO ] PCI 6.2, PIN B, using IRQ #18

[INFO ] PCI 7.0, PIN A, using IRQ #19

[INFO ] PCI 7.1, PIN B, using IRQ #20

[INFO ] PCI 7.2, PIN C, using IRQ #21

[INFO ] PCI 7.3, PIN D, using IRQ #22

[INFO ] PCI 8.0, PIN A, using IRQ #23

[INFO ] PCI D.0, PIN A, using IRQ #17

[INFO ] PCI D.1, PIN B, using IRQ #19

[INFO ] PCI 10.0, PIN A, using IRQ #24

[INFO ] PCI 10.1, PIN B, using IRQ #25

[INFO ] PCI 10.6, PIN C, using IRQ #20

[INFO ] PCI 10.7, PIN D, using IRQ #21

[INFO ] PCI 11.0, PIN A, using IRQ #26

[INFO ] PCI 11.1, PIN B, using IRQ #27

[INFO ] PCI 11.2, PIN C, using IRQ #28

[INFO ] PCI 11.3, PIN D, using IRQ #29

[INFO ] PCI 12.0, PIN A, using IRQ #30

[INFO ] PCI 12.6, PIN B, using IRQ #31

[INFO ] PCI 12.7, PIN C, using IRQ #22

[INFO ] PCI 13.0, PIN A, using IRQ #32

[INFO ] PCI 13.1, PIN B, using IRQ #33

[INFO ] PCI 13.2, PIN C, using IRQ #34

[INFO ] PCI 13.3, PIN D, using IRQ #35

[INFO ] PCI 14.0, PIN B, using IRQ #23

[INFO ] PCI 14.1, PIN A, using IRQ #36

[INFO ] PCI 14.3, PIN C, using IRQ #17

[INFO ] PCI 15.0, PIN A, using IRQ #37

[INFO ] PCI 15.1, PIN B, using IRQ #38

[INFO ] PCI 15.2, PIN C, using IRQ #39

[INFO ] PCI 15.3, PIN D, using IRQ #40

[INFO ] PCI 16.0, PIN A, using IRQ #18

[INFO ] PCI 16.1, PIN B, using IRQ #19

[INFO ] PCI 16.2, PIN C, using IRQ #20

[INFO ] PCI 16.3, PIN D, using IRQ #21

[INFO ] PCI 16.4, PIN A, using IRQ #18

[INFO ] PCI 16.5, PIN B, using IRQ #19

[INFO ] PCI 17.0, PIN A, using IRQ #22

[INFO ] PCI 19.0, PIN A, using IRQ #41

[INFO ] PCI 19.1, PIN B, using IRQ #42

[INFO ] PCI 19.2, PIN C, using IRQ #44

[INFO ] PCI 1A.0, PIN A, using IRQ #23

[INFO ] PCI 1C.0, PIN A, using IRQ #16

[INFO ] PCI 1C.1, PIN B, using IRQ #17

[INFO ] PCI 1C.2, PIN C, using IRQ #18

[INFO ] PCI 1C.3, PIN D, using IRQ #19

[INFO ] PCI 1C.4, PIN A, using IRQ #16

[INFO ] PCI 1C.5, PIN B, using IRQ #17

[INFO ] PCI 1C.6, PIN C, using IRQ #18

[INFO ] PCI 1C.7, PIN D, using IRQ #19

[INFO ] PCI 1D.0, PIN A, using IRQ #16

[INFO ] PCI 1D.1, PIN B, using IRQ #17

[INFO ] PCI 1D.2, PIN C, using IRQ #18

[INFO ] PCI 1D.3, PIN D, using IRQ #19

[INFO ] PCI 1E.0, PIN A, using IRQ #20

[INFO ] PCI 1E.1, PIN B, using IRQ #21

[INFO ] PCI 1E.2, PIN C, using IRQ #45

[INFO ] PCI 1E.3, PIN D, using IRQ #46

[INFO ] PCI 1F.3, PIN B, using IRQ #23

[INFO ] PCI 1F.4, PIN C, using IRQ #20

[INFO ] PCI 1F.6, PIN D, using IRQ #21

[INFO ] PCI 1F.7, PIN A, using IRQ #22

[INFO ] IRQ: Using dynamically assigned PCI IO-APIC IRQs

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[DEBUG] Detected 4 core, 4 thread CPU.

[INFO ] FSPS, status=0x00000000

[DEBUG] Display FSP Version Info HOB

[DEBUG] Reference Code - CPU = c.e0.8a.20

[DEBUG] uCode Version = 0.0.0.1e

[DEBUG] TXT ACM version = ff.ff.ff.ffff

[DEBUG] Reference Code - ME = c.e0.8a.20

[DEBUG] MEBx version = 0.0.0.0

[DEBUG] ME Firmware Version = Consumer SKU

[DEBUG] Reference Code - PCH = c.e0.8a.20

[DEBUG] PCH-CRID Status = Disabled

[DEBUG] PCH-CRID Original Value = ff.ff.ff.ffff

[DEBUG] PCH-CRID New Value = ff.ff.ff.ffff

[DEBUG] OPROM - RST - RAID = ff.ff.ff.ffff

[DEBUG] PCH Hsio Version = 4.0.0.0

[DEBUG] Reference Code - SA - System Agent = c.e0.8a.20

[DEBUG] Reference Code - MRC = 1.0.4.4d

[DEBUG] SA - PCIe Version = c.e0.8a.20

[DEBUG] SA-CRID Status = Disabled

[DEBUG] SA-CRID Original Value = 0.0.0.0

[DEBUG] SA-CRID New Value = 0.0.0.0

[DEBUG] OPROM - VBIOS = ff.ff.ff.ffff

[DEBUG] IO Manageability Engine FW Version = 23.0.9.0

[DEBUG] PHY Build Version = 0.0.0.0

[DEBUG] Thunderbolt(TM) FW Version = 0.0.0.0

[DEBUG] System Agent Manageability Engine FW Version = ff.ff.ff.ffff

[INFO ] Found PCIe Root Port #1 at PCI: 00:1c.0.

[INFO ] Found PCIe Root Port #2 at PCI: 00:1c.1.

[INFO ] Found PCIe Root Port #3 at PCI: 00:1c.2.

[INFO ] Found PCIe Root Port #7 at PCI: 00:1c.6.

[INFO ] Found PCIe Root Port #9 at PCI: 00:1d.0.

[NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:00:1d.2) which was enabled in devicetree, removing and disabling.

[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 229 / 419 ms

[INFO ] Enumerating buses...

[DEBUG] Root Device scanning...

[DEBUG] CPU_CLUSTER: 0 enabled

[DEBUG] DOMAIN: 00000000 enabled

[DEBUG] DOMAIN: 00000000 scanning...

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00

[DEBUG] PCI: 00:00:00.0 [8086/461c] enabled

[DEBUG] PCI: 00:00:02.0 [8086/46d4] enabled

[INFO ] PCI: Static device PCI: 00:00:0a.0 not found, disabling it.

[DEBUG] PCI: 00:00:14.0 [8086/54ed] enabled

[DEBUG] PCI: 00:00:14.2 [8086/54ef] enabled

[DEBUG] HSFSTS: 0x6000

[DEBUG] CMOS: me_state = 0

[DEBUG] ME is enabled.

[DEBUG] PCI: 00:00:16.0 [8086/54e0] enabled

[DEBUG] PCI: 00:00:17.0 [8086/54d3] enabled

[DEBUG] PCI: 00:00:1c.0 [8086/54b8] enabled

[DEBUG] PCI: 00:00:1c.1 [8086/54b9] enabled

[DEBUG] PCI: 00:00:1c.2 [8086/54ba] enabled

[DEBUG] PCI: 00:00:1c.6 [8086/54be] enabled

[DEBUG] PCI: 00:00:1d.0 [8086/54b0] enabled

[DEBUG] PCI: 00:00:1f.0 [8086/5481] enabled

[DEBUG] PCI: 00:00:1f.1 [0000/0000] hidden

[DEBUG] RTC Init

[INFO ] Set power on after power failure.

[DEBUG] Disabling Deep S3

[DEBUG] Disabling Deep S3

[DEBUG] Disabling Deep S4

[DEBUG] Disabling Deep S4

[DEBUG] Disabling Deep S5

[DEBUG] Disabling Deep S5

[DEBUG] PCI: 00:00:1f.2 [0000/0000] hidden

[DEBUG] PCI: 00:00:1f.3 [8086/54c8] enabled

[DEBUG] PCI: 00:00:1f.4 [8086/54a3] enabled

[DEBUG] PCI: 00:00:1f.5 [8086/54a4] enabled

[DEBUG] GPIO: 0 enabled

[DEBUG] MMIO: fed40000 enabled

[DEBUG] PCI: 00:00:02.0 scanning...

[DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs

[DEBUG] PCI: 00:00:14.0 scanning...

[DEBUG] USB0 port 0 disabled

[DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs

[DEBUG] PCI: 00:00:1c.0 scanning...

[INFO ] PCI: 00:00:1c.0: Enabled LTR

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01

[DEBUG] PCI: 00:01:00.0 [8086/125c] enabled

[INFO ] PCIe: Common Clock Configuration already enabled

[INFO ] PCIE CLK PM is not supported by endpoint

[INFO ] L1 Sub-State supported from root port 28

[INFO ] L1 Sub-State Support = 0xa

[INFO ] CommonModeRestoreTime = 0x37

[INFO ] Power On Value = 0x7, Power On Scale = 0x1

[INFO ] ASPM: Enabled None

[INFO ] PCI: 00:01:00.0: Enabled LTR

[INFO ] PCI: 00:01:00.0: Programmed LTR max latencies

[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port

[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 61 msecs

[DEBUG] PCI: 00:00:1c.1 scanning...

[INFO ] PCI: 00:00:1c.1: Enabled LTR

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02

[DEBUG] PCI: 00:02:00.0 [8086/125c] enabled

[INFO ] PCIe: Common Clock Configuration already enabled

[INFO ] PCIE CLK PM is not supported by endpoint

[INFO ] L1 Sub-State supported from root port 28

[INFO ] L1 Sub-State Support = 0xa

[INFO ] CommonModeRestoreTime = 0x37

[INFO ] Power On Value = 0x7, Power On Scale = 0x1

[INFO ] ASPM: Enabled None

[INFO ] PCI: 00:02:00.0: Enabled LTR

[INFO ] PCI: 00:02:00.0: Programmed LTR max latencies

[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port

[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 60 msecs

[DEBUG] PCI: 00:00:1c.2 scanning...

[INFO ] PCI: 00:00:1c.2: Enabled LTR

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03

[DEBUG] PCI: 00:03:00.0 [8086/125c] enabled

[INFO ] PCIe: Common Clock Configuration already enabled

[INFO ] PCIE CLK PM is not supported by endpoint

[INFO ] L1 Sub-State supported from root port 28

[INFO ] L1 Sub-State Support = 0xa

[INFO ] CommonModeRestoreTime = 0x37

[INFO ] Power On Value = 0x7, Power On Scale = 0x1

[INFO ] ASPM: Enabled None

[INFO ] PCI: 00:03:00.0: Enabled LTR

[INFO ] PCI: 00:03:00.0: Programmed LTR max latencies

[INFO ] PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port

[DEBUG] scan_bus: bus PCI: 00:00:1c.2 finished in 60 msecs

[DEBUG] PCI: 00:00:1c.6 scanning...

[INFO ] PCI: 00:00:1c.6: Enabled LTR

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 04

[DEBUG] PCI: 00:04:00.0 [8086/125c] enabled

[INFO ] PCIe: Common Clock Configuration already enabled

[INFO ] PCIE CLK PM is not supported by endpoint

[INFO ] L1 Sub-State supported from root port 28

[INFO ] L1 Sub-State Support = 0xa

[INFO ] CommonModeRestoreTime = 0x37

[INFO ] Power On Value = 0x7, Power On Scale = 0x1

[INFO ] ASPM: Enabled None

[INFO ] PCI: 00:04:00.0: Enabled LTR

[INFO ] PCI: 00:04:00.0: Programmed LTR max latencies

[INFO ] PCI: 00:00:1c.6: Setting Max_Payload_Size to 128 for devices under this root port

[DEBUG] scan_bus: bus PCI: 00:00:1c.6 finished in 61 msecs

[DEBUG] PCI: 00:00:1d.0 scanning...

[INFO ] PCI: 00:00:1d.0: Enabled LTR

[DEBUG] PCI: pci_scan_bus for segment group 00 bus 05

[DEBUG] PCI: 00:05:00.0 [2646/5029] enabled

[INFO ] PCIe: Common Clock Configuration already enabled

[INFO ] ASPM: Enabled None

[INFO ] PCI: 00:05:00.0: Enabled LTR

[INFO ] PCI: 00:05:00.0: Programmed LTR max latencies

[INFO ] PCI: 00:00:1d.0: Setting Max_Payload_Size to 128 for devices under this root port

[DEBUG] scan_bus: bus PCI: 00:00:1d.0 finished in 34 msecs

[DEBUG] PCI: 00:00:1f.0 scanning...

[DEBUG] PNP: 002e.1 enabled

[DEBUG] PNP: 002e.2 enabled

[DEBUG] PNP: 002e.3 enabled

[DEBUG] PNP: 002e.4 enabled

[DEBUG] PNP: 002e.5 enabled

[DEBUG] PNP: 002e.6 enabled

[DEBUG] PNP: 002e.7 enabled

[DEBUG] PNP: 002e.8 enabled

[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs

[DEBUG] PCI: 00:00:1f.2 scanning...

[DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs

[DEBUG] PCI: 00:00:1f.3 scanning...

[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs

[DEBUG] PCI: 00:00:1f.4 scanning...

[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs

[DEBUG] PCI: 00:00:1f.5 scanning...

[DEBUG] scan_bus: bus PCI: 00:00:1f.5 finished in 0 msecs

[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 292 msecs

[DEBUG] scan_bus: bus Root Device finished in 292 msecs

[INFO ] done

[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 297 ms

[INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'

[DEBUG] FMAP: area RW_MRC_CACHE found @ c00000 (65536 bytes)

[INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.

[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 12 ms

[DEBUG] found VGA at PCI: 00:00:02.0

[DEBUG] Setting up VGA for PCI: 00:00:02.0

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000

[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

[INFO ] Allocating resources...

[INFO ] Reading resources...

[DEBUG] SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000

[DEBUG] SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000

[DEBUG] SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000

[DEBUG] SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x00001000

[DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000

[DEBUG] SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000

[DEBUG] SA MMIO resource: TPM -> base = 0xfed40000, size = 0x00010000

[DEBUG] SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x00020000

[DEBUG] SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000

[DEBUG] SA MMIO resource: PCH_RESERVED -> base = 0xfc800000, size = 0x02000000

[DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000

[DEBUG] SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x00001000

[DEBUG] SA MMIO resource: TBT0BAR -> base = 0xfed84000, size = 0x00001000

[DEBUG] SA MMIO resource: TBT1BAR -> base = 0xfed85000, size = 0x00001000

[DEBUG] SA MMIO resource: TBT2BAR -> base = 0xfed86000, size = 0x00001000

[DEBUG] SA MMIO resource: TBT3BAR -> base = 0xfed87000, size = 0x00001000

[DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000

[DEBUG] SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000

[DEBUG] SA MMIO resource: DSM -> base = 0x7c800000, size = 0x03c00000

[DEBUG] SA MMIO resource: TSEG -> base = 0x7b800000, size = 0x00800000

[DEBUG] SA MMIO resource: GSM -> base = 0x7c000000, size = 0x00800000

[INFO ] Available memory above 4GB: 14332M

[DEBUG] PCI: 00:00:02.0: supports 7 SR-IOV VFs

[DEBUG] PCI: 00:00:02.0: found 64bit SR-IOV BAR, size 0x1000000 @ index 344

[DEBUG] PCI: 00:00:02.0: found 64bit SR-IOV BAR, size 0x20000000 @ index 34c

[INFO ] Done reading resources.

[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===

[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff

[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done

[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff

[DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0xfffff] mem

[DEBUG] PCI: 00:01:00.0 30 * [0x100000 - 0x1fffff] mem

[DEBUG] PCI: 00:01:00.0 1c * [0x200000 - 0x203fff] mem

[DEBUG] PCI: 00:00:1c.0 mem: size: 300000 align: 20 gran: 20 limit: ffffffff done

[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff

[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff

[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done

[DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff

[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0xfffff] mem

[DEBUG] PCI: 00:02:00.0 30 * [0x100000 - 0x1fffff] mem

[DEBUG] PCI: 00:02:00.0 1c * [0x200000 - 0x203fff] mem

[DEBUG] PCI: 00:00:1c.1 mem: size: 300000 align: 20 gran: 20 limit: ffffffff done

[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff

[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff

[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff done

[DEBUG] PCI: 00:00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff

[DEBUG] PCI: 00:03:00.0 10 * [0x0 - 0xfffff] mem

[DEBUG] PCI: 00:03:00.0 30 * [0x100000 - 0x1fffff] mem

[DEBUG] PCI: 00:03:00.0 1c * [0x200000 - 0x203fff] mem

[DEBUG] PCI: 00:00:1c.2 mem: size: 300000 align: 20 gran: 20 limit: ffffffff done

[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff

[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

[DEBUG] PCI: 00:00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff

[DEBUG] PCI: 00:00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff done

[DEBUG] PCI: 00:00:1c.6 mem: size: 0 align: 20 gran: 20 limit: ffffffff

[DEBUG] PCI: 00:04:00.0 10 * [0x0 - 0xfffff] mem

[DEBUG] PCI: 00:04:00.0 30 * [0x100000 - 0x1fffff] mem

[DEBUG] PCI: 00:04:00.0 1c * [0x200000 - 0x203fff] mem

[DEBUG] PCI: 00:00:1c.6 mem: size: 300000 align: 20 gran: 20 limit: ffffffff done

[DEBUG] PCI: 00:00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff

[DEBUG] PCI: 00:00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

[DEBUG] PCI: 00:00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff

[DEBUG] PCI: 00:00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done

[DEBUG] PCI: 00:00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff

[DEBUG] PCI: 00:05:00.0 10 * [0x0 - 0x3fff] mem

[DEBUG] PCI: 00:00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done

[DEBUG] PCI: 00:00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff

[DEBUG] PCI: 00:00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done

[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===

[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000080 limit 0000008f io (fixed)

[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 000003f8 limit 000003ff io (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 01 base 00001800 limit 000018ff io (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)

[INFO ] DOMAIN: 00000000: Resource ranges:

[INFO ] * Base: 1000, Size: 800, Tag: 100

[INFO ] * Base: 1900, Size: d6a0, Tag: 100

[INFO ] * Base: efc0, Size: 1040, Tag: 100

[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io

[DEBUG] PCI: 00:00:17.0 20 * [0xffa0 - 0xffbf] limit: ffbf io

[DEBUG] PCI: 00:00:17.0 18 * [0xff98 - 0xff9f] limit: ff9f io

[DEBUG] PCI: 00:00:17.0 1c * [0xff94 - 0xff97] limit: ff97 io

[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done

[DEBUG] DOMAIN: 00000000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff

[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fedc0000 limit feddffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base feda0000 limit feda0fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base feda1000 limit feda1fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fb000000 limit fb000fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed80000 limit fed83fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base feb00000 limit feb7ffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed40000 limit fed4ffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed50000 limit fed6ffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base fec00000 limit fecfffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base fc800000 limit fe7fffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base fed90000 limit fed90fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base fed92000 limit fed92fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base fed84000 limit fed84fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base fed85000 limit fed85fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0e base fed86000 limit fed86fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0f base fed87000 limit fed87fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 10 base fed91000 limit fed91fff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 11 base c0000000 limit cfffffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 12 base 7c800000 limit 803fffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 13 base 7b800000 limit 7bffffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 14 base 7c000000 limit 7c7fffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 15 base 00000000 limit 0009ffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 16 base 000c0000 limit 76ffffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 17 base 77000000 limit 803fffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 18 base 100000000 limit 47fbfffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 19 base 000a0000 limit 000bffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 1a base 000c0000 limit 000fffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 10 base fe000000 limit fe00ffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.5 00 base ff000000 limit ffffffff mem (fixed)

[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.5 01 base f8000000 limit f9ffffff mem (fixed)

[INFO ] DOMAIN: 00000000: Resource ranges:

[INFO ] * Base: 80400000, Size: 3fc00000, Tag: 200

[INFO ] * Base: d0000000, Size: 10000000, Tag: 200

[INFO ] * Base: 47fc00000, Size: 7b80400000, Tag: 200

[DEBUG] PCI: 00:00:02.0 34c * [0x7f00000000 - 0x7fffffffff] limit: 7fffffffff prefmem

[DEBUG] PCI: 00:00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem

[DEBUG] PCI: 00:00:02.0 344 * [0x7ef8000000 - 0x7effffffff] limit: 7effffffff mem

[DEBUG] PCI: 00:00:02.0 10 * [0xbf000000 - 0xbfffffff] limit: bfffffff mem

[DEBUG] PCI: 00:00:1c.0 20 * [0xbed00000 - 0xbeffffff] limit: beffffff mem

[DEBUG] PCI: 00:00:1c.1 20 * [0xbea00000 - 0xbecfffff] limit: becfffff mem

[DEBUG] PCI: 00:00:1c.2 20 * [0xbe700000 - 0xbe9fffff] limit: be9fffff mem

[DEBUG] PCI: 00:00:1c.6 20 * [0xbe400000 - 0xbe6fffff] limit: be6fffff mem

[DEBUG] PCI: 00:00:1d.0 20 * [0xbe300000 - 0xbe3fffff] limit: be3fffff mem

[DEBUG] PCI: 00:00:1f.3 20 * [0xbe200000 - 0xbe2fffff] limit: be2fffff mem

[DEBUG] PCI: 00:00:14.0 10 * [0xbe1f0000 - 0xbe1fffff] limit: be1fffff mem

[DEBUG] PCI: 00:00:14.2 10 * [0xbe1ec000 - 0xbe1effff] limit: be1effff mem

[DEBUG] PCI: 00:00:1f.3 10 * [0xbe1e8000 - 0xbe1ebfff] limit: be1ebfff mem

[DEBUG] PCI: 00:00:17.0 10 * [0xbe1e6000 - 0xbe1e7fff] limit: be1e7fff mem

[DEBUG] PCI: 00:00:14.2 18 * [0xbe1e5000 - 0xbe1e5fff] limit: be1e5fff mem

[DEBUG] PCI: 00:00:16.0 10 * [0xbe1e4000 - 0xbe1e4fff] limit: be1e4fff mem

[DEBUG] PCI: 00:00:1f.5 10 * [0xbe1e3000 - 0xbe1e3fff] limit: be1e3fff mem

[DEBUG] PCI: 00:00:17.0 24 * [0xbe1e2000 - 0xbe1e27ff] limit: be1e27ff mem

[DEBUG] PCI: 00:00:17.0 14 * [0xbe1e1000 - 0xbe1e10ff] limit: be1e10ff mem

[DEBUG] PCI: 00:00:1f.4 10 * [0xbe1e0000 - 0xbe1e00ff] limit: be1e00ff mem

[DEBUG] DOMAIN: 00000000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff done

[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done

[DEBUG] PCI: 00:01:00.0 10 * [0xbed00000 - 0xbedfffff] limit: bedfffff mem

[DEBUG] PCI: 00:01:00.0 1c * [0xbef00000 - 0xbef03fff] limit: bef03fff mem

[DEBUG] PCI: 00:01:00.0 30 * [0xbee00000 - 0xbeefffff] limit: beefffff mem

[DEBUG] PCI: 00:02:00.0 10 * [0xbea00000 - 0xbeafffff] limit: beafffff mem

[DEBUG] PCI: 00:02:00.0 1c * [0xbec00000 - 0xbec03fff] limit: bec03fff mem

[DEBUG] PCI: 00:02:00.0 30 * [0xbeb00000 - 0xbebfffff] limit: bebfffff mem

[DEBUG] PCI: 00:03:00.0 10 * [0xbe700000 - 0xbe7fffff] limit: be7fffff mem

[DEBUG] PCI: 00:03:00.0 1c * [0xbe900000 - 0xbe903fff] limit: be903fff mem

[DEBUG] PCI: 00:03:00.0 30 * [0xbe800000 - 0xbe8fffff] limit: be8fffff mem

[DEBUG] PCI: 00:04:00.0 10 * [0xbe400000 - 0xbe4fffff] limit: be4fffff mem

[DEBUG] PCI: 00:04:00.0 1c * [0xbe600000 - 0xbe603fff] limit: be603fff mem

[DEBUG] PCI: 00:04:00.0 30 * [0xbe500000 - 0xbe5fffff] limit: be5fffff mem

[DEBUG] PCI: 00:05:00.0 10 * [0xbe300000 - 0xbe303fff] limit: be303fff mem

[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===

[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000bf000000 - 0x00000000bfffffff] size 0x01000000 gran 0x18 mem64

[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000d0000000 - 0x00000000dfffffff] size 0x10000000 gran 0x1c prefmem64

[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io

[DEBUG] PCI: 00:00:02.0 344 <- [0x0000007ef8000000 - 0x0000007effffffff] size 0x08000000 gran 0x1b mem64

[DEBUG] PCI: 00:00:02.0 34c <- [0x0000007f00000000 - 0x0000007fffffffff] size 0x100000000 gran 0x20 prefmem64

[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000be1f0000 - 0x00000000be1fffff] size 0x00010000 gran 0x10 mem64

[DEBUG] PCI: 00:00:14.2 10 <- [0x00000000be1ec000 - 0x00000000be1effff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:00:14.2 18 <- [0x00000000be1e5000 - 0x00000000be1e5fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000be1e4000 - 0x00000000be1e4fff] size 0x00001000 gran 0x0c mem64

[DEBUG] PCI: 00:00:17.0 10 <- [0x00000000be1e6000 - 0x00000000be1e7fff] size 0x00002000 gran 0x0d mem

[DEBUG] PCI: 00:00:17.0 14 <- [0x00000000be1e1000 - 0x00000000be1e10ff] size 0x00000100 gran 0x08 mem

[DEBUG] PCI: 00:00:17.0 18 <- [0x000000000000ff98 - 0x000000000000ff9f] size 0x00000008 gran 0x03 io

[DEBUG] PCI: 00:00:17.0 1c <- [0x000000000000ff94 - 0x000000000000ff97] size 0x00000004 gran 0x02 io

[DEBUG] PCI: 00:00:17.0 20 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io

[DEBUG] PCI: 00:00:17.0 24 <- [0x00000000be1e2000 - 0x00000000be1e27ff] size 0x00000800 gran 0x0b mem

[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io

[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem

[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000bed00000 - 0x00000000beffffff] size 0x00300000 gran 0x14 seg 00 bus 01 mem

[DEBUG] PCI: 00:01:00.0 10 <- [0x00000000bed00000 - 0x00000000bedfffff] size 0x00100000 gran 0x14 mem

[DEBUG] PCI: 00:01:00.0 1c <- [0x00000000bef00000 - 0x00000000bef03fff] size 0x00004000 gran 0x0e mem

[DEBUG] PCI: 00:01:00.0 30 <- [0x00000000bee00000 - 0x00000000beefffff] size 0x00100000 gran 0x14 romem

[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io

[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem

[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000bea00000 - 0x00000000becfffff] size 0x00300000 gran 0x14 seg 00 bus 02 mem

[DEBUG] PCI: 00:02:00.0 10 <- [0x00000000bea00000 - 0x00000000beafffff] size 0x00100000 gran 0x14 mem

[DEBUG] PCI: 00:02:00.0 1c <- [0x00000000bec00000 - 0x00000000bec03fff] size 0x00004000 gran 0x0e mem

[DEBUG] PCI: 00:02:00.0 30 <- [0x00000000beb00000 - 0x00000000bebfffff] size 0x00100000 gran 0x14 romem

[DEBUG] PCI: 00:00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io

[DEBUG] PCI: 00:00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem

[DEBUG] PCI: 00:00:1c.2 20 <- [0x00000000be700000 - 0x00000000be9fffff] size 0x00300000 gran 0x14 seg 00 bus 03 mem

[DEBUG] PCI: 00:03:00.0 10 <- [0x00000000be700000 - 0x00000000be7fffff] size 0x00100000 gran 0x14 mem

[DEBUG] PCI: 00:03:00.0 1c <- [0x00000000be900000 - 0x00000000be903fff] size 0x00004000 gran 0x0e mem

[DEBUG] PCI: 00:03:00.0 30 <- [0x00000000be800000 - 0x00000000be8fffff] size 0x00100000 gran 0x14 romem

[DEBUG] PCI: 00:00:1c.6 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 04 io

[DEBUG] PCI: 00:00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem

[DEBUG] PCI: 00:00:1c.6 20 <- [0x00000000be400000 - 0x00000000be6fffff] size 0x00300000 gran 0x14 seg 00 bus 04 mem

[DEBUG] PCI: 00:04:00.0 10 <- [0x00000000be400000 - 0x00000000be4fffff] size 0x00100000 gran 0x14 mem

[DEBUG] PCI: 00:04:00.0 1c <- [0x00000000be600000 - 0x00000000be603fff] size 0x00004000 gran 0x0e mem

[DEBUG] PCI: 00:04:00.0 30 <- [0x00000000be500000 - 0x00000000be5fffff] size 0x00100000 gran 0x14 romem

[DEBUG] PCI: 00:00:1d.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 05 io

[DEBUG] PCI: 00:00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 prefmem

[DEBUG] PCI: 00:00:1d.0 20 <- [0x00000000be300000 - 0x00000000be3fffff] size 0x00100000 gran 0x14 seg 00 bus 05 mem

[DEBUG] PCI: 00:05:00.0 10 <- [0x00000000be300000 - 0x00000000be303fff] size 0x00004000 gran 0x0e mem64

[DEBUG] PNP: 002e.1 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io

[DEBUG] PNP: 002e.1 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq

[DEBUG] PNP: 002e.1 f0 <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq

[NOTE ] PNP: 002e.2 60 io size: 0x0000000008 not assigned in devicetree

[NOTE ] PNP: 002e.2 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.3 60 io size: 0x0000000008 not assigned in devicetree

[NOTE ] PNP: 002e.3 62 io size: 0x0000000008 not assigned in devicetree

[NOTE ] PNP: 002e.3 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.3 74 drq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.4 60 io size: 0x0000000010 not assigned in devicetree

[NOTE ] PNP: 002e.4 62 io size: 0x0000000010 not assigned in devicetree

[NOTE ] PNP: 002e.4 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.5 60 io size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.5 62 io size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.5 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.6 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.7 60 io size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.7 62 io size: 0x0000000020 not assigned in devicetree

[NOTE ] PNP: 002e.7 64 io size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.7 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree

[NOTE ] PNP: 002e.8 70 irq size: 0x0000000001 not assigned in devicetree

[NOTE ] PNP: 002e.8 f0 irq size: 0x0000000001 not assigned in devicetree

[DEBUG] LPC: enabling default decode range LPC_IOE_COMA_EN

[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000be1e8000 - 0x00000000be1ebfff] size 0x00004000 gran 0x0e mem64

[DEBUG] PCI: 00:00:1f.3 20 <- [0x00000000be200000 - 0x00000000be2fffff] size 0x00100000 gran 0x14 mem64

[DEBUG] PCI: 00:00:1f.4 10 <- [0x00000000be1e0000 - 0x00000000be1e00ff] size 0x00000100 gran 0x08 mem64

[DEBUG] PCI: 00:00:1f.5 10 <- [0x00000000be1e3000 - 0x00000000be1e3fff] size 0x00001000 gran 0x0c mem

[INFO ] Done setting resources.

[INFO ] Done allocating resources.

[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 4 / 255 ms

[INFO ] coreboot skipped calling FSP notify phase: 00000020.

[INFO ] LAPIC 0x0 in X2APIC mode.

[DEBUG] MTRR: Physical address space:

[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6

[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0

[DEBUG] 0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6

[DEBUG] 0x0000000077000000 - 0x00000000cfffffff size 0x59000000 type 0

[DEBUG] 0x00000000d0000000 - 0x00000000dfffffff size 0x10000000 type 1

[DEBUG] 0x00000000e0000000 - 0x00000000ffffffff size 0x20000000 type 0

[DEBUG] 0x0000000100000000 - 0x000000047fbfffff size 0x37fc00000 type 6

[DEBUG] 0x0000007ef8000000 - 0x0000007fffffffff size 0x108000000 type 0

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits

[DEBUG] MTRR: default type WB/UC MTRR counts: 8/8.

[DEBUG] MTRR: UC selected as default type.

[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0

[DEBUG] MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0

[DEBUG] MTRR: 3 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1

[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007e00000000 type 6

[DEBUG] MTRR: 6 base 0x0000000400000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 7 base 0x000000047fc00000 mask 0x0000007fffc00000 type 0

[INFO ] LAPIC 0x6 in X2APIC mode.

[INFO ] LAPIC 0x4 in X2APIC mode.

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] apic_id 0x6: MTRR: Fixed MSR 0x26f 0x0606060606060606

[INFO ] LAPIC 0x2 in X2APIC mode.

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] apic_id 0x4: MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] apic_id 0x6 setup mtrr for CPU physical address size: 39 bits

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606

[DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606

[DEBUG] apic_id 0x4 setup mtrr for CPU physical address size: 39 bits

[DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits

[DEBUG] MTRR: TEMPORARY Physical address space:

[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6

[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0

[DEBUG] 0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6

[DEBUG] 0x0000000077000000 - 0x00000000feffffff size 0x88000000 type 0

[DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5

[DEBUG] 0x0000000100000000 - 0x000000047fbfffff size 0x37fc00000 type 6

[DEBUG] 0x0000007ef8000000 - 0x0000007fffffffff size 0x108000000 type 0

[DEBUG] MTRR: default type WB/UC MTRR counts: 12/8.

[DEBUG] MTRR: UC selected as default type.

[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0

[DEBUG] MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0

[DEBUG] MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5

[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007e00000000 type 6

[DEBUG] MTRR: 6 base 0x0000000400000000 mask 0x0000007f80000000 type 6

[DEBUG] MTRR: 7 base 0x000000047fc00000 mask 0x0000007fffc00000 type 0

[DEBUG] MTRR check

[DEBUG] Fixed MTRRs : Enabled

[DEBUG] Variable MTRRs: Enabled

[DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 11 / 11 ms

[INFO ] Enabling resources...

[DEBUG] PCI: 00:00:00.0 subsystem <- 8086/461c

[DEBUG] PCI: 00:00:00.0 cmd <- 06

[DEBUG] PCI: 00:00:02.0 subsystem <- 8086/46d4

[DEBUG] PCI: 00:00:02.0 cmd <- 03

[DEBUG] PCI: 00:00:14.0 subsystem <- 8086/54ed

[DEBUG] PCI: 00:00:14.0 cmd <- 02

[DEBUG] PCI: 00:00:14.2 subsystem <- 8086/54ef

[DEBUG] PCI: 00:00:14.2 cmd <- 02

[DEBUG] PCI: 00:00:16.0 subsystem <- 8086/54e0

[DEBUG] PCI: 00:00:16.0 cmd <- 02

[DEBUG] PCI: 00:00:17.0 subsystem <- 8086/54d3

[DEBUG] PCI: 00:00:17.0 cmd <- 03

[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013

[DEBUG] PCI: 00:00:1c.0 subsystem <- 8086/54b8

[DEBUG] PCI: 00:00:1c.0 cmd <- 06

[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013

[DEBUG] PCI: 00:00:1c.1 subsystem <- 8086/54b9

[DEBUG] PCI: 00:00:1c.1 cmd <- 06

[DEBUG] PCI: 00:00:1c.2 bridge ctrl <- 0013

[DEBUG] PCI: 00:00:1c.2 subsystem <- 8086/54ba

[DEBUG] PCI: 00:00:1c.2 cmd <- 06

[DEBUG] PCI: 00:00:1c.6 bridge ctrl <- 0013

[DEBUG] PCI: 00:00:1c.6 subsystem <- 8086/54be

[DEBUG] PCI: 00:00:1c.6 cmd <- 06

[DEBUG] PCI: 00:00:1d.0 bridge ctrl <- 0013

[DEBUG] PCI: 00:00:1d.0 subsystem <- 8086/54b0

[DEBUG] PCI: 00:00:1d.0 cmd <- 06

[DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/5481

[DEBUG] PCI: 00:00:1f.0 cmd <- 407

[DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/54c8

[DEBUG] PCI: 00:00:1f.3 cmd <- 02

[DEBUG] PCI: 00:00:1f.4 subsystem <- 8086/54a3

[DEBUG] PCI: 00:00:1f.4 cmd <- 03

[DEBUG] PCI: 00:00:1f.5 subsystem <- 8086/54a4

[DEBUG] PCI: 00:00:1f.5 cmd <- 406

[DEBUG] PCI: 00:01:00.0 cmd <- 02

[DEBUG] PCI: 00:02:00.0 cmd <- 02

[DEBUG] PCI: 00:03:00.0 cmd <- 02

[DEBUG] PCI: 00:04:00.0 cmd <- 02

[DEBUG] PCI: 00:05:00.0 cmd <- 02

[INFO ] done.

[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 6 ms

[DEBUG] ME: Version: 16.50.12.1465

[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 10 / 0 ms

[INFO ] Initializing devices...

[DEBUG] PCI: 00:00:00.0 init

[INFO ] CPU TDP = 6 Watts

[INFO ] CPU PL1 = 6 Watts

[INFO ] CPU PL2 = 25 Watts

[INFO ] CPU PL4 = 78 Watts

[DEBUG] PCI: 00:00:00.0 init finished in 14 msecs

[DEBUG] PCI: 00:00:02.0 init

[INFO ] GMA: Found VBT in CBFS

[INFO ] GMA: Found valid VBT in CBFS

[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

[INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000

[DEBUG] PCI: 00:00:02.0 init finished in 24 msecs

[DEBUG] PCI: 00:00:14.0 init

[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs

[DEBUG] PCI: 00:00:14.2 init

[DEBUG] PCI: 00:00:14.2 init finished in 0 msecs

[DEBUG] PCI: 00:00:16.0 init

[DEBUG] PCI: 00:00:16.0 init finished in 0 msecs

[DEBUG] PCI: 00:00:1c.0 init

[DEBUG] Initializing PCH PCIe bridge.

[DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs

[DEBUG] PCI: 00:00:1c.1 init

[DEBUG] Initializing PCH PCIe bridge.

[DEBUG] PCI: 00:00:1c.1 init finished in 0 msecs

[DEBUG] PCI: 00:00:1c.2 init

[DEBUG] Initializing PCH PCIe bridge.

[DEBUG] PCI: 00:00:1c.2 init finished in 0 msecs

[DEBUG] PCI: 00:00:1c.6 init

[DEBUG] Initializing PCH PCIe bridge.

[DEBUG] PCI: 00:00:1c.6 init finished in 0 msecs

[DEBUG] PCI: 00:00:1d.0 init

[DEBUG] Initializing PCH PCIe bridge.

[DEBUG] PCI: 00:00:1d.0 init finished in 0 msecs

[DEBUG] PCI: 00:00:1f.0 init

[DEBUG] IOAPIC: Initializing IOAPIC at fec00000

[DEBUG] IOAPIC: ID = 0x00

[DEBUG] IOAPIC: 120 interrupts

[DEBUG] IOAPIC: Clearing IOAPIC at fec00000

[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00

[DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs

[DEBUG] PCI: 00:00:1f.2 init

[DEBUG] apm_control: Disabling ACPI.

[DEBUG] APMC done.

[DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs

[DEBUG] PCI: 00:00:1f.3 init

[DEBUG] azalia_audio: base = 0xbe1e8000

[DEBUG] azalia_audio: no codec!

[DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs

[DEBUG] PCI: 00:00:1f.4 init

[DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs

[DEBUG] PCI: 00:01:00.0 init

[DEBUG] PCI: 00:01:00.0 init finished in 0 msecs

[DEBUG] PCI: 00:02:00.0 init

[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs

[DEBUG] PCI: 00:03:00.0 init

[DEBUG] PCI: 00:03:00.0 init finished in 0 msecs

[DEBUG] PCI: 00:04:00.0 init

[DEBUG] PCI: 00:04:00.0 init finished in 0 msecs

[DEBUG] PCI: 00:05:00.0 init

[DEBUG] PCI: 00:05:00.0 init finished in 0 msecs

[DEBUG] PNP: 002e.1 init

[DEBUG] PNP: 002e.1 init finished in 0 msecs

[DEBUG] PNP: 002e.2 init

[DEBUG] PNP: 002e.2 init finished in 0 msecs

[DEBUG] PNP: 002e.3 init

[DEBUG] PNP: 002e.3 init finished in 0 msecs

[DEBUG] PNP: 002e.4 init

[DEBUG] PNP: 002e.4 init finished in 0 msecs

[DEBUG] PNP: 002e.5 init

[DEBUG] PNP: 002e.5 init finished in 0 msecs

[DEBUG] PNP: 002e.6 init

[DEBUG] PNP: 002e.6 init finished in 0 msecs

[DEBUG] PNP: 002e.7 init

[DEBUG] PNP: 002e.7 init finished in 0 msecs

[DEBUG] PNP: 002e.8 init

[DEBUG] PNP: 002e.8 init finished in 0 msecs

[INFO ] Devices initialized

[DEBUG] BS: BS_DEV_INIT run times (exec / console): 5 / 47 ms

[DEBUG] Intel ME Establishment bit not valid.

[DEBUG] TXT_STS_FTIF: PTT present and active

[DEBUG] crb_tis_probe: Intel PTT is active.

[INFO ] Initialized TPM device Intel iTPM revision 0

[INFO ] tlcl2_send_startup: Startup return code is 0x0

[DEBUG] TPM: Write digests cached in TPM log to PCR

[DEBUG] TPM: Write digest for FMAP: FMAP into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: bootblock into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: fallback/romstage into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: fspm.bin into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for MRC: training cache into PCR 3

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: fallback/postcar into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: fallback/ramstage into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: cpu_microcode_blob.bin into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: fsps.bin into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Write digest for CBFS: vbt.bin into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[INFO ] TPM: setup succeeded

[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 17 / 62 ms

[INFO ] Finalize devices...

[DEBUG] PCI: 00:00:02.0 final

[DEBUG] PCI: 00:00:16.0 final

[DEBUG] PCI: 00:00:17.0 final

[DEBUG] PCI: 00:00:1f.2 final

[DEBUG] PCI: 00:00:1f.3 final

[DEBUG] PCI: 00:00:1f.4 final

[INFO ] Devices finalized

[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 7 ms

[DEBUG] ME: HFSTS1 : 0x90000255

[DEBUG] ME: HFSTS2 : 0x39850106

[DEBUG] ME: HFSTS3 : 0x00000020

[DEBUG] ME: HFSTS4 : 0x00004000

[DEBUG] ME: HFSTS5 : 0x00000000

[DEBUG] ME: HFSTS6 : 0x00400002

[DEBUG] ME: Manufacturing Mode : YES

[DEBUG] ME: SPI Protection Mode Enabled : NO

[DEBUG] ME: FW Partition Table : OK

[DEBUG] ME: Bringup Loader Failure : NO

[DEBUG] ME: Firmware Init Complete : YES

[DEBUG] ME: Boot Options Present : NO

[DEBUG] ME: Update In Progress : NO

[DEBUG] ME: D0i3 Support : YES

[DEBUG] ME: Low Power State Enabled : NO

[DEBUG] ME: CPU Replaced : NO

[DEBUG] ME: CPU Replacement Valid : YES

[DEBUG] ME: Current Working State : 5

[DEBUG] ME: Current Operation State : 1

[DEBUG] ME: Current Operation Mode : 0

[DEBUG] ME: Error Code : 0

[DEBUG] ME: FPFs Committed : NO

[DEBUG] ME: Enhanced Debug Mode : NO

[DEBUG] ME: CPU Debug Disabled : YES

[DEBUG] ME: TXT Support : NO

[DEBUG] ME: Manufacturing Vars Locked : NO

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x5bd80 size 0x214c in mcache @0x76c0d1b8

[INFO ] VB2:vb2_digest_init() 8524 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Extending digest for `CBFS: fallback/dsdt.aml` into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Digest of `CBFS: fallback/dsdt.aml` to PCR 2 measured

[DEBUG] Starting cbfs_boot_device

[WARN ] CBFS: 'fallback/slic' not found.

[INFO ] ACPI: Writing ACPI tables at 769dd000.

[DEBUG] ACPI: * FACS

[DEBUG] SCI is IRQ 9, GSI 9

[DEBUG] ACPI: * FACP

[DEBUG] ACPI: added table 1/32, length now 44

[DEBUG] Found 1 CPU(s) with 4/4 physical/logical core(s) each.

[DEBUG] PCI space above 4GB MMIO is at 0x47fc00000, len = 0x7b80400000

[INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in

[INFO ] \_SB.PCI0.PMC: Intel Alderlake at PCI: 00:00:1f.2

[DEBUG] Intel ME Establishment bit not valid.

[DEBUG] TXT_STS_FTIF: PTT present and active

[DEBUG] PPI: Pending OS request: 0x0 (0x0)

[DEBUG] PPI: OS response: CMD 0xedf751f7 = 0x0

[DEBUG] ACPI: * SSDT

[DEBUG] ACPI: added table 2/32, length now 52

[DEBUG] ACPI: * MCFG

[DEBUG] ACPI: added table 3/32, length now 60

[DEBUG] TPM2 log found at 0x76c0a000

[DEBUG] ACPI: * TPM2

[DEBUG] ACPI: added table 4/32, length now 68

[DEBUG] ACPI: * LPIT

[DEBUG] ACPI: added table 5/32, length now 76

[DEBUG] IOAPIC: 120 interrupts

[DEBUG] SCI is IRQ 9, GSI 9

[DEBUG] ACPI: * APIC

[DEBUG] ACPI: added table 6/32, length now 84

[DEBUG] ACPI: * SPCR

[DEBUG] ACPI: added table 7/32, length now 92

[DEBUG] current = 769e1050

[DEBUG] ACPI: * DMAR

[DEBUG] ACPI: added table 8/32, length now 100

[DEBUG] acpi_write_dbg2_pci_uart: Device not found

[DEBUG] ACPI: * HPET

[DEBUG] ACPI: added table 9/32, length now 108

[INFO ] ACPI: done.

[DEBUG] ACPI tables: 16672 bytes.

[DEBUG] smbios_write_tables: 769d5000

[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.12-537-gc9578eac246f-dirty'

[INFO ] Create SMBIOS type 16

[INFO ] Create SMBIOS type 17

[INFO ] Create SMBIOS type 20

[INFO ] MMIO: fed40000 (CRB TPM)

[DEBUG] SMBIOS tables: 835 bytes.

[DEBUG] Writing table forward entry at 0x00000500

[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 793e

[DEBUG] Writing coreboot table at 0x76a01000

[DEBUG] CFR: Written 3716 bytes of CFR structures at 0x76a01018, with CRC32 0x8e6de425

[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES

[DEBUG] 1. 0000000000001000-000000000009ffff: RAM

[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED

[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES

[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED

[DEBUG] 5. 0000000000100000-00000000769d4fff: RAM

[DEBUG] 6. 00000000769d5000-0000000076a8dfff: CONFIGURATION TABLES

[DEBUG] 7. 0000000076a8e000-0000000076bf0fff: RAMSTAGE

[DEBUG] 8. 0000000076bf1000-0000000076ffffff: CONFIGURATION TABLES

[DEBUG] 9. 0000000077000000-00000000803fffff: RESERVED

[DEBUG] 10. 00000000c0000000-00000000cfffffff: RESERVED

[DEBUG] 11. 00000000f8000000-00000000f9ffffff: RESERVED

[DEBUG] 12. 00000000fb000000-00000000fb000fff: RESERVED

[DEBUG] 13. 00000000fc800000-00000000fe7fffff: RESERVED

[DEBUG] 14. 00000000feb00000-00000000feb7ffff: RESERVED

[DEBUG] 15. 00000000fec00000-00000000fecfffff: RESERVED

[DEBUG] 16. 00000000fed40000-00000000fed6ffff: RESERVED

[DEBUG] 17. 00000000fed80000-00000000fed87fff: RESERVED

[DEBUG] 18. 00000000fed90000-00000000fed92fff: RESERVED

[DEBUG] 19. 00000000feda0000-00000000feda1fff: RESERVED

[DEBUG] 20. 00000000fedc0000-00000000feddffff: RESERVED

[DEBUG] 21. 00000000ff000000-00000000ffffffff: RESERVED

[DEBUG] 22. 0000000100000000-000000047fbfffff: RAM

[DEBUG] FMAP: area SMMSTORE found @ c10000 (524288 bytes)

[DEBUG] smm store: 8 # blocks with size 0x10000

[DEBUG] Starting cbfs_boot_device

[DEBUG] Wrote coreboot table at: 0x76a01000, 0x145c bytes, checksum 103b

[DEBUG] coreboot table: 5236 bytes.

[DEBUG] IMD ROOT 0. 0x76fff000 0x00001000

[DEBUG] IMD SMALL 1. 0x76ffe000 0x00001000

[DEBUG] FSP MEMORY 2. 0x76c4e000 0x003b0000

[DEBUG] CONSOLE 3. 0x76c0e000 0x00040000

[DEBUG] RO MCACHE 4. 0x76c0d000 0x0000033c

[DEBUG] TIME STAMP 5. 0x76c0c000 0x00000910

[DEBUG] TPM2 TCGLOG 6. 0x76c0a000 0x000013d8

[DEBUG] MEM INFO 7. 0x76c08000 0x000010c8

[DEBUG] AFTER CAR 8. 0x76bf1000 0x00017000

[DEBUG] RAMSTAGE 9. 0x76a8d000 0x00164000

[DEBUG] REFCODE 10. 0x76a2e000 0x0005f000

[DEBUG] SMM BACKUP 11. 0x76a1e000 0x00010000

[DEBUG] SMM COMBUFFER12. 0x76a0e000 0x00010000

[DEBUG] IGD OPREGION13. 0x76a09000 0x00004400

[DEBUG] COREBOOT 14. 0x76a01000 0x00008000

[DEBUG] ACPI 15. 0x769dd000 0x00024000

[DEBUG] SMBIOS 16. 0x769d5000 0x00008000

[DEBUG] IMD small region:

[DEBUG] IMD ROOT 0. 0x76ffec00 0x00000400

[DEBUG] FSP RUNTIME 1. 0x76ffebe0 0x00000004

[DEBUG] FMAP 2. 0x76ffeac0 0x0000010a

[DEBUG] POWER STATE 3. 0x76ffea60 0x00000044

[DEBUG] FSPM VERSION 4. 0x76ffea40 0x00000004

[DEBUG] ROMSTAGE 5. 0x76ffea20 0x00000004

[DEBUG] ROMSTG STCK 6. 0x76ffe960 0x000000a8

[DEBUG] ACPI GNVS 7. 0x76ffe920 0x00000038

[DEBUG] TPM PPI 8. 0x76ffe7c0 0x0000015a

[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 4 / 64 ms

[DEBUG] Starting cbfs_boot_device

[INFO ] CBFS: Found 'fallback/payload' @0x178800 size 0x1e7b4c in mcache @0x76c0d2cc

[INFO ] VB2:vb2_digest_init() 1997644 bytes, hash algo 2, HW acceleration unsupported

[DEBUG] TPM: Extending digest for `CBFS: fallback/payload` into PCR 2

[INFO ] tlcl2_extend: response is 0x0

[DEBUG] TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured

[DEBUG] Checking segment from ROM address 0xffe0982c

[DEBUG] Checking segment from ROM address 0xffe09848

[DEBUG] Loading segment from ROM address 0xffe0982c

[DEBUG] code (compression=1)

[DEBUG] New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffe09864 filesize 0x1e7b14

[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000001e7b14

[DEBUG] using LZMA

[DEBUG] Loading segment from ROM address 0xffe09848

[DEBUG] Entry Point 0x008022a7

[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 334 / 23 ms

[INFO ] coreboot skipped calling FSP notify phase: 00000040.

[INFO ] coreboot skipped calling FSP notify phase: 000000f0.

[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms

[INFO ] coreboot TPM 2.0 measurements:

[INFO ] PCR-2 02442ad6b9fe8b508f250d28b639f925de1c76e03107ce0bbf4a9c8242ca7981 SHA256 [FMAP: FMAP]

[INFO ] PCR-2 37e5fbbd9a25d33419ba326865d1448e7e42e47117ad65d55515bf003959fe4c SHA256 [CBFS: bootblock]

[INFO ] PCR-2 7828fb4e2f51b7832c0f2be15f72e404c42cd4c61bfb26744c588aa622b9436c SHA256 [CBFS: fallback/romstage]

[INFO ] PCR-2 3bd2b5bcd6607c2f3d8fe46249a9262d8f545cd3ed3d0b1d0f4c46377078d579 SHA256 [CBFS: fspm.bin]

[INFO ] PCR-3 63240d69d8bd289c91c5180f8aad727b649c6def6b0b08a53c086e11ce39ecb8 SHA256 [MRC: training cache]

[INFO ] PCR-2 f39ff03f41aa524e9dd94bcd59379e1dbf54794816107e4ae7b99bb9d7289498 SHA256 [CBFS: fallback/postcar]

[INFO ] PCR-2 07bd13a54bc2d402c4301a19ea26ff153cca8c6e1c716b67fe9267ca85132237 SHA256 [CBFS: fallback/ramstage]

[INFO ] PCR-2 a75d5d37b9bf2c767211fbbcca464004f6688637bf5616569c6df7808bea8d09 SHA256 [CBFS: cpu_microcode_blob.bin]

[INFO ] PCR-2 88c8e3e630d5ecfc036d17ff3ad7adaa3e18f6be2ed7d6d7d3b6195f591aaa68 SHA256 [CBFS: fsps.bin]

[INFO ] PCR-2 80379f8023ee538b9a84adc8c98a06b122e4146017256c689270e0f59a09428e SHA256 [CBFS: vbt.bin]

[INFO ] PCR-2 1b0e5360314e5b1015f826bb47c5d41b993490b6881a2551e0726c50a5a0667c SHA256 [CBFS: fallback/dsdt.aml]

[INFO ] PCR-2 c75d8c2832eb3b2ca575c995e469474b3962605866675a8ef4b114bd1875a868 SHA256 [CBFS: fallback/payload]

[DEBUG] Finalizing chipset.

[DEBUG] apm_control: Finalizing SMM.

[DEBUG] APMC done.

[DEBUG] HSFSTS: 0xF800

[INFO ] HECI: Sending End-of-Post

[INFO ] CSE: EOP requested action: continue boot

[WARN ] HECI: CSE device 16.1 is disabled

[WARN ] HECI: CSE device 16.2 is disabled

[WARN ] HECI: CSE device 16.3 is disabled

[WARN ] HECI: CSE device 16.4 is disabled

[WARN ] HECI: CSE device 16.5 is disabled

[DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 4 / 185 ms

[DEBUG] mp_park_aps done after 0 msecs.

[DEBUG] Jumping to boot code at 0x008022a7(0x76a01000)