|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0xd10000.
|
|
[DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ d10200 (3079680 bytes)
|
|
[INFO ] CBFS: mcache @0xff7e0e00 built for 13 files, used 0x2c8 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0xf980 size 0x19540 in mcache @0xff7e0e8c
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 45 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] Disabling Watchdog reboot... done.
|
|
[DEBUG] SMBus controller enabled
|
|
[DEBUG] Setting up static northbridge registers... done.
|
|
[DEBUG] Started PEG10 link training.
|
|
[DEBUG] Initializing IGD...
|
|
[DEBUG] Back from haswell_early_initialization()
|
|
[DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Xeon(R) CPU E3-1225 v3 @ 3.20GHz
|
|
[DEBUG] AES supported, TXT supported, VT supported
|
|
[DEBUG] PCH type: Q85, device id: 8c4c, rev id 5
|
|
[DEBUG] Starting native platform initialisation
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Checking whether CPU was replaced... replaced
|
|
[DEBUG] HSIO lane owner: 0x05
|
|
[DEBUG] SATA port enables: 0x3f
|
|
[DEBUG] USB2 port 0 => mapped to OC pin 0
|
|
[DEBUG] USB2 port 1 => mapped to OC pin 0
|
|
[DEBUG] USB2 port 2 => mapped to OC pin 0
|
|
[DEBUG] USB2 port 3 => mapped to OC pin 0
|
|
[DEBUG] USB2 port 4 => mapped to OC pin 3
|
|
[DEBUG] USB2 port 5 => mapped to OC pin 3
|
|
[DEBUG] USB2 port 6 => mapped to OC pin 3
|
|
[DEBUG] USB2 port 7 => mapped to OC pin 3
|
|
[DEBUG] USB2 port 8 => mapped to OC pin 5
|
|
[DEBUG] USB2 port 9 => mapped to OC pin 5
|
|
[DEBUG] USB2 port 10 => mapped to OC pin 5
|
|
[DEBUG] USB2 port 11 => mapped to OC pin 5
|
|
[DEBUG] USB2 port 12 => Invalid OC pin 7 for USB2 port 12
|
|
[DEBUG] USB2 port 13 => Invalid OC pin 7 for USB2 port 13
|
|
|
|
[DEBUG] USB3 port 0 => mapped to OC pin 0
|
|
[DEBUG] USB3 port 1 => mapped to OC pin 0
|
|
[DEBUG] USB3 port 2 => disabled
|
|
[DEBUG] USB3 port 3 => disabled
|
|
[DEBUG] USB3 port 4 => mapped to OC pin 5
|
|
[DEBUG] USB3 port 5 => mapped to OC pin 5
|
|
|
|
[DEBUG] Retraining DMI at Gen2 speeds...
|
|
[DEBUG] DMI: Running at Gen1 x4
|
|
[DEBUG] DMI: Running at Gen1 x4
|
|
[INFO ] DMI: Running at Gen2 x4
|
|
[DEBUG] Programming SA DMI VC/TC mappings...
|
|
[DEBUG] Programming PCH DMI VC/TC mappings...
|
|
[DEBUG] Waiting for PCH DMI VC negotiation... done!
|
|
[DEBUG] Waiting for SA DMI VC negotiation... done!
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ d00000 (65536 bytes)
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[NOTE ] CPU was replaced, forcing a cold boot
|
|
[DEBUG] block_cmd_loop: status = c2, len = 256 / 256, loops = 15301
|
|
[DEBUG] Found compatible clock / CAS settings
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 11T
|
|
[DEBUG] MPLL busy... done in 18 us
|
|
[DEBUG] MPLL frequency is set to: 800 MHz (period: 1250000 femtoseconds)
|
|
[DEBUG] Quadrature clock period: 625 picoseconds
|
|
[DEBUG] Selected tCK : 1250 ps
|
|
[DEBUG] Selected tAA : 11T
|
|
[DEBUG] Selected tWR : 12T
|
|
[DEBUG] Selected tRCD : 11T
|
|
[DEBUG] Selected tRRD : 5T
|
|
[DEBUG] Selected tRP : 11T
|
|
[DEBUG] Selected tRAS : 28T
|
|
[DEBUG] Selected tRC : 39T
|
|
[DEBUG] Selected tRFC : 208T
|
|
[DEBUG] Selected tWTR : 6T
|
|
[DEBUG] Selected tRTP : 6T
|
|
[DEBUG] Selected tFAW : 24T
|
|
[DEBUG] Selected tCWL : 8T
|
|
[DEBUG] Selected tCMD : 1T
|
|
[DEBUG] Selected tREFI : 6240T
|
|
[DEBUG] Selected tXP : 5T
|
|
[DEBUG] ME: Requested 32MB UMA
|
|
[DEBUG] Stage 1: Vref offset training
|
|
|
|
|
|
[DEBUG] Hi-Lo (XOR):
|
|
[DEBUG] C1: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
|
|
|
|
[DEBUG] RdVref:
|
|
[DEBUG] C1: -2 -4 -5 -5 -4 -5 -3 -4
|
|
|
|
[DEBUG] Stage 2: Samp offset training
|
|
[DEBUG] Channel 1
|
|
[DEBUG] Byte 0 1 2 3 4 5 6 7
|
|
[DEBUG] BitSAmp c8997868 899978a7 96878998 87888876 a879a88a 87787978 78aaa8a9 99869689
|
|
[DEBUG] Rank 2
|
|
[DEBUG] Steps 1 and 2: Find middle of high region
|
|
[DEBUG] Update RcvEn timing to be in the center of high region
|
|
[DEBUG] C1.R2: Left Right Width Center
|
|
[DEBUG] B0: 336 392 56 364
|
|
[DEBUG] B1: 224 288 64 256
|
|
[DEBUG] B2: 240 296 56 268
|
|
[DEBUG] B3: 248 304 56 276
|
|
[DEBUG] B4: 256 312 56 284
|
|
[DEBUG] B5: 272 328 56 300
|
|
[DEBUG] B6: 304 352 48 328
|
|
[DEBUG] B7: 320 376 56 348
|
|
|
|
[DEBUG] Step 3: Quarter preamble - Walk backwards
|
|
|
|
[DEBUG] C1: Preamble
|
|
[DEBUG] B0: 236
|
|
[DEBUG] B1: 256
|
|
[DEBUG] B2: 268
|
|
[DEBUG] B3: 276
|
|
[DEBUG] B4: 284
|
|
[DEBUG] B5: 300
|
|
[DEBUG] B6: 328
|
|
[DEBUG] B7: 348
|
|
|
|
[DEBUG] Step 4: Add 1 qclk
|
|
|
|
[DEBUG] Step 5: Walk forward to find rising edge
|
|
|
|
[DEBUG] Step 6: center on preamble and clean up rank
|
|
[DEBUG] C1: Preamble increment
|
|
[DEBUG] B0: 269 32
|
|
[DEBUG] B1: 288 31
|
|
[DEBUG] B2: 298 29
|
|
[DEBUG] B3: 307 30
|
|
[DEBUG] B4: 321 36
|
|
[DEBUG] B5: 337 36
|
|
[DEBUG] B6: 361 32
|
|
[DEBUG] B7: 381 32
|
|
|
|
|
|
[DEBUG] Step 7: Sync IO latency across all ranks
|
|
|
|
[DEBUG] Final Receive Enable and IO latency settings:
|
|
[DEBUG] C1.R2: IOLAT = 6 rt_iocomp = 23
|
|
[DEBUG] B0: 269
|
|
[DEBUG] B1: 288
|
|
[DEBUG] B2: 298
|
|
[DEBUG] B3: 307
|
|
[DEBUG] B4: 321
|
|
[DEBUG] B5: 337
|
|
[DEBUG] B6: 361
|
|
[DEBUG] B7: 381
|
|
|
|
[DEBUG] Rank 2
|
|
[DEBUG] C1.R2: Left Right Width Center RxDqsPN
|
|
[DEBUG] B0: -16 31 47 7 39
|
|
[DEBUG] B1: -14 31 45 8 40
|
|
[DEBUG] B2: -16 31 47 7 39
|
|
[DEBUG] B3: -17 31 48 7 39
|
|
[DEBUG] B4: -16 31 47 7 39
|
|
[DEBUG] B5: -15 31 46 8 40
|
|
[DEBUG] B6: -17 31 48 7 39
|
|
[DEBUG] B7: -16 31 47 7 39
|
|
|
|
|
|
[DEBUG] Rank 2
|
|
|
|
[DEBUG] InitSt InitEn CurrSt CurrEn LargSt LargEn
|
|
[DEBUG] C1
|
|
[DEBUG] B0: 190 190 200 264 200 264
|
|
[DEBUG] B1: 190 190 218 280 218 280
|
|
[DEBUG] B2: 190 190 236 300 236 300
|
|
[DEBUG] B3: 192 192 256 320 256 320
|
|
[DEBUG] B4: 192 216 280 344 280 344
|
|
[DEBUG] B5: 192 232 298 360 298 360
|
|
[DEBUG] B6: 192 244 310 372 310 372
|
|
[DEBUG] B7: 192 252 316 380 316 380
|
|
|
|
[DEBUG] C1.R2: LftEdge Width
|
|
[DEBUG] B0: 200 64
|
|
[DEBUG] B1: 218 62
|
|
[DEBUG] B2: 236 64
|
|
[DEBUG] B3: 256 64
|
|
[DEBUG] B4: 280 64
|
|
[DEBUG] B5: 298 62
|
|
[DEBUG] B6: 310 62
|
|
[DEBUG] B7: 316 64
|
|
|
|
[DEBUG] Rank 2
|
|
|
|
|
|
[DEBUG] C1.R2: Offset FinalEdge
|
|
[DEBUG] B0: 0 200
|
|
[DEBUG] B1: 0 218
|
|
[DEBUG] B2: 0 236
|
|
[DEBUG] B3: 0 256
|
|
[DEBUG] B4: 0 280
|
|
[DEBUG] B5: 0 298
|
|
[DEBUG] B6: 0 310
|
|
[DEBUG] B7: 0 316
|
|
|
|
|
|
[DEBUG] Waiting for mc_init_done acknowledgement... DONE!
|
|
[DEBUG] ME: Requested 32MB UMA
|
|
[DEBUG] ME: Sending Init Done with status: 0, UMA base: 0x0fe0
|
|
[NOTE ] ME: Requested BIOS Action: Continue to boot
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : NO
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Normal
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : 0x50
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : NO
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Normal
|
|
[DEBUG] ME: Current Operation State : M0 with UMA
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : uKernel Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Unknown phase: 0x02 state: 0x00
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7e7ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7e7fec00 62 entries.
|
|
[DEBUG] FMAP: area COREBOOT found @ d10200 (3079680 bytes)
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x7ebff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7ebfec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ d00000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[INFO ] Manufacturer: c2
|
|
[INFO ] SF: Detected c2 2018 with sector size 0x1000, total 0x1000000
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x7e800000 0x800000
|
|
[DEBUG] Subregion 0: 0x7e800000 0x300000
|
|
[DEBUG] Subregion 1: 0x7eb00000 0x100000
|
|
[DEBUG] Subregion 2: 0x7ec00000 0x400000
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x4ac00 size 0x6954 in mcache @0xff7e1014
|
|
[DEBUG] Loading module at 0x7e7d0000 with entry 0x7e7d0031. filesize: 0x6488 memsize: 0xc7d8
|
|
[DEBUG] Processing 291 relocs. Offset value of 0x7c7d0000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 932 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] 0x0000000000000d0a: IA32_MTRRCAP: SMRR, WC, FIX, 10 variable MTRRs
|
|
[DEBUG] 0x0000000000000800: IA32_MTRR_DEF_TYPE: E, UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX64K_00000
|
|
[DEBUG] 0x00000000 - 0x0007ffff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_80000
|
|
[DEBUG] 0x00080000 - 0x0009ffff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
|
|
[DEBUG] 0x000a0000 - 0x000bffff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_C0000
|
|
[DEBUG] 0x000c0000 - 0x000c7fff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_C8000
|
|
[DEBUG] 0x000c8000 - 0x000cffff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_D0000
|
|
[DEBUG] 0x000d0000 - 0x000d7fff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_D8000
|
|
[DEBUG] 0x000d8000 - 0x000dffff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E0000
|
|
[DEBUG] 0x000e0000 - 0x000e7fff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E8000
|
|
[DEBUG] 0x000e8000 - 0x000effff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F0000
|
|
[DEBUG] 0x000f0000 - 0x000f7fff: UC
|
|
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F8000
|
|
[DEBUG] 0x000f8000 - 0x000fffff: UC
|
|
[DEBUG] 0x000000007e000006: PHYBASE0: Address = 0x000000007e000000, WB
|
|
[DEBUG] 0x0000007fff000800: PHYMASK0: Length = 0x0000000001000000, Valid
|
|
[DEBUG] 0x00000000ff800005: PHYBASE1: Address = 0x00000000ff800000, WP
|
|
[DEBUG] 0x0000007fff800800: PHYMASK1: Length = 0x0000000000800000, Valid
|
|
[DEBUG] 0x0000000000000000: PHYBASE2
|
|
[DEBUG] 0x0000000000000000: PHYMASK2: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE3
|
|
[DEBUG] 0x0000000000000000: PHYMASK3: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE4
|
|
[DEBUG] 0x0000000000000000: PHYMASK4: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE5
|
|
[DEBUG] 0x0000000000000000: PHYMASK5: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE6
|
|
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE7
|
|
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE8
|
|
[DEBUG] 0x0000000000000000: PHYMASK8: Disabled
|
|
[DEBUG] 0x0000000000000000: PHYBASE9
|
|
[DEBUG] 0x0000000000000000: PHYMASK9: Disabled
|
|
[DEBUG] Normal boot
|
|
[DEBUG] FMAP: area COREBOOT found @ d10200 (3079680 bytes)
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x28f40 size 0x1e283 in mcache @0x7e7fea0c
|
|
[DEBUG] Loading module at 0x7e683000 with entry 0x7e683000. filesize: 0x3c628 memsize: 0x14b7f0
|
|
[DEBUG] Processing 4447 relocs. Offset value of 0x7a683000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 262 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] BS: Entering BS_PRE_DEVICE state.
|
|
[DEBUG] BS: Exiting BS_PRE_DEVICE state.
|
|
[DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 4 ms
|
|
[DEBUG] BS: callback (0x7e6bf5dc) @ src/acpi/gnvs.c:35.
|
|
[DEBUG] BS: callback (0x7e6bf5dc) @ src/acpi/gnvs.c:35 (0 ms).
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_PRE_DEVICE exit times (exec / console): 0 / 17 ms
|
|
[DEBUG] BS: Entering BS_DEV_INIT_CHIPS state.
|
|
[DEBUG] BS: Exiting BS_DEV_INIT_CHIPS state.
|
|
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 5 ms
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_DEV_INIT_CHIPS exit times (exec / console): 0 / 5 ms
|
|
[DEBUG] BS: Entering BS_DEV_ENUMERATE state.
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0c08] enabled
|
|
[DEBUG] PCI: 00:00:01.0 [8086/0c01] enabled
|
|
[DEBUG] PCI: 00:00:02.0 [8086/041a] enabled
|
|
[DEBUG] PCI: 00:00:03.0 [8086/0c0c] enabled
|
|
[DEBUG] PCI: 00:00:14.0 [8086/8c31] enabled
|
|
[DEBUG] PCI: 00:00:16.0 [8086/8c3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.1 [8086/8c3b] disabled No operations
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:00:16.2 [8086/8c3c] disabled No operations
|
|
[DEBUG] PCI: 00:00:16.3 [8086/8c3d] enabled
|
|
[DEBUG] PCI: 00:00:19.0 [8086/153a] enabled
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/8c2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/8c20] enabled
|
|
[DEBUG] PCIe Root Port 1 ASPM is disabled
|
|
[DEBUG] PCI: 00:00:1c.0 [8086/8c10] enabled
|
|
[DEBUG] PCIe Root Port 2 ASPM is disabled
|
|
[DEBUG] PCI: 00:00:1c.1 [8086/8c12] enabled
|
|
[DEBUG] PCI: 00:00:1c.2 [8086/8c14] disabled
|
|
[DEBUG] PCIe Root Port 4 ASPM is disabled
|
|
[DEBUG] PCI: 00:00:1c.3 [8086/8c16] enabled
|
|
[DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2
|
|
[DEBUG] PCIe Root Port 5 ASPM is disabled
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4 [8086/8c18] enabled
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/8c26] enabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/8c4c] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/8c00] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/8c22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/8c08] disabled
|
|
[DEBUG] PCI: 00:00:1f.6: Disabling device
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:00:1c.5
|
|
[WARN ] PCI: 00:00:1c.6
|
|
[WARN ] PCI: 00:00:1c.7
|
|
[WARN ] PCI: 00:00:1f.6
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:00:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1c.3 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 04
|
|
[INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1c.4 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 05
|
|
[INFO ] PCI: 00:00:1c.4: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.4 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[DEBUG] PNP: 002e.ff enabled
|
|
[INFO ] Found TPM 1.2 SLB9635 TT 1.2 (0x000b) by Infineon (0x15d1)
|
|
[DEBUG] PNP: 004e.0 enabled
|
|
[DEBUG] PNP: 002e.ff scanning...
|
|
[DEBUG] PNP: 002e.0 disabled
|
|
[DEBUG] PNP: 002e.1 enabled
|
|
[DEBUG] PNP: 002e.2 disabled
|
|
[DEBUG] PNP: 002e.3 enabled
|
|
[DEBUG] PNP: 002e.4 enabled
|
|
[DEBUG] PNP: 002e.5 enabled
|
|
[DEBUG] PNP: 002e.6 enabled
|
|
[DEBUG] PNP: 002e.7 enabled
|
|
[DEBUG] PNP: 002e.8 enabled
|
|
[DEBUG] PNP: 002e.f enabled
|
|
[DEBUG] PNP: 002e.15 enabled
|
|
[DEBUG] PNP: 002e.1c enabled
|
|
[DEBUG] PNP: 002e.1e enabled
|
|
[DEBUG] scan_bus: bus PNP: 002e.ff finished in 43 msecs
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 66 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 386 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 404 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: Exiting BS_DEV_ENUMERATE state.
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 423 ms
|
|
[DEBUG] BS: callback (0x7e6bed60) @ src/drivers/mrc_cache/mrc_cache.c:767.
|
|
[DEBUG] BS: callback (0x7e6bed60) @ src/drivers/mrc_cache/mrc_cache.c:767 (0 ms).
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 20 ms
|
|
[DEBUG] BS: Entering BS_DEV_RESOURCES state.
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
|
|
[DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
|
|
[DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
|
|
[DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
|
|
[DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] MC MAP: TOM: 0x100000000
|
|
[DEBUG] MC MAP: TOUUD: 0x17ae00000
|
|
[DEBUG] MC MAP: MESEG_BASE: 0xfe000000
|
|
[DEBUG] MC MAP: MESEG_LIMIT: 0x7ffe0fffff
|
|
[DEBUG] MC MAP: REMAP_BASE: 0x100000000
|
|
[DEBUG] MC MAP: REMAP_LIMIT: 0x17adfffff
|
|
[DEBUG] MC MAP: TOLUD: 0x83200000
|
|
[DEBUG] MC MAP: BGSM: 0x7f000000
|
|
[DEBUG] MC MAP: BDSM: 0x7f200000
|
|
[DEBUG] MC MAP: TSEGMB: 0x7e800000
|
|
[DEBUG] MC MAP: GGC: 0x211
|
|
[DEBUG] MC MAP: DPR: 0x7e800001
|
|
[INFO ] Available memory above 4GB: 1966M
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.ff 00 base 0000002e limit 0000002f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.3 60 base 000003f8 limit 000003ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 60 base 00000a00 limit 00000a07 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 62 base 00000a10 limit 00000a1f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.6 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.6 62 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.7 60 base 00000a20 limit 00000a3f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.8 60 base 00000800 limit 000008ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.15 60 base 00000a80 limit 00000a8f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.15 62 base 00000a90 limit 00000a9f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1c 60 base 00000a40 limit 00000a5f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1e 60 base 00000a60 limit 00000a7f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: f000, Tag: 100
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io
|
|
[DEBUG] PCI: 00:00:16.3 10 * [0xff78 - 0xff7f] limit: ff7f io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xff70 - 0xff77] limit: ff77 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xff68 - 0xff6f] limit: ff6f io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xff64 - 0xff67] limit: ff67 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xff60 - 0xff63] limit: ff63 io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 7e800000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 00100000 limit 7e7fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 7e800000 limit 7effffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 7f000000 limit 831fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 17adfffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 004e.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 83200000, Size: 6ce00000, Tag: 200
|
|
[INFO ] * Base: 17ae00000, Size: 7e85200000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
|
|
[DEBUG] PCI: 00:00:19.0 10 * [0xdfbe0000 - 0xdfbfffff] limit: dfbfffff mem
|
|
[DEBUG] PCI: 00:00:14.0 10 * [0xdfbd0000 - 0xdfbdffff] limit: dfbdffff mem
|
|
[DEBUG] PCI: 00:00:03.0 10 * [0xdfbcc000 - 0xdfbcffff] limit: dfbcffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xdfbc8000 - 0xdfbcbfff] limit: dfbcbfff mem
|
|
[DEBUG] PCI: 00:00:16.3 14 * [0xdfbc7000 - 0xdfbc7fff] limit: dfbc7fff mem
|
|
[DEBUG] PCI: 00:00:19.0 14 * [0xdfbc6000 - 0xdfbc6fff] limit: dfbc6fff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0xdfbc5000 - 0xdfbc57ff] limit: dfbc57ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0xdfbc4000 - 0xdfbc43ff] limit: dfbc43ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0xdfbc3000 - 0xdfbc33ff] limit: dfbc33ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0xdfbc2000 - 0xdfbc20ff] limit: dfbc20ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0xdfbc1000 - 0xdfbc100f] limit: dfbc100f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 7e800000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:00:03.0 10 <- [0x00000000dfbcc000 - 0x00000000dfbcffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:14.0 10 <- [0x00000000dfbd0000 - 0x00000000dfbdffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000dfbc1000 - 0x00000000dfbc100f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:16.3 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:16.3 14 <- [0x00000000dfbc7000 - 0x00000000dfbc7fff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000dfbe0000 - 0x00000000dfbfffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000dfbc6000 - 0x00000000dfbc6fff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000dfbc4000 - 0x00000000dfbc43ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000dfbc8000 - 0x00000000dfbcbfff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:00:1c.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:00:1c.3 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 04 io
|
|
[DEBUG] PCI: 00:00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
|
|
[DEBUG] PCI: 00:00:1c.3 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 mem
|
|
[DEBUG] PCI: 00:00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 05 io
|
|
[DEBUG] PCI: 00:00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 prefmem
|
|
[DEBUG] PCI: 00:00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000dfbc3000 - 0x00000000dfbc33ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PNP: 002e.1 14 <- [0x000000000000009c - 0x000000000000009b] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1c <- [0x00000000000000a8 - 0x00000000000000a7] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1d <- [0x0000000000000008 - 0x0000000000000007] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 22 <- [0x000000000000003f - 0x000000000000003e] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1a <- [0x00000000000000b0 - 0x00000000000000af] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1b <- [0x000000000000001e - 0x000000000000001d] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 27 <- [0x0000000000000008 - 0x0000000000000007] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 2a <- [0x0000000000000020 - 0x000000000000001f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 2d <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.1 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 74 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.3 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.3 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.4 60 <- [0x0000000000000a00 - 0x0000000000000a07] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.4 62 <- [0x0000000000000a10 - 0x0000000000000a1f] size 0x00000010 gran 0x04 io
|
|
[NOTE ] PNP: 002e.4 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.5 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.6 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.6 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.6 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.6 f0 <- [0x0000000000000040 - 0x000000000000003f] size 0x00000000 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.7 60 <- [0x0000000000000a20 - 0x0000000000000a3f] size 0x00000020 gran 0x05 io
|
|
[NOTE ] PNP: 002e.7 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.8 60 <- [0x0000000000000800 - 0x00000000000008ff] size 0x00000100 gran 0x08 io
|
|
[DEBUG] PNP: 002e.8 f0 <- [0x0000000000000020 - 0x0000000000000020] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f1 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f2 <- [0x0000000000000040 - 0x0000000000000040] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f3 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f4 <- [0x0000000000000066 - 0x0000000000000066] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f5 <- [0x0000000000000067 - 0x0000000000000067] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f6 <- [0x0000000000000066 - 0x0000000000000066] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f7 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.8 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.f f1 <- [0x0000000000000097 - 0x0000000000000097] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f f2 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f f5 <- [0x0000000000000008 - 0x0000000000000008] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f fe <- [0x0000000000000080 - 0x0000000000000080] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.f f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fd irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.15 60 <- [0x0000000000000a80 - 0x0000000000000a8f] size 0x00000010 gran 0x04 io
|
|
[DEBUG] PNP: 002e.15 62 <- [0x0000000000000a90 - 0x0000000000000a9f] size 0x00000010 gran 0x04 io
|
|
[NOTE ] PNP: 002e.15 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.1c 60 <- [0x0000000000000a40 - 0x0000000000000a5f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PNP: 002e.1e 60 <- [0x0000000000000a60 - 0x0000000000000a7f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PNP: 002e.1e f4 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.1e f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.ff 00 <- [0x000000000000002e - 0x000000000000002f] size 0x00000002 gran 0x00 io
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff64 - 0x000000000000ff67] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff68 - 0x000000000000ff6f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff60 - 0x000000000000ff63] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000dfbc5000 - 0x00000000dfbc57ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000dfbc2000 - 0x00000000dfbc20ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: Exiting BS_DEV_RESOURCES state.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1828 ms
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_DEV_RESOURCES exit times (exec / console): 0 / 5 ms
|
|
[DEBUG] BS: Entering BS_DEV_ENABLE state.
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:01.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:01.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:03.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:03.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:14.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:16.3 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:16.3 cmd <- 03
|
|
[DEBUG] PCI: 00:00:19.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.1 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1c.1 cmd <- 00
|
|
[DEBUG] PCI: 00:00:1c.3 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.3 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1c.3 cmd <- 00
|
|
[DEBUG] PCI: 00:00:1c.4 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.4 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1c.4 cmd <- 00
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 103c/18e7
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[INFO ] done.
|
|
[DEBUG] BS: Exiting BS_DEV_ENABLE state.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 191 ms
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_DEV_ENABLE exit times (exec / console): 0 / 5 ms
|
|
[DEBUG] BS: Entering BS_DEV_INIT state.
|
|
[DEBUG] BS: callback (0x7e6bf52c) @ src/arch/x86/ebda.c:59.
|
|
[DEBUG] BS: callback (0x7e6bf52c) @ src/arch/x86/ebda.c:59 (0 ms).
|
|
[DEBUG] BS: callback (0x7e6bc7b8) @ src/southbridge/intel/common/spi.c:354.
|
|
[DEBUG] BS: callback (0x7e6bc7b8) @ src/southbridge/intel/common/spi.c:354 (0 ms).
|
|
[DEBUG] BS: BS_DEV_INIT entry times (exec / console): 0 / 28 ms
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007effffff size 0x7ef40000 type 6
|
|
[DEBUG] 0x000000007f000000 - 0x00000000dfffffff size 0x61000000 type 0
|
|
[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000017adfffff size 0x7ae00000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 5/4.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x000000007f000000 mask 0x0000007fff000000 type 0
|
|
[DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1
|
|
[DEBUG] MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] Initializing VR config.
|
|
[DEBUG] CPU has 4 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] microcode: sig=0x306c3 pf=0x2 revision=0x28
|
|
[DEBUG] FMAP: area COREBOOT found @ d10200 (3079680 bytes)
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7e7fe94c
|
|
[INFO ] CPU: Intel(R) Xeon(R) CPU E3-1225 v3 @ 3.20GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x4 in XAPIC mode.
|
|
[INFO ] LAPIC 0x6 in XAPIC mode.
|
|
[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000028
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 3 apic_id 6, MCU rev: 0x00000028
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000028
|
|
[DEBUG] done.
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7e801000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7e6a4235
|
|
[DEBUG] Installing permanent SMM handler to 0x7e800000
|
|
[DEBUG] HANDLER [0x7eafd000-0x7eaff987]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x7eafcc00-0x7eafcfff]
|
|
[DEBUG] stub0 [0x7eaf5000-0x7eaf519f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x7eafc800-0x7eafcbff]
|
|
[DEBUG] stub1 [0x7eaf4c00-0x7eaf4d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x7eafc400-0x7eafc7ff]
|
|
[DEBUG] stub2 [0x7eaf4800-0x7eaf499f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x7eafc000-0x7eafc3ff]
|
|
[DEBUG] stub3 [0x7eaf4400-0x7eaf459f]
|
|
|
|
[DEBUG] stacks [0x7e800000-0x7e800fff]
|
|
[DEBUG] Loading module at 0x7eafd000 with entry 0x7eafdeb3. filesize: 0x2958 memsize: 0x2988
|
|
[DEBUG] Processing 249 relocs. Offset value of 0x7eafd000
|
|
[DEBUG] Loading module at 0x7eaf5000 with entry 0x7eaf5000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x7eaf5000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7e801000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 7eaf4c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 7eaf4800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 7eaf4400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 7eaf5000. Will call 0x7eafdeb3
|
|
[DEBUG] SMI_STS: PM1
|
|
[DEBUG] WAK PWRBTN TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7eaed000, cpu = 0
|
|
[DEBUG] In relocation handler: CPU 0
|
|
[DEBUG] New SMBASE=0x7eaed000 IEDBASE=0x7ec00000
|
|
[DEBUG] Writing SMRR. base = 0x7e800006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7eaec400, cpu = 3
|
|
[DEBUG] In relocation handler: CPU 3
|
|
[DEBUG] New SMBASE=0x7eaec400 IEDBASE=0x7ec00000
|
|
[DEBUG] Writing SMRR. base = 0x7e800006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7eaecc00, cpu = 1
|
|
[DEBUG] In relocation handler: CPU 1
|
|
[DEBUG] New SMBASE=0x7eaecc00 IEDBASE=0x7ec00000
|
|
[DEBUG] Writing SMRR. base = 0x7e800006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7eaec800, cpu = 2
|
|
[DEBUG] In relocation handler: CPU 2
|
|
[DEBUG] New SMBASE=0x7eaec800 IEDBASE=0x7ec00000
|
|
[DEBUG] Writing SMRR. base = 0x7e800006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306c3
|
|
[DEBUG] CPU: family 06, model 3c, stepping 03
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306c3
|
|
[DEBUG] CPU: family 06, model 3c, stepping 03
|
|
[INFO ] Initializing CPU #2
|
|
[DEBUG] CPU: vendor Intel device 306c3
|
|
[DEBUG] CPU: family 06, model 3c, stepping 03
|
|
[DEBUG] CPU: vendor Intel device 306c3
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] CPU: family 06, model 3c, stepping 03
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #1 initialized
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #3 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] CPU #2 initialized
|
|
[INFO ] bsp_do_flight_plan done after 425 msecs.
|
|
[DEBUG] CPU: frequency set to 3600
|
|
[DEBUG] Enabling SMIs.
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 752 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling "device 4".
|
|
[DEBUG] Disabling "device 7".
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 84 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 20 msecs
|
|
[DEBUG] PCI: 00:00:01.0 init
|
|
[DEBUG] PCI: 00:00:01.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x4a640 size 0x570 in mcache @0x7e7feb04
|
|
[INFO ] Found a VBT of 6144 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
|
|
[INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xe0000000
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 59 msecs
|
|
[DEBUG] PCI: 00:00:03.0 init
|
|
[DEBUG] Mini-HD: base = 0xdfbcc000
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x00000000
|
|
[DEBUG] azalia_audio: - no verb!
|
|
[DEBUG] PCI: 00:00:03.0 init finished in 21 msecs
|
|
[DEBUG] PCI: 00:00:14.0 init
|
|
[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : YES
|
|
[DEBUG] ME: Manufacturing Mode : NO
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Normal
|
|
[DEBUG] ME: Current Operation State : M0 with UMA
|
|
[DEBUG] ME: Current Operation Mode : Normal
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : Host Communication
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Host communication established
|
|
[NOTE ] ME: BIOS path: Normal
|
|
[DEBUG] ME: Extend SHA-256: 289ab4695550a481815aed65f4426d44ddaf3a694b6784eca9e47755f06bcd28
|
|
[INFO ] ME MBP: Header: items: 10, size dw: 36
|
|
[ERROR] ME MBP: unknown item 0x20104 @ dw offset 0x6
|
|
[DEBUG] ME: found version 9.1.20.1035
|
|
[DEBUG] ME: Wake Event to ME Reset: 0 ms
|
|
[DEBUG] ME: ME Reset to Platform Reset: 0 ms
|
|
[DEBUG] ME: Platform Reset to CPU Reset: 369 ms
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 106 msecs
|
|
[DEBUG] PCI: 00:00:16.3 init
|
|
[DEBUG] PCI: 00:00:16.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:19.0 init
|
|
[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0xdfbc8000
|
|
[DEBUG] Azalia: codec_mask = 01
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0221
|
|
[DEBUG] azalia_audio: - verb size: 44
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 30 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.1 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1c.3 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.3 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1c.4 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.4 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] LynxPoint H PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 smm starting (log level: 7)...
|
|
[DEBUG] SMI_STS: PM1 APM
|
|
[DEBUG] SMI#: Disabling ACPI.
|
|
[DEBUG] TMROF [DEBUG] APMC done.
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 67 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0xdfbc5000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 10 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1 init
|
|
[DEBUG] PNP: 002e.1 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.3 init
|
|
[DEBUG] PNP: 002e.3 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.4 init
|
|
[DEBUG] PNP: 002e.4 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.5 init
|
|
[DEBUG] PNP: 002e.5 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.6 init
|
|
[DEBUG] PNP: 002e.6 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.7 init
|
|
[DEBUG] PNP: 002e.7 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.8 init
|
|
[INFO ] NPCD378: PSU fan PWM 0x77
|
|
[DEBUG] PNP: 002e.8 init finished in 3 msecs
|
|
[DEBUG] PNP: 002e.f init
|
|
[DEBUG] PNP: 002e.f init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.15 init
|
|
[DEBUG] PNP: 002e.15 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1c init
|
|
[DEBUG] PNP: 002e.1c init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1e init
|
|
[DEBUG] PNP: 002e.1e init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: Exiting BS_DEV_INIT state.
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 262 / 1096 ms
|
|
[DEBUG] BS: callback (0x7e6becac) @ src/drivers/tpm/tpm.c:13.
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] BS: callback (0x7e6becac) @ src/drivers/tpm/tpm.c:13 (39 ms).
|
|
[DEBUG] BS: callback (0x7e6bc7d0) @ src/security/memory/memory_clear.c:142.
|
|
[DEBUG] BS: callback (0x7e6bc7d0) @ src/security/memory/memory_clear.c:142 (0 ms).
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 10 / 63 ms
|
|
[DEBUG] BS: Entering BS_POST_DEVICE state.
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:00.0 final
|
|
[DEBUG] PCI: 00:00:16.0 final
|
|
[INFO ] ME: MBP cleared
|
|
[NOTE ] ME: mkhi_end_of_post
|
|
[INFO ] ME: END OF POST message successful (1)
|
|
[DEBUG] PCI: 00:00:1b.0 final
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[INFO ] Manufacturer: c2
|
|
[INFO ] SF: Detected c2 2018 with sector size 0x1000, total 0x1000000
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 smm starting (log level: 7)...
|
|
[DEBUG] SMI_STS: APM
|
|
[DEBUG] SMI#: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[DEBUG] BS: Exiting BS_POST_DEVICE state.
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 25 / 52 ms
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
|
|
[DEBUG] BS: Entering BS_OS_RESUME_CHECK state.
|
|
[DEBUG] BS: Exiting BS_OS_RESUME_CHECK state.
|
|
[DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 5 ms
|
|
[DEBUG] ----------------------------------------
|
|
[DEBUG] BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 5 ms
|
|
[DEBUG] BS: Entering BS_WRITE_TABLES state.
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x48400 size 0x21f5 in mcache @0x7e7fead8
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7e642000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] PSS: 3201MHz power 84000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 3200MHz power 84000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2800MHz power 70119 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 57393 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 45570 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 34692 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 24727 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 800MHz power 15645 control 0x800 status 0x800
|
|
[DEBUG] PSS: 3201MHz power 84000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 3200MHz power 84000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2800MHz power 70119 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 57393 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 45570 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 34692 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 24727 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 800MHz power 15645 control 0x800 status 0x800
|
|
[DEBUG] PSS: 3201MHz power 84000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 3200MHz power 84000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2800MHz power 70119 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 57393 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 45570 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 34692 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 24727 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 800MHz power 15645 control 0x800 status 0x800
|
|
[DEBUG] PSS: 3201MHz power 84000 control 0x2400 status 0x2400
|
|
[DEBUG] PSS: 3200MHz power 84000 control 0x2000 status 0x2000
|
|
[DEBUG] PSS: 2800MHz power 70119 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2400MHz power 57393 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2000MHz power 45570 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1600MHz power 34692 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1200MHz power 24727 control 0xc00 status 0xc00
|
|
[DEBUG] PSS: 800MHz power 15645 control 0x800 status 0x800
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x17ae00000, len = 0x7e85200000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0: PNP: 002e.ff
|
|
[DEBUG] PPI: Pending OS request: 0xe3f79829 (0x19ef5e18)
|
|
[DEBUG] PPI: OS response: CMD 0x973dece3 = 0x6f4687a5
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 004e.0
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L010: PNP: 002e.1
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L030: PNP: 002e.3
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L040: PNP: 002e.4
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L050: PNP: 002e.5
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L060: PNP: 002e.6
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L070: PNP: 002e.7
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L080: PNP: 002e.8
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L0F0: PNP: 002e.f
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L150: PNP: 002e.15
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L1C0: PNP: 002e.1c
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L1E0: PNP: 002e.1e
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] TCPA log created at 0x7e632000
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] ACPI: * SPCR
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[DEBUG] current = 7e646e70
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 7/32, length now 92
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 8/32, length now 100
|
|
[DEBUG] current = 7e646f70
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 20336 bytes.
|
|
[DEBUG] smbios_write_tables: 7e62a000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '25.06-77-g812d0e2f626d-dirty'
|
|
[DEBUG] SMBIOS tables: 619 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 2178
|
|
[DEBUG] Writing coreboot table at 0x7e666000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007e629fff: RAM
|
|
[DEBUG] 6. 000000007e62a000-000000007e682fff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007e683000-000000007e7cefff: RAMSTAGE
|
|
[DEBUG] 8. 000000007e7cf000-000000007e7fffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 000000007e800000-00000000831fffff: RESERVED
|
|
[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 11. 00000000fed10000-00000000fed19fff: RESERVED
|
|
[DEBUG] 12. 00000000fed40000-00000000fed44fff: RESERVED
|
|
[DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED
|
|
[DEBUG] 14. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 15. 0000000100000000-000000017adfffff: RAM
|
|
[DEBUG] Wrote coreboot table at: 0x7e666000, 0x464 bytes, checksum 4bfc
|
|
[DEBUG] coreboot table: 1148 bytes.
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 smm starting (log level: 7)...
|
|
[DEBUG] SMI_STS: PM1 APM
|
|
[DEBUG] SMI#: Unknown APMC 0xcd.
|
|
[DEBUG] TMROF EFI stub: Loaded initrd from LINUX_EFI_INITRD_MEDIA_GUID device path
|
|
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 smm starting (log level: 7)...
|
|
[DEBUG] SMI_STS: PM1 APM
|
|
[DEBUG] SMI#: Enabling ACPI.
|
|
[DEBUG] TMROF
|
|
|
|
[NOTE ] coreboot-25.06-77-g812d0e2f626d-dirty Fri Jul 04 13:18:33 UTC 2025 x86_32 smm starting (log level: 7)...
|
|
[DEBUG] SMI_STS: SLP_SMI
|
|
[DEBUG] SMI#: Entering S5 (Soft Power off)
|