|
*** Pre-CBMEM romstage console overflowed, log truncated! ***
|
|
EF100_CFG value: 0x7
|
|
[DEBUG] Trying CAS 11, tCK 320.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 800 MHz
|
|
[DEBUG] Selected CAS latency : 11T
|
|
[DEBUG] MPLL busy... done in 70 us
|
|
[DEBUG] MPLL frequency is set at : 800 MHz
|
|
[DEBUG] Selected CWL latency : 8T
|
|
[DEBUG] Selected tRCD : 11T
|
|
[DEBUG] Selected tRP : 11T
|
|
[DEBUG] Selected tRAS : 28T
|
|
[DEBUG] Selected tWR : 12T
|
|
[DEBUG] Selected tFAW : 24T
|
|
[DEBUG] Selected tRRD : 5T
|
|
[DEBUG] Selected tRTP : 6T
|
|
[DEBUG] Selected tWTR : 6T
|
|
[DEBUG] Selected tRFC : 128T
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 1
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7d600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 1
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[WARN ] Logic delay 2 greater than 1: 0 0
|
|
[WARN ] Logic delay 2 greater than 1: 0 1
|
|
[DEBUG] t123: 1767, 6000, 6120
|
|
[NOTE ] ME: Wrong mode : 2
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: ME is reporting as disabled, so not waiting for a response.
|
|
[NOTE ] ME: FWS2: 0x100a0140
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x0
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x1
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x1
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0xa
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: No DID Ack received
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1596 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00620010):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 4096 MB width x8 dual rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] memcfg channel[1] config (00000000):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode off
|
|
[DEBUG] rank interleave off
|
|
[DEBUG] DIMMA 0 MB width x8 single rank, selected
|
|
[DEBUG] DIMMB 0 MB width x8 single rank
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] FMAP: area COREBOOT found @ 850200 (3866112 bytes)
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] SF: Successfully written 2 bytes @ 0x800000
|
|
[DEBUG] SF: Successfully written 2 bytes @ 0x800002
|
|
[DEBUG] SF: Successfully written 20 bytes @ 0x800050
|
|
[DEBUG] SF: Successfully written 1588 bytes @ 0x800064
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffdc000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x4b0c0 size 0x5b80 in mcache @0xfeff100c
|
|
[DEBUG] Loading module at 0x7ffd0000 with entry 0x7ffd0031. filesize: 0x57c8 memsize: 0xbb18
|
|
[DEBUG] Processing 222 relocs. Offset value of 0x7dfd0000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 2 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.03-dirty Fri Mar 28 23:23:34 UTC 2025 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] FMAP: area COREBOOT found @ 850200 (3866112 bytes)
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x1d0c0 size 0x285c6 in mcache @0x7fffe9fc
|
|
[DEBUG] Loading module at 0x7fe64000 with entry 0x7fe64000. filesize: 0x570a0 memsize: 0x16a2b0
|
|
[DEBUG] Processing 6686 relocs. Offset value of 0x7be64000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
|
|
|
|
|
|
[NOTE ] coreboot-25.03-dirty Fri Mar 28 23:23:34 UTC 2025 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0154] enabled
|
|
[DEBUG] PCI: 00:00:01.0 [8086/0151] disabled
|
|
[DEBUG] PCI: 00:00:02.0 [8086/0166] enabled
|
|
[DEBUG] PCI: 00:00:04.0 [8086/0153] disabled
|
|
[DEBUG] PCI: 00:00:14.0 [8086/1e31] enabled
|
|
[DEBUG] PCI: 00:00:16.0 [8086/1e3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[DEBUG] PCI: 00:00:16.3: Disabling device
|
|
[DEBUG] PCI: 00:00:19.0 [8086/1502] enabled
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/1e2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/1e20] enabled
|
|
[DEBUG] PCI: 00:00:1c.0: Found a downstream device
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:00:1c.0 [8086/1e10] enabled
|
|
[DEBUG] PCI: 00:00:1c.1: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.1 [8086/1e12] enabled
|
|
[DEBUG] PCI: 00:00:1c.2: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.2 [8086/1e14] enabled
|
|
[DEBUG] PCI: 00:00:1c.3: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3 [8086/1e16] disabled
|
|
[DEBUG] PCI: 00:00:1c.4: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.4: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4: check set enabled
|
|
[DEBUG] PCI: 00:00:1c.5: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.6: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.7: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.7: Disabling device
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/1e26] enabled
|
|
[DEBUG] PCI: 00:00:1e.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/2448] disabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/1e55] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/1e01] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/1e22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/1e09] disabled No operations
|
|
[DEBUG] PCI: 00:00:1f.6 [8086/1e24] enabled
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:00:01.1
|
|
[WARN ] PCI: 00:00:01.2
|
|
[WARN ] PCI: 00:00:06.0
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[DEBUG] PCI: 00:01:00.0 [1180/e823] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L0s and L1
|
|
[DEBUG] PCI: 00:01:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[DEBUG] PCI: 00:02:00.0 [8086/0085] enabled
|
|
[INFO ] Enabling Common Clock Configuration
|
|
[INFO ] ASPM: Enabled L1
|
|
[DEBUG] PCI: 00:02:00.0: No LTR support
|
|
[INFO ] PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.1 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.2 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 03
|
|
[INFO ] PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1c.2 finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[INFO ] PMH7: ID 05 Revision 12
|
|
[DEBUG] PNP: 00ff.1 enabled
|
|
[INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a)
|
|
[DEBUG] PNP: 0c31.0 enabled
|
|
[INFO ] H8: EC Firmware ID G2HT33WW-3.22, Version 2.01B
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[DEBUG] PNP: 00ff.2 enabled
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 3 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] I2C: 01:54 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:55 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:56 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:57 enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5c enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5d enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5e enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->I2C: 01:5f enabled
|
|
[DEBUG] bus: PCI: 00:00:1f.3->scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 4 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 4 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 0 ms
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x17d600000 TOLUD 0x82a00000 TOM 0x100000000
|
|
[DEBUG] MEBASE 0x7ffff00000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 2006M
|
|
[ERROR] PNP: 00ff.1 missing read_resources
|
|
[ERROR] PNP: 00ff.2 missing read_resources
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0xff] mem
|
|
[DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0x0 - 0x1fff] mem
|
|
[DEBUG] PCI: 00:00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] NONE 18 * [0x0 - 0x7ff] io
|
|
[DEBUG] PCI: 00:00:1c.2 io: size: 1000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] NONE 10 * [0x0 - 0x7fffff] mem
|
|
[DEBUG] PCI: 00:00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
|
|
[INFO ] * Base: 15f0, Size: 10, Tag: 100
|
|
[INFO ] * Base: 167c, Size: e984, Tag: 100
|
|
[DEBUG] PCI: 00:00:1c.2 1c * [0x2000 - 0x2fff] limit: 2fff io
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
|
|
[DEBUG] PCI: 00:00:19.0 18 * [0x1040 - 0x105f] limit: 105f io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 100000000 limit 17d5fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 80000000 limit 829fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
|
|
[INFO ] * Base: 17d600000, Size: e82a00000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem
|
|
[DEBUG] PCI: 00:00:1c.2 24 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 20 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[DEBUG] PCI: 00:00:1c.0 20 * [0x82a00000 - 0x82afffff] limit: 82afffff mem
|
|
[DEBUG] PCI: 00:00:1c.1 20 * [0x82b00000 - 0x82bfffff] limit: 82bfffff mem
|
|
[DEBUG] PCI: 00:00:19.0 10 * [0x83800000 - 0x8381ffff] limit: 8381ffff mem
|
|
[DEBUG] PCI: 00:00:14.0 10 * [0x83820000 - 0x8382ffff] limit: 8382ffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0x83830000 - 0x83833fff] limit: 83833fff mem
|
|
[DEBUG] PCI: 00:00:19.0 14 * [0x83834000 - 0x83834fff] limit: 83834fff mem
|
|
[DEBUG] PCI: 00:00:1f.6 10 * [0x83835000 - 0x83835fff] limit: 83835fff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0x83836000 - 0x838367ff] limit: 838367ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0x83837000 - 0x838373ff] limit: 838373ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0x83838000 - 0x838383ff] limit: 838383ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0x83839000 - 0x838390ff] limit: 838390ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0x8383a000 - 0x8383a00f] limit: 8383a00f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:01:00.0 10 * [0x82a00000 - 0x82a000ff] limit: 82a000ff mem
|
|
[DEBUG] PCI: 00:02:00.0 10 * [0x82b00000 - 0x82b01fff] limit: 82b01fff mem
|
|
[DEBUG] NONE 18 * [0x2000 - 0x27ff] limit: 27ff io
|
|
[DEBUG] NONE 14 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem
|
|
[DEBUG] NONE 10 * [0x83000000 - 0x837fffff] limit: 837fffff mem
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:00:14.0 10 <- [0x0000000083820000 - 0x000000008382ffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x000000008383a000 - 0x000000008383a00f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:19.0 10 <- [0x0000000083800000 - 0x000000008381ffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:00:19.0 14 <- [0x0000000083834000 - 0x0000000083834fff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 18 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x0000000083837000 - 0x00000000838373ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x0000000083830000 - 0x0000000083833fff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:1c.0 20 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:01:00.0 10 <- [0x0000000082a00000 - 0x0000000082a000ff] size 0x00000100 gran 0x08 mem
|
|
[DEBUG] PCI: 00:00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1c.1 20 <- [0x0000000082b00000 - 0x0000000082bfffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PCI: 00:02:00.0 10 <- [0x0000000082b00000 - 0x0000000082b01fff] size 0x00002000 gran 0x0d mem64
|
|
[DEBUG] PCI: 00:00:1c.2 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c seg 00 bus 03 io
|
|
[DEBUG] PCI: 00:00:1c.2 24 <- [0x00000000a0000000 - 0x00000000afffffff] size 0x10000000 gran 0x14 seg 00 bus 03 prefmem
|
|
[DEBUG] PCI: 00:00:1c.2 20 <- [0x0000000083000000 - 0x00000000837fffff] size 0x00800000 gran 0x14 seg 00 bus 03 mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x0000000083838000 - 0x00000000838383ff] size 0x00000400 gran 0x0a mem
|
|
[ERROR] PNP: 00ff.1 missing set_resources
|
|
[ERROR] PNP: 00ff.2 missing set_resources
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x0000000000001080 - 0x0000000000001087] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x0000000000001090 - 0x0000000000001093] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x0000000000001088 - 0x000000000000108f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x0000000000001094 - 0x0000000000001097] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x0000000000001060 - 0x000000000000107f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x0000000083836000 - 0x00000000838367ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x0000000083839000 - 0x00000000838390ff] size 0x00000100 gran 0x08 mem64
|
|
[DEBUG] PCI: 00:00:1f.6 10 <- [0x0000000083835000 - 0x0000000083835fff] size 0x00001000 gran 0x0c mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 8086/0154
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 8086/0166
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:14.0 subsystem <- 8086/1e31
|
|
[DEBUG] PCI: 00:00:14.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 8086/1e3a
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:19.0 subsystem <- 17aa/21f3
|
|
[DEBUG] PCI: 00:00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 8086/1e2d
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 8086/1e20
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.0 subsystem <- 8086/1e10
|
|
[DEBUG] PCI: 00:00:1c.0 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.1 subsystem <- 8086/1e12
|
|
[DEBUG] PCI: 00:00:1c.1 cmd <- 106
|
|
[DEBUG] PCI: 00:00:1c.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1c.2 subsystem <- 8086/1e14
|
|
[DEBUG] PCI: 00:00:1c.2 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 8086/1e26
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/1e55
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 8086/1e03
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/1e22
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1f.6 subsystem <- 8086/1e24
|
|
[DEBUG] PCI: 00:00:1f.6 cmd <- 02
|
|
[DEBUG] PCI: 00:01:00.0 subsystem <- 1180/e823
|
|
[DEBUG] PCI: 00:01:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:02:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000017d5fffff size 0x7d600000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/3.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21
|
|
[DEBUG] FMAP: area COREBOOT found @ 850200 (3866112 bytes)
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7fffe96c
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[DEBUG] done.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021
|
|
[INFO ] LAPIC 0x3 in XAPIC mode.
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] AP: slot 2 apic_id 3, MCU rev: 0x00000021
|
|
[INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000021
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fe9656c
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fb000-0x802ff287]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fac00-0x802fafff]
|
|
[DEBUG] stub0 [0x802f3000-0x802f319f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fa800-0x802fabff]
|
|
[DEBUG] stub1 [0x802f2c00-0x802f2d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fa400-0x802fa7ff]
|
|
[DEBUG] stub2 [0x802f2800-0x802f299f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fa000-0x802fa3ff]
|
|
[DEBUG] stub3 [0x802f2400-0x802f259f]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80000fff]
|
|
[DEBUG] Loading module at 0x802fb000 with entry 0x802fb7a0. filesize: 0x4158 memsize: 0x4288
|
|
[DEBUG] Processing 266 relocs. Offset value of 0x802fb000
|
|
[DEBUG] FMAP: area SMMSTORE found @ 810000 (262144 bytes)
|
|
[DEBUG] flash size 0xc00000 bytes
|
|
[INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000
|
|
[DEBUG] smm store: 4 # blocks with size 0x10000
|
|
[DEBUG] Loading module at 0x802f3000 with entry 0x802f3000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f3000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f2400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f3000. Will call 0x802fb7a0
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802eb000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eac00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802eac00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ea800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ea400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 00: PP0 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #2
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[DEBUG] CPU: vendor Intel device 306a9
|
|
[DEBUG] CPU: family 06, model 3a, stepping 09
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz.
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 02: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] APIC: 03: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] CPU: cpuid(1) 0x306a9
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] CPU #3 initialized
|
|
[INFO ] CPU #2 initialized
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 01: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 2600
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 9 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO2 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 20 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling PEG10.
|
|
[DEBUG] Disabling Device 4.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Disabling PEG IO clock.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 35 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 1 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x4a280 size 0x593 in mcache @0x7fffeaf4
|
|
[INFO ] Found a VBT of 4281 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] IVB GT2 25W-35W Power Meter Weights
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[0.029637] HW.GFX.GMA.Initialize
|
|
[0.029639] HW.GFX.GMA.Panel.Setup_PP_Sequencer
|
|
[0.029639] HW.GFX.GMA.Panel.Setup_PP_Sequencer
|
|
[0.029641] HW.GFX.GMA.Registers.Read: 0xc7d00834 <- 0x000c7208:PCH_PP_ON_DELAYS
|
|
[0.029644] HW.GFX.GMA.Registers.Read: 0x07d00834 <- 0x000c720c:PCH_PP_OFF_DELAYS
|
|
[0.029646] HW.GFX.GMA.Registers.Read: 0x00186912 <- 0x000c7210:PCH_PP_DIVISOR
|
|
[0.029647] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL
|
|
[0.029649] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.029650] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.029652] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_LVDS
|
|
[0.029653] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000e1180:PCH_LVDS
|
|
[0.029654] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
|
|
[0.029655] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A
|
|
[0.029656] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB
|
|
[0.029657] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB
|
|
[0.029658] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B
|
|
[0.029659] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B
|
|
[0.029660] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.029661] HW.GFX.GMA.Registers.Read: 0x00180000 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.029662] HW.GFX.GMA.Registers.Write: 0x00180013 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.029664] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC
|
|
[0.029665] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1150:PCH_HDMIC
|
|
[0.029666] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C
|
|
[0.029667] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4200:PCH_DP_C
|
|
[0.029668] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.029669] HW.GFX.GMA.Registers.Read: 0x00180010 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.029670] HW.GFX.GMA.Registers.Write: 0x00181310 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.029672] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID
|
|
[0.029673] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID
|
|
[0.029674] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D
|
|
[0.029675] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4300:PCH_DP_D
|
|
[0.029676] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
|
|
[0.029677] HW.GFX.GMA.Registers.Read: 0x00181010 <- 0x000c4030:SHOTPLUG_CTL
|
|
[0.029678] HW.GFX.GMA.Registers.Write: 0x00131010 -> 0x000c4030:SHOTPLUG_CTL
|
|
[0.029781] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
|
|
[0.029782] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:CPU_VGACNTRL
|
|
[0.029783] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
|
|
[0.029784] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL
|
|
[0.029786] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL
|
|
[0.029789] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
|
|
[0.029791] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ
|
|
[0.029792] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ
|
|
[0.029794] HW.GFX.GMA.Panel.On
|
|
[0.029794] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
|
|
[0.029796] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.029797] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
|
|
[0.029798] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.029799] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.029800] HW.GFX.GMA.Panel.Wait_On
|
|
[0.229801] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
|
|
[0.229803] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
|
|
[0.229805] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.229806] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.229808] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.229809] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.229810] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.229811] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.229813] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.229814] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.229815] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.229817] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230316] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230317] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.230318] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230319] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.230320] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.230321] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230322] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230324] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230820] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230821] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.230822] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230823] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1
|
|
[0.230825] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D
|
|
[0.230826] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230827] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.230829] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.231323] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D
|
|
[0.231324] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.231324] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.231326] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231327] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.231329] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.231330] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231331] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231333] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231830] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231831] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.231832] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231833] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.231835] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.231836] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231837] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.231839] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232337] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232338] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.232339] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232340] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1
|
|
[0.232342] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B
|
|
[0.232343] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232344] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232346] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232840] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B
|
|
[0.232841] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.232841] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.232843] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.232844] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.232846] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.232847] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.232848] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.232850] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233344] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233345] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.233346] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233347] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.233349] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.233350] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233351] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233353] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233849] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233850] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.233851] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233852] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1
|
|
[0.233854] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C
|
|
[0.233855] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233856] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.233858] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.234352] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C
|
|
[0.234353] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.234353] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.234354] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.234354] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.234357] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.234359] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.234361] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
|
|
[0.234363] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.234364] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
|
|
[0.234365] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.234367] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.734369] HW.GFX.GMA.Registers.Wait: Timed Out!
|
|
[0.734371] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734372] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.734372] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734374] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.734376] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.734376] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.734377] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.734377] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.734378] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.734381] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.734383] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734385] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.734386] HW.GFX.GMA.Registers.Read: 0x00008200 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734387] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734389] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.734484] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734485] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734487] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734489] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734490] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734492] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.734590] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734591] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.734593] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734595] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734597] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.734597] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734599] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.734601] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.734601] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.734602] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.734602] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.734604] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.734606] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.734608] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734610] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.734611] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734612] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734614] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.734715] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734716] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.734718] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734720] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734722] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.734722] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734724] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.734726] HW.GFX.GMA.Display_Probing.Read_EDID
|
|
[0.734726] HW.GFX.GMA.I2C.I2C_Read
|
|
[0.734727] HW.GFX.GMA.I2C.Init_GMBUS
|
|
[0.734727] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
|
|
[0.734729] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
|
|
[0.734731] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
|
|
[0.734733] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734735] HW.GFX.GMA.I2C.Check_And_Reset
|
|
[0.734736] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734737] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734739] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
|
|
[0.734841] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
|
|
[0.734842] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
|
|
[0.734844] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734846] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
|
|
[0.734848] HW.GFX.GMA.I2C.Release_GMBUS
|
|
[0.734848] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
|
|
[0.734850] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
|
|
[0.734852] HW.GFX.GMA.Panel.Off
|
|
[0.734852] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
|
|
[0.734854] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.734855] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL
|
|
[0.734857] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL
|
|
[0.734858] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL
|
|
[0.934861] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 905 msecs
|
|
[DEBUG] PCI: 00:00:14.0 init
|
|
[DEBUG] XHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Initializing
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
|
|
[DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED
|
|
[CRIT ] intel_me_path: mbp is not ready!
|
|
[NOTE ] ME: BIOS path: Error
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:19.0 init
|
|
[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0x83830000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: initializing codec #3...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x80862806
|
|
[DEBUG] azalia_audio: - verb size: 16
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0269
|
|
[DEBUG] azalia_audio: - verb size: 76
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 5 msecs
|
|
[DEBUG] PCI: 00:00:1c.0 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.1 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1c.2 init
|
|
[DEBUG] Initializing PCH PCIe bridge.
|
|
[DEBUG] PCI: 00:00:1c.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] PantherPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0x83836000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1f.6 init
|
|
[DEBUG] PCI: 00:00:1f.6 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:01:00.0 init
|
|
[DEBUG] PCI: 00:01:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:02:00.0 init
|
|
[DEBUG] PCI: 00:02:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 00ff.2 init
|
|
[DEBUG] PNP: 00ff.2 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:54 init
|
|
[DEBUG] I2C: 01:54 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:55 init
|
|
[DEBUG] I2C: 01:55 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:56 init
|
|
[DEBUG] I2C: 01:56 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:57 init
|
|
[DEBUG] I2C: 01:57 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5c init
|
|
[DEBUG] Locking EEPROM RFID
|
|
[DEBUG] init EEPROM done
|
|
[DEBUG] I2C: 01:5c init finished in 26 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5d init
|
|
[DEBUG] I2C: 01:5d init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5e init
|
|
[DEBUG] I2C: 01:5e init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:00:1f.3->I2C: 01:5f init
|
|
[DEBUG] I2C: 01:5f init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 959 / 1 ms
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 50 / 0 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x46880 size 0x39ad in mcache @0x7fffeac8
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fe13000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6 C7 C7S
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PSS: 2601MHz power 35000 control 0x2100 status 0x2100
|
|
[DEBUG] PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 31561 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 28247 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 25084 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 22064 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 19135 control 0x1000 status 0x1000
|
|
[DEBUG] PSS: 1400MHz power 16344 control 0xe00 status 0xe00
|
|
[DEBUG] PSS: 1200MHz power 13666 control 0xc00 status 0xc00
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C7
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x17d600000, len = 0xe82a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[DEBUG] PPI: Pending OS request: 0xfb50b887 (0x43ff6676)
|
|
[DEBUG] PPI: OS response: CMD 0xc556c48b = 0xbaf62a64
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
|
|
[INFO ] ACPI: * H8
|
|
[INFO ] H8: BDC detection not implemented. Assuming BDC installed
|
|
[INFO ] H8: WWAN not installed
|
|
[INFO ] \_SB.PCI0.RP02.WF00: PCI: 00:02:00.0
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] TCPA log created at 0x7fe03000
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] current = 7fe18a40
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[DEBUG] current = 7fe18b00
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 7/32, length now 92
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 23360 bytes.
|
|
[DEBUG] smbios_write_tables: 7fdfb000
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[INFO ] PCI: 00:02:00.0 (unknown)
|
|
[DEBUG] SMBIOS tables: 968 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum ffb
|
|
[DEBUG] Writing coreboot table at 0x7fe37000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000007fdfafff: RAM
|
|
[DEBUG] 6. 000000007fdfb000-000000007fe63fff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007fe64000-000000007ffcefff: RAMSTAGE
|
|
[DEBUG] 8. 000000007ffcf000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 9. 0000000080000000-00000000829fffff: RESERVED
|
|
[DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 11. 00000000fed40000-00000000fed44fff: RESERVED
|
|
[DEBUG] 12. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 13. 0000000100000000-000000017d5fffff: RAM
|
|
[DEBUG] FMAP: area SMMSTORE found @ 810000 (262144 bytes)
|
|
[DEBUG] smm store: 4 # blocks with size 0x10000
|
|
[DEBUG] Wrote coreboot table at: 0x7fe37000, 0x428 bytes, checksum 6a64
|
|
[DEBUG] coreboot table: 1088 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] TIME STAMP 3. 0x7ffdd000 0x00000910
|
|
[DEBUG] MEM INFO 4. 0x7ffdc000 0x00000f48
|
|
[DEBUG] AFTER CAR 5. 0x7ffcf000 0x0000d000
|
|
[DEBUG] RAMSTAGE 6. 0x7fe63000 0x0016c000
|
|
[DEBUG] SMM BACKUP 7. 0x7fe53000 0x00010000
|
|
[DEBUG] SMM COMBUFFER 8. 0x7fe43000 0x00010000
|
|
[DEBUG] IGD OPREGION 9. 0x7fe3f000 0x00003200
|
|
[DEBUG] COREBOOT 10. 0x7fe37000 0x00008000
|
|
[DEBUG] ACPI 11. 0x7fe13000 0x00024000
|
|
[DEBUG] TCPA TCGLOG12. 0x7fe03000 0x00010000
|
|
[DEBUG] SMBIOS 13. 0x7fdfb000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] RO MCACHE 1. 0x7fffe940 0x000002c0
|
|
[DEBUG] FMAP 2. 0x7fffe820 0x0000010a
|
|
[DEBUG] ROMSTAGE 3. 0x7fffe800 0x00000004
|
|
[DEBUG] ROMSTG STCK 4. 0x7fffe740 0x000000a8
|
|
[DEBUG] ACPI GNVS 5. 0x7fffe640 0x00000100
|
|
[DEBUG] TPM PPI 6. 0x7fffe4e0 0x0000015a
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 25 / 0 ms
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x50cc0 size 0x115e82 in mcache @0x7fffeb90
|
|
[DEBUG] Checking segment from ROM address 0xffca0eec
|
|
[DEBUG] Checking segment from ROM address 0xffca0f08
|
|
[DEBUG] Loading segment from ROM address 0xffca0eec
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffca0f24 filesize 0x115e4a
|
|
[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x0000000000115e4a
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xffca0f08
|
|
[DEBUG] Entry Point 0x0080249a
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 360 / 0 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x0080249a(0x7fe37000)
|