|
�
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x40000.
|
|
[DEBUG] FMAP: base = 0xffe00000 size = 0x200000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[INFO ] CBFS: mcache @0xfeff0e00 built for 16 files, used 0x344 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x68c0 size 0x17050 in mcache @0xfeff0e5c
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 46 ms
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[ERROR] early_usb_init: USB00: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB01: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB02: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB03: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB04: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB05: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB06: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB07: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB08: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB09: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB10: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB11: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB12: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB13: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[INFO ] Detected system type: desktop
|
|
[DEBUG] Setting up static northbridge registers... done
|
|
[DEBUG] Graphics not supported by this CPU/chipset.
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 32MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[DEBUG] DMI: Running at X4 @ 5000MT/s
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] ECC supported: no ECC forced: no
|
|
[INFO ] ECC RAM unsupported.
|
|
[DEBUG] SPD probe channel0, slot0
|
|
[DEBUG] SPD probe channel0, slot1
|
|
[INFO ] Row addr bits : 14
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 2048 MB
|
|
[INFO ] CAS latencies : 6 7 8 9
|
|
[INFO ] tCKmin : 1.500 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 36.000 ns
|
|
[INFO ] tRCmin : 49.125 ns
|
|
[INFO ] tRFCmin : 110.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[0] rankmap = 0xc
|
|
[DEBUG] SPD probe channel1, slot0
|
|
[DEBUG] SPD probe channel1, slot1
|
|
[INFO ] Row addr bits : 14
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 2048 MB
|
|
[INFO ] CAS latencies : 6 7 8 9
|
|
[INFO ] tCKmin : 1.500 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 36.000 ns
|
|
[INFO ] tRCmin : 49.125 ns
|
|
[INFO ] tRFCmin : 110.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[1] rankmap = 0xc
|
|
[DEBUG] ECC is disabled
|
|
[DEBUG] Starting Sandy Bridge RAM training (full initialization).
|
|
[DEBUG] 100MHz reference clock support: no
|
|
[DEBUG] PLL_REF100_CFG value: 0x0
|
|
[DEBUG] Trying CAS 9, tCK 384.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 666 MHz
|
|
[DEBUG] Selected CAS latency : 9T
|
|
[DEBUG] MPLL busy... done in 10 us
|
|
[DEBUG] MPLL frequency is set at : 666 MHz
|
|
[DEBUG] Selected CWL latency : 7T
|
|
[DEBUG] Selected tRCD : 9T
|
|
[DEBUG] Selected tRP : 9T
|
|
[DEBUG] Selected tRAS : 24T
|
|
[DEBUG] Selected tWR : 10T
|
|
[DEBUG] Selected tFAW : 20T
|
|
[DEBUG] Selected tRRD : 4T
|
|
[DEBUG] Selected tRTP : 5T
|
|
[DEBUG] Selected tWTR : 5T
|
|
[DEBUG] Selected tRFC : 74T
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 1
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 8a800000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 73800000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 1
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80800000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] PCI(0, 0, 0)[7c] = 7f
|
|
[DEBUG] PCI(0, 0, 0)[70] = fe000000
|
|
[DEBUG] PCI(0, 0, 0)[74] = 0
|
|
[DEBUG] PCI(0, 0, 0)[78] = fe000c00
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[WARN ] Logic delay 2 greater than 1: 0 2
|
|
[WARN ] Logic delay 2 greater than 1: 0 3
|
|
[DEBUG] t123: 1768, 9120, 500
|
|
[NOTE ] ME: Wrong mode : 4
|
|
[NOTE ] ME: FWS2: 0x104e0002
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x4e
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] Waited long enough, or CPU was not replaced, continue...
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: FWS2: 0x10240002
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x24
|
|
[NOTE ] ME: Current PM event: 0x0
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: Non-power cycle reset
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x40000.
|
|
[DEBUG] FMAP: base = 0xffe00000 size = 0x200000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[INFO ] CBFS: mcache @0xfeff0e00 built for 16 files, used 0x344 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x68c0 size 0x17050 in mcache @0xfeff0e5c
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 46 ms
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[ERROR] early_usb_init: USB00: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB01: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB02: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB03: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB04: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB05: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB06: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB07: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB08: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB09: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB10: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB11: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB12: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB13: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[INFO ] Detected system type: desktop
|
|
[DEBUG] Setting up static northbridge registers... done
|
|
[DEBUG] Initializing Graphics...
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 32MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[INFO ] system_reset() called!
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 bootblock starting (log level: 7)...
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x40000.
|
|
[DEBUG] FMAP: base = 0xffe00000 size = 0x200000 #areas = 4
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[INFO ] CBFS: mcache @0xfeff0e00 built for 16 files, used 0x344 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x68c0 size 0x17050 in mcache @0xfeff0e5c
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 46 ms
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[ERROR] early_usb_init: USB00: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB01: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB02: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB03: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB04: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB05: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB06: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB07: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB08: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB09: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB10: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB11: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB12: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[ERROR] early_usb_init: USB13: USBIR_TXRX_GAIN_MOBILE_LOW is an invalid setting for desktop!
|
|
[INFO ] Detected system type: desktop
|
|
[DEBUG] Setting up static northbridge registers... done
|
|
[DEBUG] Initializing Graphics...
|
|
[DEBUG] Back from systemagent_early_init()
|
|
[INFO ] Intel ME early init
|
|
[INFO ] Intel ME firmware is ready
|
|
[DEBUG] ME: Requested 32MB UMA
|
|
[DEBUG] Starting native Platform init
|
|
[DEBUG] DMI: Running at X4 @ 5000MT/s
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] ECC supported: no ECC forced: no
|
|
[INFO ] ECC RAM unsupported.
|
|
[DEBUG] SPD probe channel0, slot0
|
|
[DEBUG] SPD probe channel0, slot1
|
|
[INFO ] Row addr bits : 14
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 2048 MB
|
|
[INFO ] CAS latencies : 6 7 8 9
|
|
[INFO ] tCKmin : 1.500 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 36.000 ns
|
|
[INFO ] tRCmin : 49.125 ns
|
|
[INFO ] tRFCmin : 110.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[0] rankmap = 0xc
|
|
[DEBUG] SPD probe channel1, slot0
|
|
[DEBUG] SPD probe channel1, slot1
|
|
[INFO ] Row addr bits : 14
|
|
[INFO ] Column addr bits : 10
|
|
[INFO ] Number of ranks : 2
|
|
[INFO ] DIMM Capacity : 2048 MB
|
|
[INFO ] CAS latencies : 6 7 8 9
|
|
[INFO ] tCKmin : 1.500 ns
|
|
[INFO ] tAAmin : 13.125 ns
|
|
[INFO ] tWRmin : 15.000 ns
|
|
[INFO ] tRCDmin : 13.125 ns
|
|
[INFO ] tRRDmin : 6.000 ns
|
|
[INFO ] tRPmin : 13.125 ns
|
|
[INFO ] tRASmin : 36.000 ns
|
|
[INFO ] tRCmin : 49.125 ns
|
|
[INFO ] tRFCmin : 110.000 ns
|
|
[INFO ] tWTRmin : 7.500 ns
|
|
[INFO ] tRTPmin : 7.500 ns
|
|
[INFO ] tFAWmin : 30.000 ns
|
|
[DEBUG] channel[1] rankmap = 0xc
|
|
[DEBUG] ECC is disabled
|
|
[DEBUG] Starting Sandy Bridge RAM training (full initialization).
|
|
[DEBUG] 100MHz reference clock support: no
|
|
[DEBUG] PLL_REF100_CFG value: 0x0
|
|
[DEBUG] Trying CAS 9, tCK 384.
|
|
[DEBUG] Found compatible clock, CAS pair.
|
|
[DEBUG] Selected DRAM frequency: 666 MHz
|
|
[DEBUG] Selected CAS latency : 9T
|
|
[DEBUG] MPLL busy... done in 10 us
|
|
[DEBUG] MPLL frequency is set at : 666 MHz
|
|
[DEBUG] Selected CWL latency : 7T
|
|
[DEBUG] Selected tRCD : 9T
|
|
[DEBUG] Selected tRP : 9T
|
|
[DEBUG] Selected tRAS : 24T
|
|
[DEBUG] Selected tWR : 10T
|
|
[DEBUG] Selected tFAW : 20T
|
|
[DEBUG] Selected tRRD : 4T
|
|
[DEBUG] Selected tRTP : 5T
|
|
[DEBUG] Selected tWTR : 5T
|
|
[DEBUG] Selected tRFC : 74T
|
|
[DEBUG] Done dimm mapping
|
|
[DEBUG] Update PCI-E configuration space:
|
|
[DEBUG] PCI(0, 0, 0)[a0] = 0
|
|
[DEBUG] PCI(0, 0, 0)[a4] = 1
|
|
[DEBUG] PCI(0, 0, 0)[bc] = 82a00000
|
|
[DEBUG] PCI(0, 0, 0)[a8] = 7b600000
|
|
[DEBUG] PCI(0, 0, 0)[ac] = 1
|
|
[DEBUG] PCI(0, 0, 0)[b8] = 80000000
|
|
[DEBUG] PCI(0, 0, 0)[b0] = 80a00000
|
|
[DEBUG] PCI(0, 0, 0)[b4] = 80800000
|
|
[DEBUG] PCI(0, 0, 0)[7c] = 7f
|
|
[DEBUG] PCI(0, 0, 0)[70] = fe000000
|
|
[DEBUG] PCI(0, 0, 0)[74] = 0
|
|
[DEBUG] PCI(0, 0, 0)[78] = fe000c00
|
|
[DEBUG] Done memory map
|
|
[DEBUG] Done io registers
|
|
[DEBUG] Done jedec reset
|
|
[DEBUG] Done MRS commands
|
|
[WARN ] Logic delay 2 greater than 1: 0 2
|
|
[WARN ] Logic delay 2 greater than 1: 0 3
|
|
[DEBUG] t123: 1768, 9120, 500
|
|
[NOTE ] ME: Wrong mode : 4
|
|
[NOTE ] ME: FWS2: 0x164e0002
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x4e
|
|
[NOTE ] ME: Current PM event: 0x6
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] Waited long enough, or CPU was not replaced, continue...
|
|
[NOTE ] PASSED! Tell ME that DRAM is ready
|
|
[NOTE ] ME: FWS2: 0x16520002
|
|
[NOTE ] ME: Bist in progress: 0x0
|
|
[NOTE ] ME: ICC Status : 0x1
|
|
[NOTE ] ME: Invoke MEBx : 0x0
|
|
[NOTE ] ME: CPU replaced : 0x0
|
|
[NOTE ] ME: MBP ready : 0x0
|
|
[NOTE ] ME: MFS failure : 0x0
|
|
[NOTE ] ME: Warm reset req : 0x0
|
|
[NOTE ] ME: CPU repl valid : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: FW update req : 0x0
|
|
[NOTE ] ME: (Reserved) : 0x0
|
|
[NOTE ] ME: Current state : 0x52
|
|
[NOTE ] ME: Current PM event: 0x6
|
|
[NOTE ] ME: Progress code : 0x1
|
|
[NOTE ] ME: Requested BIOS Action: Continue to boot
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Recovery
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Security Override via Jumper
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Pseudo-global reset
|
|
[DEBUG] ME: Progress Phase State : 0x52
|
|
[DEBUG] memcfg DDR3 ref clock 133 MHz
|
|
[DEBUG] memcfg DDR3 clock 1330 MHz
|
|
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
|
|
[DEBUG] memcfg channel[0] config (00630008):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 2048 MB width x8 dual rank
|
|
[DEBUG] DIMMB 0 MB width x8 single rank, selected
|
|
[DEBUG] memcfg channel[1] config (00630008):
|
|
[DEBUG] ECC inactive
|
|
[DEBUG] enhanced interleave mode on
|
|
[DEBUG] rank interleave on
|
|
[DEBUG] DIMMA 2048 MB width x8 dual rank
|
|
[DEBUG] DIMMB 0 MB width x8 single rank, selected
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7ffff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7fffec00 62 entries.
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x803ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x803fec00 62 entries.
|
|
[DEBUG] FMAP: area RW_MRC_CACHE found @ 30000 (65536 bytes)
|
|
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
|
|
[INFO ] Manufacturer: c2
|
|
[INFO ] SF: Detected c2 2017 with sector size 0x1000, total 0x800000
|
|
[ERROR] SF size 0x800000 does not correspond to CONFIG_ROM_SIZE 0x200000!!
|
|
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
|
|
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
|
|
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
|
|
[DEBUG] CBMEM entry for DIMM info: 0x7ffdb000
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x80000000 0x800000
|
|
[DEBUG] Subregion 0: 0x80000000 0x300000
|
|
[DEBUG] Subregion 1: 0x80300000 0x100000
|
|
[DEBUG] Subregion 2: 0x80400000 0x400000
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x46580 size 0x5e68 in mcache @0xfeff103c
|
|
[DEBUG] Loading module at 0x7ffcf000 with entry 0x7ffcf031. filesize: 0x5a88 memsize: 0xbdd8
|
|
[DEBUG] Processing 232 relocs. Offset value of 0x7dfcf000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 908 ms
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x1d980 size 0x1d84f in mcache @0x7ffdd0bc
|
|
[DEBUG] Loading module at 0x7fe83000 with entry 0x7fe83000. filesize: 0x3b1e0 memsize: 0x14a350
|
|
[DEBUG] Processing 4354 relocs. Offset value of 0x7be83000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 44 ms
|
|
|
|
|
|
[NOTE ] coreboot-24.12-869-g92d77dd2e385-dirty Sun Mar 16 05:25:07 UTC 2025 x86_32 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 00000000 enabled
|
|
[DEBUG] DOMAIN: 00000000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
|
|
[DEBUG] PCI: 00:00:00.0 [8086/0100] enabled
|
|
[DEBUG] PCI: 00:00:01.0 [8086/0101] enabled
|
|
[DEBUG] PCI: 00:00:02.0 [8086/0102] enabled
|
|
[DEBUG] PCI: 00:00:14.0: Disabling device
|
|
[DEBUG] PCI: 00:00:16.0 [8086/1c3a] enabled
|
|
[DEBUG] PCI: 00:00:16.1: Disabling device
|
|
[DEBUG] PCI: 00:00:16.2: Disabling device
|
|
[INFO ] PCI: Static device PCI: 00:00:16.3 not found, disabling it.
|
|
[DEBUG] PCI: 00:00:19.0 [8086/1502] enabled
|
|
[DEBUG] PCI: 00:00:1a.0 [8086/1c2d] enabled
|
|
[DEBUG] PCI: 00:00:1b.0 [8086/1c20] enabled
|
|
[DEBUG] PCI: 00:00:1c.0: No downstream device
|
|
[INFO ] PCH: PCIe Root Port coalescing is enabled
|
|
[DEBUG] PCI: 00:00:1c.0: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.0: check set enabled
|
|
[DEBUG] PCI: 00:00:1c.1: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.1: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.2: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.2: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.3: Found a downstream device
|
|
[DEBUG] PCI: 00:00:1c.3: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.4: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.4: check set enabled
|
|
[DEBUG] PCI: 00:00:1c.5: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.6: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1c.7: No downstream device
|
|
[DEBUG] PCI: 00:00:1c.7: Disabling device
|
|
[DEBUG] PCI: 00:00:1d.0 [8086/1c26] enabled
|
|
[DEBUG] PCI: 00:00:1e.0 [8086/244e] enabled
|
|
[DEBUG] PCI: 00:00:1f.0 [8086/1c4e] enabled
|
|
[DEBUG] PCI: 00:00:1f.2 [8086/1c00] enabled
|
|
[DEBUG] PCI: 00:00:1f.3 [8086/1c22] enabled
|
|
[DEBUG] PCI: 00:00:1f.5: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.5 [8086/1c08] disabled No operations
|
|
[DEBUG] PCI: 00:00:1f.6: Disabling device
|
|
[DEBUG] PCI: 00:00:1f.6 [8086/1c24] disabled No operations
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:00:01.1
|
|
[WARN ] PCI: 00:00:01.2
|
|
[WARN ] PCI: 00:00:04.0
|
|
[WARN ] PCI: 00:00:06.0
|
|
[WARN ] PCI: 00:00:16.3
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:00:01.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
|
|
[INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 128 for devices under this root port
|
|
[DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 14 msecs
|
|
[DEBUG] PCI: 00:00:1e.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 02
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1e.0 finished in 5 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 scanning...
|
|
[DEBUG] PNP: 002e.ff enabled
|
|
[INFO ] Found TPM 1.2 SLB9635 TT 1.2 (0x000b) by Infineon (0x15d1)
|
|
[DEBUG] PNP: 004e.0 enabled
|
|
[DEBUG] PNP: 002e.ff scanning...
|
|
[DEBUG] PNP: 002e.0 disabled
|
|
[DEBUG] PNP: 002e.1 enabled
|
|
[DEBUG] PNP: 002e.2 disabled
|
|
[DEBUG] PNP: 002e.3 enabled
|
|
[DEBUG] PNP: 002e.4 enabled
|
|
[DEBUG] PNP: 002e.5 enabled
|
|
[DEBUG] PNP: 002e.6 enabled
|
|
[DEBUG] PNP: 002e.7 enabled
|
|
[DEBUG] PNP: 002e.8 enabled
|
|
[DEBUG] PNP: 002e.f enabled
|
|
[DEBUG] PNP: 002e.15 enabled
|
|
[DEBUG] PNP: 002e.1c enabled
|
|
[DEBUG] PNP: 002e.1e enabled
|
|
[DEBUG] scan_bus: bus PNP: 002e.ff finished in 43 msecs
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 65 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 scanning...
|
|
[DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 342 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 359 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 374 ms
|
|
[DEBUG] found VGA at PCI: 00:00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[DEBUG] TOUUD 0x17b600000 TOLUD 0x82a00000 TOM 0x100000000
|
|
[DEBUG] MEBASE 0xfe000000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT
|
|
[DEBUG] TSEG base 0x80000000 size 8M
|
|
[INFO ] Available memory below 4GB: 2048M
|
|
[INFO ] Available memory above 4GB: 1974M
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.ff 00 base 0000002e limit 0000002f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.3 60 base 000003f8 limit 000003ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 60 base 00000600 limit 00000607 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.4 62 base 00000610 limit 0000061f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.6 60 base 00000060 limit 00000060 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.6 62 base 00000064 limit 00000064 io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.7 60 base 00000620 limit 0000063f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.8 60 base 00000800 limit 000008ff io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.15 60 base 00000680 limit 0000068f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.15 62 base 00000690 limit 0000069f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1c 60 base 00000640 limit 0000065f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 002e.1e 60 base 00000660 limit 0000067f io (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: f000, Tag: 100
|
|
[DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io
|
|
[DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io
|
|
[DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io
|
|
[DEBUG] PCI: 00:00:1f.2 10 * [0xff78 - 0xff7f] limit: ff7f io
|
|
[DEBUG] PCI: 00:00:1f.2 18 * [0xff70 - 0xff77] limit: ff77 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 * [0xff6c - 0xff6f] limit: ff6f io
|
|
[DEBUG] PCI: 00:00:1f.2 1c * [0xff68 - 0xff6b] limit: ff6b io
|
|
[DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 100000000 limit 17b5fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 80000000 limit 829fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 20000000 limit 201fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 40000000 limit 401fffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base fed90000 limit fed90fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base fed91000 limit fed91fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[DEBUG] avoid_fixed_resources: PNP: 004e.0 00 base fed40000 limit fed44fff mem (fixed)
|
|
[INFO ] DOMAIN: 00000000: Resource ranges:
|
|
[INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200
|
|
[INFO ] * Base: 17b600000, Size: e84a00000, Tag: 200
|
|
[DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem
|
|
[DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
|
|
[DEBUG] PCI: 00:00:19.0 10 * [0xdfbe0000 - 0xdfbfffff] limit: dfbfffff mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 * [0xdfbdc000 - 0xdfbdffff] limit: dfbdffff mem
|
|
[DEBUG] PCI: 00:00:19.0 14 * [0xdfbdb000 - 0xdfbdbfff] limit: dfbdbfff mem
|
|
[DEBUG] PCI: 00:00:1f.2 24 * [0xdfbda000 - 0xdfbda7ff] limit: dfbda7ff mem
|
|
[DEBUG] PCI: 00:00:1a.0 10 * [0xdfbd9000 - 0xdfbd93ff] limit: dfbd93ff mem
|
|
[DEBUG] PCI: 00:00:1d.0 10 * [0xdfbd8000 - 0xdfbd83ff] limit: dfbd83ff mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 * [0xdfbd7000 - 0xdfbd70ff] limit: dfbd70ff mem
|
|
[DEBUG] PCI: 00:00:16.0 10 * [0xdfbd6000 - 0xdfbd600f] limit: dfbd600f mem
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: efffffff done
|
|
[DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
|
|
[DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
|
|
[DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
|
|
[DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
|
|
[DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io
|
|
[DEBUG] PCI: 00:00:16.0 10 <- [0x00000000dfbd6000 - 0x00000000dfbd600f] size 0x00000010 gran 0x04 mem64
|
|
[DEBUG] PCI: 00:00:19.0 10 <- [0x00000000dfbe0000 - 0x00000000dfbfffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:00:19.0 14 <- [0x00000000dfbdb000 - 0x00000000dfbdbfff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000dfbd9000 - 0x00000000dfbd93ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000dfbdc000 - 0x00000000dfbdffff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000dfbd8000 - 0x00000000dfbd83ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io
|
|
[DEBUG] PCI: 00:00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem
|
|
[DEBUG] PCI: 00:00:1e.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 mem
|
|
[DEBUG] PNP: 002e.1 14 <- [0x000000000000009c - 0x000000000000009b] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1c <- [0x00000000000000a8 - 0x00000000000000a7] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1d <- [0x0000000000000008 - 0x0000000000000007] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 22 <- [0x000000000000003f - 0x000000000000003e] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1a <- [0x00000000000000b0 - 0x00000000000000af] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 1b <- [0x000000000000001e - 0x000000000000001d] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 27 <- [0x0000000000000008 - 0x0000000000000007] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 2a <- [0x0000000000000020 - 0x000000000000001f] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 2d <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.1 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.1 74 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.3 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.3 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.4 60 <- [0x0000000000000600 - 0x0000000000000607] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 002e.4 62 <- [0x0000000000000610 - 0x000000000000061f] size 0x00000010 gran 0x04 io
|
|
[NOTE ] PNP: 002e.4 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.4 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.5 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.6 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.6 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
|
|
[DEBUG] PNP: 002e.6 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 002e.6 f0 <- [0x0000000000000040 - 0x000000000000003f] size 0x00000000 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.7 60 <- [0x0000000000000620 - 0x000000000000063f] size 0x00000020 gran 0x05 io
|
|
[NOTE ] PNP: 002e.7 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.7 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.8 60 <- [0x0000000000000800 - 0x00000000000008ff] size 0x00000100 gran 0x08 io
|
|
[DEBUG] PNP: 002e.8 f0 <- [0x0000000000000020 - 0x0000000000000020] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f1 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f2 <- [0x0000000000000040 - 0x0000000000000040] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f3 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f4 <- [0x0000000000000066 - 0x0000000000000066] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f5 <- [0x0000000000000067 - 0x0000000000000067] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f6 <- [0x0000000000000066 - 0x0000000000000066] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.8 f7 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.8 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.f f1 <- [0x0000000000000097 - 0x0000000000000097] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f f2 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f f5 <- [0x0000000000000008 - 0x0000000000000008] size 0x00000001 gran 0x00 drq
|
|
[DEBUG] PNP: 002e.f fe <- [0x0000000000000080 - 0x0000000000000080] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.f f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.f fd irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.15 60 <- [0x0000000000000680 - 0x000000000000068f] size 0x00000010 gran 0x04 io
|
|
[DEBUG] PNP: 002e.15 62 <- [0x0000000000000690 - 0x000000000000069f] size 0x00000010 gran 0x04 io
|
|
[NOTE ] PNP: 002e.15 70 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f4 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f5 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f6 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f7 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f8 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 f9 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fa irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fb irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fc irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fd irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.15 fe irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.1c 60 <- [0x0000000000000640 - 0x000000000000065f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PNP: 002e.1e 60 <- [0x0000000000000660 - 0x000000000000067f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PNP: 002e.1e f4 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 drq
|
|
[NOTE ] PNP: 002e.1e f0 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f1 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f2 irq size: 0x0000000001 not assigned in devicetree
|
|
[NOTE ] PNP: 002e.1e f3 irq size: 0x0000000001 not assigned in devicetree
|
|
[DEBUG] PNP: 002e.ff 00 <- [0x000000000000002e - 0x000000000000002f] size 0x00000002 gran 0x00 io
|
|
[DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000dfbda000 - 0x00000000dfbda7ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000dfbd7000 - 0x00000000dfbd70ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1562 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00:00.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:01.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:01.0 cmd <- 00
|
|
[DEBUG] PCI: 00:00:02.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:00:16.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:16.0 cmd <- 02
|
|
[DEBUG] PCI: 00:00:19.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:00:1a.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1a.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1b.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1d.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1d.0 cmd <- 102
|
|
[DEBUG] PCI: 00:00:1e.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:00:1e.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1e.0 cmd <- 100
|
|
[DEBUG] PCI: 00:00:1f.0 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:00:1f.2 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:00:1f.3 subsystem <- 103c/1495
|
|
[DEBUG] PCI: 00:00:1f.3 cmd <- 103
|
|
[INFO ] done.
|
|
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 120 ms
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
|
|
[DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0
|
|
[DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
|
|
[DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000017b5fffff size 0x7b600000 type 6
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 4/3.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 4 cores, 4 threads enabled.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[DEBUG] microcode: sig=0x206a7 pf=0x2 revision=0x2f
|
|
[DEBUG] FMAP: area COREBOOT found @ 40200 (1834496 bytes)
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x6800 in mcache @0x7ffdd02c
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] CPU: APIC: 02 enabled
|
|
[DEBUG] CPU: APIC: 03 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 3 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[INFO ] LAPIC 0x2 in XAPIC mode.
|
|
[INFO ] LAPIC 0x4 in XAPIC mode.
|
|
[INFO ] AP: slot 1 apic_id 2, MCU rev: 0x0000002f
|
|
[INFO ] AP: slot 2 apic_id 4, MCU rev: 0x0000002f
|
|
[INFO ] LAPIC 0x6 in XAPIC mode.
|
|
[INFO ] AP: slot 3 apic_id 6, MCU rev: 0x0000002f
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7fea3270
|
|
[DEBUG] Installing permanent SMM handler to 0x80000000
|
|
[DEBUG] HANDLER [0x802fe000-0x802ff1ef]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x802fdc00-0x802fdfff]
|
|
[DEBUG] stub0 [0x802f6000-0x802f619f]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x802fd800-0x802fdbff]
|
|
[DEBUG] stub1 [0x802f5c00-0x802f5d9f]
|
|
|
|
[DEBUG] CPU 2
|
|
[DEBUG] ss2 [0x802fd400-0x802fd7ff]
|
|
[DEBUG] stub2 [0x802f5800-0x802f599f]
|
|
|
|
[DEBUG] CPU 3
|
|
[DEBUG] ss3 [0x802fd000-0x802fd3ff]
|
|
[DEBUG] stub3 [0x802f5400-0x802f559f]
|
|
|
|
[DEBUG] stacks [0x80000000-0x80000fff]
|
|
[DEBUG] Loading module at 0x802fe000 with entry 0x802fe27b. filesize: 0x11d0 memsize: 0x11f0
|
|
[DEBUG] Processing 56 relocs. Offset value of 0x802fe000
|
|
[DEBUG] Loading module at 0x802f6000 with entry 0x802f6000. filesize: 0x1a0 memsize: 0x1a0
|
|
[DEBUG] Processing 9 relocs. Offset value of 0x802f6000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x80001000
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5c00, cpu # 0x1
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5800, cpu # 0x2
|
|
[DEBUG] SMM Module: placing smm entry code at 802f5400, cpu # 0x3
|
|
[DEBUG] SMM Module: stub loaded at 802f6000. Will call 0x802fe27b
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ee000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x802ee000 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802edc00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x802edc00 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed800, cpu = 2
|
|
[DEBUG] In relocation handler: cpu 2
|
|
[DEBUG] New SMBASE=0x802ed800 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed400, cpu = 3
|
|
[DEBUG] In relocation handler: cpu 3
|
|
[DEBUG] New SMBASE=0x802ed400 IEDBASE=0x80400000
|
|
[DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] microcode: Update skipped, already up-to-date
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 206a7
|
|
[DEBUG] CPU: family 06, model 2a, stepping 07
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz.
|
|
[INFO ] CPU: cpuid(1) 0x206a7
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[INFO ] APIC: 00: PP0 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP0 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 current limit not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI0 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI1 not set in devicetree
|
|
[INFO ] APIC: 00: PP1 PSI2 not set in devicetree
|
|
[INFO ] APIC: 00: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 3100
|
|
[INFO ] Turbo is available but hidden
|
|
[INFO ] Turbo is available and visible
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[INFO ] Initializing CPU #3
|
|
[DEBUG] CPU: vendor Intel device 206a7
|
|
[DEBUG] CPU: family 06, model 2a, stepping 07
|
|
[INFO ] Initializing CPU #2
|
|
[DEBUG] CPU: vendor Intel device 206a7
|
|
[DEBUG] CPU: family 06, model 2a, stepping 07
|
|
[DEBUG] CPU: vendor Intel device 206a7
|
|
[DEBUG] CPU: family 06, model 2a, stepping 07
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz.
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz.
|
|
[INFO ] CPU: Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz.
|
|
[INFO ] CPU: cpuid(1) 0x206a7
|
|
[INFO ] CPU: cpuid(1) 0x206a7
|
|
[INFO ] CPU: cpuid(1) 0x206a7
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[INFO ] CPU: AES supported
|
|
[INFO ] CPU: TXT supported
|
|
[INFO ] CPU: VT supported
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] APIC: 06: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] IA32_FEATURE_CONTROL status: locked
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[INFO ] APIC: 04: Programmable ratio limit for turbo mode is disabled
|
|
[INFO ] APIC: 04: Programmable ratio limit for turbo mode is disabled
|
|
[DEBUG] model_x06ax: frequency set to 3100
|
|
[INFO ] CPU #3 initialized
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] cpu: energy policy set to 6
|
|
[DEBUG] model_x06ax: frequency set to 3100
|
|
[INFO ] CPU #2 initialized
|
|
[DEBUG] model_x06ax: frequency set to 3100
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 609 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 910 msecs
|
|
[DEBUG] PCI: 00:00:00.0 init
|
|
[DEBUG] Disabling PEG12.
|
|
[DEBUG] Disabling PEG11.
|
|
[DEBUG] Disabling Device 4.
|
|
[DEBUG] Disabling PEG60.
|
|
[DEBUG] Disabling Device 7.
|
|
[DEBUG] Set BIOS_RESET_CPL
|
|
[DEBUG] CPU TDP: 95 Watts
|
|
[DEBUG] PCI: 00:00:00.0 init finished in 22 msecs
|
|
[DEBUG] PCI: 00:00:01.0 init
|
|
[DEBUG] PCI: 00:00:01.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:02.0 init
|
|
[INFO ] CBFS: Found 'vbt.bin' @0x45b80 size 0x4c6 in mcache @0x7ffdd1e4
|
|
[INFO ] Found a VBT of 3777 bytes
|
|
[INFO ] GMA: Found VBT in CBFS
|
|
[INFO ] GMA: Found valid VBT in CBFS
|
|
[DEBUG] GT Power Management Init
|
|
[DEBUG] SNB GT1 Power Meter Weights
|
|
[DEBUG] GT Power Management Init (post VBIOS)
|
|
[DEBUG] PCI: 00:00:02.0 init finished in 47 msecs
|
|
[DEBUG] PCI: 00:00:16.0 init
|
|
[DEBUG] ME: FW Partition Table : OK
|
|
[DEBUG] ME: Bringup Loader Failure : NO
|
|
[DEBUG] ME: Firmware Init Complete : NO
|
|
[DEBUG] ME: Manufacturing Mode : YES
|
|
[DEBUG] ME: Boot Options Present : NO
|
|
[DEBUG] ME: Update In Progress : NO
|
|
[DEBUG] ME: Current Working State : Recovery
|
|
[DEBUG] ME: Current Operation State : Bring up
|
|
[DEBUG] ME: Current Operation Mode : Security Override via Jumper
|
|
[DEBUG] ME: Error Code : No Error
|
|
[DEBUG] ME: Progress Phase : BUP Phase
|
|
[DEBUG] ME: Power Management Event : Pseudo-global reset
|
|
[DEBUG] ME: Progress Phase State : 0x52
|
|
[NOTE ] ME: BIOS path: Disable
|
|
[DEBUG] ME: me_state=0, me_state_prev=0
|
|
[DEBUG] PCI: 00:00:16.0: Disabling device
|
|
[DEBUG] PCI: 00:00:16.0 init finished in 75 msecs
|
|
[DEBUG] PCI: 00:00:19.0 init
|
|
[DEBUG] PCI: 00:00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00:1a.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1b.0 init
|
|
[DEBUG] Azalia: base = 0xdfbdc000
|
|
[DEBUG] Azalia: codec_mask = 09
|
|
[DEBUG] azalia_audio: initializing codec #3...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x80862805
|
|
[DEBUG] azalia_audio: - verb size: 16
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] azalia_audio: initializing codec #0...
|
|
[DEBUG] azalia_audio: - vendor/device id: 0x10ec0662
|
|
[DEBUG] azalia_audio: - verb size: 44
|
|
[DEBUG] azalia_audio: - verb loaded
|
|
[DEBUG] PCI: 00:00:1b.0 init finished in 48 msecs
|
|
[DEBUG] PCI: 00:00:1d.0 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs
|
|
[DEBUG] PCI: 00:00:1e.0 init
|
|
[DEBUG] PCI init.
|
|
[DEBUG] PCI: 00:00:1e.0 init finished in 2 msecs
|
|
[DEBUG] PCI: 00:00:1f.0 init
|
|
[DEBUG] pch: lpc_init
|
|
[INFO ] PCH: detected Q67, device id: 0x1c4e, rev id 0x5
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: ID = 0x00
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at fec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power off after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] CougarPoint PM init
|
|
[DEBUG] RTC: failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] pch_spi_init
|
|
[DEBUG] PCI: 00:00:1f.0 init finished in 56 msecs
|
|
[DEBUG] PCI: 00:00:1f.2 init
|
|
[DEBUG] SATA: Initializing...
|
|
[DEBUG] SATA: Controller in AHCI mode.
|
|
[DEBUG] ABAR: 0xdfbda000
|
|
[DEBUG] PCI: 00:00:1f.2 init finished in 10 msecs
|
|
[DEBUG] PCI: 00:00:1f.3 init
|
|
[DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1 init
|
|
[DEBUG] PNP: 002e.1 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.3 init
|
|
[DEBUG] PNP: 002e.3 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.4 init
|
|
[DEBUG] PNP: 002e.4 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.5 init
|
|
[DEBUG] PNP: 002e.5 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.6 init
|
|
[DEBUG] PNP: 002e.6 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.7 init
|
|
[DEBUG] PNP: 002e.7 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.8 init
|
|
[INFO ] NPCD378: PSU fan PWM 0x77
|
|
[DEBUG] PNP: 002e.8 init finished in 3 msecs
|
|
[DEBUG] PNP: 002e.f init
|
|
[DEBUG] PNP: 002e.f init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.15 init
|
|
[DEBUG] PNP: 002e.15 init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1c init
|
|
[DEBUG] PNP: 002e.1c init finished in 0 msecs
|
|
[DEBUG] PNP: 002e.1e init
|
|
[DEBUG] PNP: 002e.1e init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 328 / 1063 ms
|
|
[DEBUG] TPM: Startup
|
|
[DEBUG] TPM: command 0x99 returned 0x0
|
|
[DEBUG] TPM: Asserting physical presence
|
|
[DEBUG] TPM: command 0x4000000a returned 0x0
|
|
[DEBUG] TPM: command 0x65 returned 0x0
|
|
[DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
|
|
[INFO ] TPM: setup succeeded
|
|
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 66 / 29 ms
|
|
[INFO ] Finalize devices...
|
|
[DEBUG] PCI: 00:00:1f.0 final
|
|
[INFO ] Manufacturer: c2
|
|
[INFO ] SF: Detected c2 2017 with sector size 0x1000, total 0x800000
|
|
[ERROR] SF size 0x800000 does not correspond to CONFIG_ROM_SIZE 0x200000!!
|
|
[DEBUG] apm_control: Finalizing SMM.
|
|
[DEBUG] APMC done.
|
|
[INFO ] Devices finalized
|
|
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 34 ms
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x43600 size 0x2537 in mcache @0x7ffdd1b8
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7fe43000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * FACP
|
|
[DEBUG] ACPI: added table 1/32, length now 44
|
|
[DEBUG] Found 1 CPU(s) with 4 core(s) each.
|
|
[DEBUG] Supported C-states: C0 C1 C1E C3 C6
|
|
[DEBUG] PSS: 3101MHz power 95000 control 0x2200 status 0x2200
|
|
[DEBUG] PSS: 3100MHz power 95000 control 0x1f00 status 0x1f00
|
|
[DEBUG] PSS: 2800MHz power 82868 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2600MHz power 75072 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 67721 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 60619 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 53799 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 47220 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 40980 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3101MHz power 95000 control 0x2200 status 0x2200
|
|
[DEBUG] PSS: 3100MHz power 95000 control 0x1f00 status 0x1f00
|
|
[DEBUG] PSS: 2800MHz power 82868 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2600MHz power 75072 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 67721 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 60619 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 53799 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 47220 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 40980 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3101MHz power 95000 control 0x2200 status 0x2200
|
|
[DEBUG] PSS: 3100MHz power 95000 control 0x1f00 status 0x1f00
|
|
[DEBUG] PSS: 2800MHz power 82868 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2600MHz power 75072 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 67721 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 60619 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 53799 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 47220 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 40980 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PSS: 3101MHz power 95000 control 0x2200 status 0x2200
|
|
[DEBUG] PSS: 3100MHz power 95000 control 0x1f00 status 0x1f00
|
|
[DEBUG] PSS: 2800MHz power 82868 control 0x1c00 status 0x1c00
|
|
[DEBUG] PSS: 2600MHz power 75072 control 0x1a00 status 0x1a00
|
|
[DEBUG] PSS: 2400MHz power 67721 control 0x1800 status 0x1800
|
|
[DEBUG] PSS: 2200MHz power 60619 control 0x1600 status 0x1600
|
|
[DEBUG] PSS: 2000MHz power 53799 control 0x1400 status 0x1400
|
|
[DEBUG] PSS: 1800MHz power 47220 control 0x1200 status 0x1200
|
|
[DEBUG] PSS: 1600MHz power 40980 control 0x1000 status 0x1000
|
|
[INFO ] Requested C-state C7 not supported, using C6 instead
|
|
[DEBUG] Advertising ACPI C State type C1 as CPU C1
|
|
[DEBUG] Advertising ACPI C State type C2 as CPU C3
|
|
[DEBUG] Advertising ACPI C State type C3 as CPU C6
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x17b600000, len = 0xe84a00000
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0: PNP: 002e.ff
|
|
[INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 004e.0
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L010: PNP: 002e.1
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L030: PNP: 002e.3
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L040: PNP: 002e.4
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L050: PNP: 002e.5
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L060: PNP: 002e.6
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L070: PNP: 002e.7
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L080: PNP: 002e.8
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L0F0: PNP: 002e.f
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L150: PNP: 002e.15
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L1C0: PNP: 002e.1c
|
|
[DEBUG] \_SB.PCI0.LPCB.SIO0.L1E0: PNP: 002e.1e
|
|
[DEBUG] ACPI: * SSDT
|
|
[DEBUG] ACPI: added table 2/32, length now 52
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 60
|
|
[DEBUG] TCPA log created at 0x7fe33000
|
|
[DEBUG] ACPI: * TCPA
|
|
[DEBUG] ACPI: added table 4/32, length now 68
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: * APIC
|
|
[DEBUG] ACPI: added table 5/32, length now 76
|
|
[DEBUG] ACPI: * SPCR
|
|
[DEBUG] ACPI: added table 6/32, length now 84
|
|
[DEBUG] current = 7fe47d40
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 7/32, length now 92
|
|
[DEBUG] current = 7fe47e00
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 8/32, length now 100
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 20032 bytes.
|
|
[DEBUG] smbios_write_tables: 7fe2b000
|
|
[DEBUG] SMBIOS firmware version is set to coreboot_version: '24.12-869-g92d77dd2e385-dirty'
|
|
[INFO ] Create SMBIOS type 16
|
|
[INFO ] Create SMBIOS type 17
|
|
[INFO ] Create SMBIOS type 20
|
|
[INFO ] Root Device (HP HP Compaq 8200 Elite SFF PC)
|
|
[DEBUG] SMBIOS tables: 1046 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum ff8
|
|
[DEBUG] Writing coreboot table at 0x7fe67000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED
|
|
[DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
|
|
[DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED
|
|
[DEBUG] 5. 0000000000100000-000000001fffffff: RAM
|
|
[DEBUG] 6. 0000000020000000-00000000201fffff: RESERVED
|
|
[DEBUG] 7. 0000000020200000-000000003fffffff: RAM
|
|
[DEBUG] 8. 0000000040000000-00000000401fffff: RESERVED
|
|
[DEBUG] 9. 0000000040200000-000000007fe2afff: RAM
|
|
[DEBUG] 10. 000000007fe2b000-000000007fe82fff: CONFIGURATION TABLES
|
|
[DEBUG] 11. 000000007fe83000-000000007ffcdfff: RAMSTAGE
|
|
[DEBUG] 12. 000000007ffce000-000000007fffffff: CONFIGURATION TABLES
|
|
[DEBUG] 13. 0000000080000000-00000000829fffff: RESERVED
|
|
[DEBUG] 14. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 15. 00000000fed40000-00000000fed44fff: RESERVED
|
|
[DEBUG] 16. 00000000fed90000-00000000fed91fff: RESERVED
|
|
[DEBUG] 17. 0000000100000000-000000017b5fffff: RAM
|
|
[DEBUG] Wrote coreboot table at: 0x7fe67000, 0x45c bytes, checksum bbd7
|
|
[DEBUG] coreboot table: 1140 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7ffde000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7ffdd000 0x00000344
|
|
[DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910
|
|
[DEBUG] MEM INFO 5. 0x7ffdb000 0x00000f48
|
|
[DEBUG] AFTER CAR 6. 0x7ffce000 0x0000d000
|
|
[DEBUG] RAMSTAGE 7. 0x7fe82000 0x0014c000
|
|
[DEBUG] SMM BACKUP 8. 0x7fe72000 0x00010000
|
|
[DEBUG] IGD OPREGION 9. 0x7fe6f000 0x00003000
|
|
[DEBUG] COREBOOT 10. 0x7fe67000 0x00008000
|
|
[DEBUG] ACPI 11. 0x7fe43000 0x00024000
|
|
[DEBUG] TCPA TCGLOG12. 0x7fe33000 0x00010000
|
|
[DEBUG] SMBIOS 13. 0x7fe2b000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7fffeb20 0x000000e0
|
|
[DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8
|
|
[DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 757 ms
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x4c440 size 0x11c5f in mcache @0x7ffdd280
|
|
[DEBUG] Checking segment from ROM address 0xffe8c66c
|
|
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
|
|
[DEBUG] Checking segment from ROM address 0xffe8c688
|
|
[DEBUG] Loading segment from ROM address 0xffe8c66c
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x000de1a0 memsize 0x21e60 srcaddr 0xffe8c6a4 filesize 0x11c27
|
|
[DEBUG] Loading Segment: addr: 0x000de1a0 memsz: 0x0000000000021e60 filesz: 0x0000000000011c27
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xffe8c688
|
|
[DEBUG] Entry Point 0x000fd246
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 22 / 65 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x000fd246(0x7fe67000)
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
|
|
BUILD: gcc: (coreboot toolchain v2025-01-29_cdcd580bce) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
|
|
BUILD: gcc: (coreboot toolchain v2025-01-29_cdcd580bce) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
Found coreboot cbmem console @ 7ffde000
|
|
Found mainboard HP HP Compaq 8200 Elite SFF PC
|
|
Relocating init from 0x000df900 to 0x7ee1dbc0 (size 54080)
|
|
Found CBFS header at 0xffe4022c
|
|
multiboot: eax=7febd85c, ebx=7febd824
|
|
Found 11 PCI devices (max PCI bus is 02)
|
|
Copying SMBIOS from 0x7fe2b000 to 0x000f5b40
|
|
Copying SMBIOS 3.0 from 0x7fe2b020 to 0x000f5b20
|
|
Copying ACPI RSDP from 0x7fe43000 to 0x000f5af0
|
|
table(50434146)=0x7fe457d0 (via xsdt)
|
|
Using pmtimer, ioport 0x508
|
|
table(41504354)=0x7fe47c20 (via xsdt)
|
|
Scan for VGA option rom
|
|
Running option rom at c000:0003
|
|
Start SeaVGABIOS (version rel-1.16.3-0-ga6ed6b70)
|
|
VGABUILD: gcc: (coreboot toolchain v2025-01-29_cdcd580bce) 14.2.0 binutils: (GNU Binutils) 2.43.1
|
|
enter vga_post:
|
|
a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000
|
|
si=00000000 di=000066e0 bp=00000000 sp=00006da2 cs=f000 ip=cff4 f=0000
|
|
coreboot vga init
|
|
Did not find coreboot framebuffer - assuming EGA text
|
|
Attempting to allocate 512 bytes lowmem via pmm call to f000:d06c
|
|
pmm call arg1=0
|
|
VGA stack allocated at ec180
|
|
Hooking hardware timer irq (old=f000fea5 new=c0003ef8)
|
|
Turning on vga text mode console
|
|
set VGA mode 3
|
|
SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
|
|
EHCI init on dev 00:1a.0 (regs=0xdfbd9020)
|
|
EHCI init on dev 00:1d.0 (regs=0xdfbd8020)
|
|
AHCI controller at 00:1f.2, iobase 0xdfbda000, irq 11
|
|
Searching bootorder for: HALT
|
|
Found 1 lpt ports
|
|
Found 1 serial ports
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0
|
|
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@1/disk@0
|
|
Got ps2 nak (status=51)
|
|
AHCI/1: registering: "DVD/CD [AHCI/1: hp DVD A DH16ABSH ATAPI-8 DVD/CD]"
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@4/disk@0
|
|
AHCI/4: Set transfer mode to UDMA-6
|
|
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@4/disk@0
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AHCI/4: registering: "AHCI/4: ST500VT000-1DK142 ATA-8 Hard-Disk (465 GiBytes)"
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ehci_wait_td error - status=80010d40
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Searching bootorder for: /pci@i0cf8/usb@1a/hub@1/storage@6/*@0/*@0,0
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Searching bootorder for: /pci@i0cf8/usb@1a/hub@1/usb-*@6
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USB MSC vendor='JetFlash' product='Transcend 8GB' rev='8.07' type=0 removable=1
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USB MSC blksize=512 sectors=15687680
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USB keyboard initialized
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USB mouse initialized
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Initialized USB HUB (3 ports used)
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Initialized USB HUB (0 ports used)
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All threads complete.
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Scan for option roms
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Press ESC for boot menu.
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Select boot device:
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1. DVD/CD [AHCI/1: hp DVD A DH16ABSH ATAPI-8 DVD/CD]
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2. AHCI/4: ST500VT000-1DK142 ATA-8 Hard-Disk (465 GiBytes)
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3. USB MSC Drive JetFlash Transcend 8GB 8.07
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t. TPM Configuration
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