coreboot

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## ##

## CHIPSEC: Platform Hardware Security Assessment Framework ##

## ##

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[CHIPSEC] Version : 1.13.9

[CHIPSEC] Arguments: -m chipsec.modules.common.bios_smi -dv

[*] [DEBUG] [helper] Linux Helper created

[*] [DEBUG] Module /dev/chipsec loaded successfully

[*] [DEBUG] [helper] Linux Helper started/loaded

[*] [HAL] [cpuid] in: EAX=0x00000001, ECX=0x00000000

[*] [HAL] [cpuid] out: EAX=0x000806EA, EBX=0x00100800, ECX=0x7FFAFBFF, EDX=0xBFEBFBFF

[*] [DEBUG] [*] Loading device buses..

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/common.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] + HOSTCTRL : {'name': 'HOSTCTRL', 'bus': [0], 'dev': 0, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + PEG10 : {'name': 'PEG10', 'bus': [0], 'dev': 1, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + PEG11 : {'name': 'PEG11', 'bus': [0], 'dev': 1, 'fun': 1, 'vid': 32902}

[*] [DEBUG] + PEG12 : {'name': 'PEG12', 'bus': [0], 'dev': 1, 'fun': 2, 'vid': 32902}

[*] [DEBUG] + IGD : {'name': 'IGD', 'bus': [0], 'dev': 2, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + HDAUDIO : {'name': 'HDAUDIO', 'bus': [0], 'dev': 3, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + XHCI : {'name': 'XHCI', 'bus': [0], 'dev': 20, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + MEI1 : {'name': 'MEI1', 'bus': [0], 'dev': 22, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + MEI2 : {'name': 'MEI2', 'bus': [0], 'dev': 22, 'fun': 1, 'vid': 32902}

[*] [DEBUG] + IDER : {'name': 'IDER', 'bus': [0], 'dev': 22, 'fun': 2, 'vid': 32902}

[*] [DEBUG] + KT : {'name': 'KT', 'bus': [0], 'dev': 22, 'fun': 3, 'vid': 32902}

[*] [DEBUG] + GBE : {'name': 'GBE', 'bus': [0], 'dev': 25, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + EHCI2 : {'name': 'EHCI2', 'bus': [0], 'dev': 26, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + AUDIO : {'name': 'AUDIO', 'bus': [0], 'dev': 27, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + PCIE1 : {'name': 'PCIE1', 'bus': [0], 'dev': 28, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + PCIE2 : {'name': 'PCIE2', 'bus': [0], 'dev': 28, 'fun': 1, 'vid': 32902}

[*] [DEBUG] + PCIE3 : {'name': 'PCIE3', 'bus': [0], 'dev': 28, 'fun': 2, 'vid': 32902}

[*] [DEBUG] + PCIE4 : {'name': 'PCIE4', 'bus': [0], 'dev': 28, 'fun': 3, 'vid': 32902}

[*] [DEBUG] + PCIE5 : {'name': 'PCIE5', 'bus': [0], 'dev': 28, 'fun': 4, 'vid': 32902}

[*] [DEBUG] + PCIE6 : {'name': 'PCIE6', 'bus': [0], 'dev': 28, 'fun': 5, 'vid': 32902}

[*] [DEBUG] + PCIE7 : {'name': 'PCIE7', 'bus': [0], 'dev': 28, 'fun': 6, 'vid': 32902}

[*] [DEBUG] + PCIE8 : {'name': 'PCIE8', 'bus': [0], 'dev': 28, 'fun': 7, 'vid': 32902}

[*] [DEBUG] + EHCI1 : {'name': 'EHCI1', 'bus': [0], 'dev': 29, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + LPC : {'name': 'LPC', 'bus': [0], 'dev': 31, 'fun': 0, 'vid': 32902}

[*] [DEBUG] + SATA1 : {'name': 'SATA1', 'bus': [0], 'dev': 31, 'fun': 2, 'vid': 32902}

[*] [DEBUG] + SMBUS : {'name': 'SMBUS', 'bus': [0], 'dev': 31, 'fun': 3, 'vid': 32902}

[*] [DEBUG] + SATA2 : {'name': 'SATA2', 'bus': [0], 'dev': 31, 'fun': 5, 'vid': 32902}

[*] [DEBUG] + THERMAL : {'name': 'THERMAL', 'bus': [0], 'dev': 31, 'fun': 6, 'vid': 32902}

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] + PXPEPBAR : {'name': 'PXPEPBAR', 'bus': [0], 'dev': 0, 'fun': 0, 'reg': 64, 'width': 8, 'mask': 549755809792, 'size': 4096, 'enable_bit': '0', 'desc': 'PCI Express Egress Port Register Range'}

[*] [DEBUG] + MCHBAR : {'name': 'MCHBAR', 'bus': [0], 'dev': 0, 'fun': 0, 'reg': 72, 'width': 8, 'mask': 549755781120, 'size': 32768, 'enable_bit': '0', 'desc': 'Host Memory Mapped Register Range'}

[*] [DEBUG] + MMCFG : {'name': 'MMCFG', 'bus': [0], 'dev': 0, 'fun': 0, 'reg': 96, 'width': 8, 'mask': 549688705024, 'size': 4096, 'enable_bit': '0', 'desc': 'PCI Express Register Range'}

[*] [DEBUG] + DMIBAR : {'name': 'DMIBAR', 'bus': [0], 'dev': 0, 'fun': 0, 'reg': 104, 'width': 8, 'mask': 549755809792, 'size': 4096, 'enable_bit': '0', 'desc': 'Root Complex Register Range'}

[*] [DEBUG] + GTTMMADR : {'name': 'GTTMMADR', 'bus': [0], 'dev': 2, 'fun': 0, 'reg': 16, 'width': 8, 'mask': 549751619584, 'desc': 'Graphics Translation Table Range'}

[*] [DEBUG] + GMADR : {'name': 'GMADR', 'bus': [0], 'dev': 2, 'fun': 0, 'reg': 24, 'width': 8, 'mask': 549621596160, 'desc': 'Graphics Memory Range'}

[*] [DEBUG] + HDABAR : {'name': 'HDABAR', 'bus': [0], 'dev': 3, 'fun': 0, 'reg': 16, 'width': 8, 'mask': 549755809792, 'size': 4096, 'desc': 'HD Audio Controller Register Range'}

[*] [DEBUG] + HDBAR : {'name': 'HDBAR', 'bus': [0], 'dev': 27, 'fun': 0, 'reg': 16, 'width': 8, 'mask': 549755797504, 'size': 4096, 'desc': 'PCH HD Audio Controller Register Range'}

[*] [DEBUG] + RCBA : {'name': 'RCBA', 'bus': [0], 'dev': 31, 'fun': 0, 'reg': 240, 'width': 4, 'mask': 4294950912, 'size': 16384, 'enable_bit': '0', 'desc': 'PCH Root Complex Register Range'}

[*] [DEBUG] + SPIBAR : {'name': 'SPIBAR', 'bus': [0], 'dev': 31, 'fun': 0, 'reg': 240, 'width': 4, 'mask': 4294950912, 'size': 512, 'enable_bit': '0', 'desc': 'SPI Controller Register Range', 'offset': 14336}

[*] [DEBUG] + RCBA_RTC : {'name': 'RCBA_RTC', 'bus': [0], 'dev': 31, 'fun': 0, 'reg': 240, 'width': 4, 'mask': 4294950912, 'size': 512, 'enable_bit': '0', 'desc': 'General Control Register Range', 'offset': 13312}

[*] [DEBUG] + VTBAR : {'name': 'VTBAR', 'register': 'VTBAR', 'base_field': 'Base', 'size': 4096, 'enable_field': 'Enable', 'desc': 'Intel VT-d Register Register Range'}

[*] [DEBUG] + GFXVTBAR : {'name': 'GFXVTBAR', 'register': 'GFXVTBAR', 'base_field': 'Base', 'size': 4096, 'enable_field': 'Enable', 'desc': 'Intel Processor Graphics VT-d Register Range'}

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'register': 'ABASE', 'base_field': 'Base', 'size': 128, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + PMBASE : {'name': 'PMBASE', 'register': 'ABASE', 'base_field': 'Base', 'size': 128, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + TCOBASE : {'name': 'TCOBASE', 'register': 'ABASE', 'base_field': 'Base', 'size': 128, 'desc': 'TCO Base Address', 'offset': 96}

[*] [DEBUG] + GPIOBASE : {'name': 'GPIOBASE', 'register': 'GPIOBASE', 'base_field': 'Base', 'size': 128, 'desc': 'GPIO Base Address'}

[*] [DEBUG] + SMBUS_BASE : {'name': 'SMBUS_BASE', 'register': 'SMB_BASE', 'base_field': 'Base', 'size': 32, 'desc': 'SMBus Base Address'}

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] + Legacy DOS : {'name': 'Legacy DOS', 'access': 'dram', 'address': 0, 'size': 1048576, 'desc': 'Legacy DOS'}

[*] [DEBUG] + TXT : {'name': 'TXT', 'access': 'mmio', 'address': 4275175424, 'size': 131072, 'desc': 'TXT'}

[*] [DEBUG] + TPM : {'name': 'TPM', 'access': 'mmio', 'address': 4275306496, 'size': 65536, 'desc': 'TPM'}

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + PCI0.0.0_VID : {'name': 'PCI0.0.0_VID', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 0, 'size': 2, 'desc': 'Vendor ID', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_DID : {'name': 'PCI0.0.0_DID', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 2, 'size': 2, 'desc': 'Device ID', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PXPEPBAR: {'name': 'PCI0.0.0_PXPEPBAR', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 64, 'size': 8, 'desc': 'PCI Express Egress Port Base Address', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_MCHBAR : {'name': 'PCI0.0.0_MCHBAR', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 72, 'size': 8, 'desc': 'MCH Base Address', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_GGC : {'name': 'PCI0.0.0_GGC', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 80, 'size': 2, 'desc': 'Graphics Control', 'FIELDS': {'GGCLOCK': {'name': 'GGCLOCK', 'bit': 0, 'size': 1, 'desc': 'GGC Lock'}}}

[*] [DEBUG] + PCI0.0.0_DEVEN : {'name': 'PCI0.0.0_DEVEN', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 84, 'size': 4, 'desc': 'Device Enables', 'FIELDS': {'D2EN': {'name': 'D2EN', 'bit': 4, 'size': 1, 'desc': 'Device 2 Function 0 Enable'}}}

[*] [DEBUG] + PCI0.0.0_PAVPC : {'name': 'PCI0.0.0_PAVPC', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 88, 'size': 4, 'desc': 'PAVP Configuration', 'FIELDS': {'PAVPLCK': {'name': 'PAVPLCK', 'bit': 2, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_DPR : {'name': 'PCI0.0.0_DPR', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 92, 'size': 4, 'desc': 'DMA Protected Range', 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_PCIEXBAR: {'name': 'PCI0.0.0_PCIEXBAR', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 96, 'size': 8, 'desc': 'PCIe MMCFG Base Address', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_DMIBAR : {'name': 'PCI0.0.0_DMIBAR', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 104, 'size': 8, 'desc': 'DMI Base Address', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_MESEG_BASE: {'name': 'PCI0.0.0_MESEG_BASE', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 112, 'size': 8, 'desc': 'Manageability Engine Base Address Register', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_MESEG_MASK: {'name': 'PCI0.0.0_MESEG_MASK', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 120, 'size': 8, 'desc': 'Manageability Engine Limit Address Register', 'FIELDS': {'MELCK': {'name': 'MELCK', 'bit': 10, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_PAM0 : {'name': 'PCI0.0.0_PAM0', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 128, 'size': 1, 'desc': 'Programmable Attribute Map 0', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM1 : {'name': 'PCI0.0.0_PAM1', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 129, 'size': 1, 'desc': 'Programmable Attribute Map 1', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM2 : {'name': 'PCI0.0.0_PAM2', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 130, 'size': 1, 'desc': 'Programmable Attribute Map 2', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM3 : {'name': 'PCI0.0.0_PAM3', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 131, 'size': 1, 'desc': 'Programmable Attribute Map 3', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM4 : {'name': 'PCI0.0.0_PAM4', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 132, 'size': 1, 'desc': 'Programmable Attribute Map 4', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM5 : {'name': 'PCI0.0.0_PAM5', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 133, 'size': 1, 'desc': 'Programmable Attribute Map 5', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_PAM6 : {'name': 'PCI0.0.0_PAM6', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 134, 'size': 1, 'desc': 'Programmable Attribute Map 6', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_LAC : {'name': 'PCI0.0.0_LAC', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 135, 'size': 1, 'desc': 'Legacy Access Control', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_SMRAMC : {'name': 'PCI0.0.0_SMRAMC', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 136, 'size': 1, 'desc': 'System Management RAM Control', 'FIELDS': {'D_OPEN': {'name': 'D_OPEN', 'bit': 6, 'size': 1, 'desc': 'SMRAM Open'}, 'D_CLS': {'name': 'D_CLS', 'bit': 5, 'size': 1, 'desc': 'SMRAM Closed'}, 'D_LCK': {'name': 'D_LCK', 'bit': 4, 'size': 1, 'desc': 'SMRAM Locked'}, 'G_SMRAME': {'name': 'G_SMRAME', 'bit': 3, 'size': 1, 'desc': 'SMRAM Enabled'}, 'C_BASE_SEG': {'name': 'C_BASE_SEG', 'bit': 0, 'size': 3, 'desc': 'SMRAM Base Segment = 010b'}}}

[*] [DEBUG] + PCI0.0.0_REMAPBASE: {'name': 'PCI0.0.0_REMAPBASE', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 144, 'size': 8, 'desc': 'Memory Remap Base Address', 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_REMAPLIMIT: {'name': 'PCI0.0.0_REMAPLIMIT', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 152, 'size': 8, 'desc': 'Memory Remap Limit Address', 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_TOM : {'name': 'PCI0.0.0_TOM', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 160, 'size': 8, 'desc': 'Top of Memory', 'FIELDS': {'TOM': {'name': 'TOM', 'bit': 20, 'size': 19, 'desc': 'Top of Memory'}, 'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_TOUUD : {'name': 'PCI0.0.0_TOUUD', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 168, 'size': 8, 'desc': 'Top of Upper Usable DRAM', 'FIELDS': {'TOUUD': {'name': 'TOUUD', 'bit': 20, 'size': 19, 'desc': 'Top of Upper Usable DRAM'}, 'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_BDSM : {'name': 'PCI0.0.0_BDSM', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 176, 'size': 4, 'desc': 'Base of Graphics Stolen Memory', 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_BGSM : {'name': 'PCI0.0.0_BGSM', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 180, 'size': 4, 'desc': 'Base of GTT Stolen Memory', 'FIELDS': {'BGSM': {'name': 'BGSM', 'bit': 20, 'size': 12, 'desc': 'Base of GTT Stolen Memory'}, 'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_TSEGMB : {'name': 'PCI0.0.0_TSEGMB', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 184, 'size': 4, 'desc': 'TSEG Memory Base', 'FIELDS': {'TSEGMB': {'name': 'TSEGMB', 'bit': 20, 'size': 12, 'desc': 'TSEG Memory Base'}, 'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_TOLUD : {'name': 'PCI0.0.0_TOLUD', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 188, 'size': 4, 'desc': 'Top of Low Usable DRAM', 'FIELDS': {'TOLUD': {'name': 'TOLUD', 'bit': 20, 'size': 12, 'desc': 'Top of Lower Usable DRAM'}, 'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}}}

[*] [DEBUG] + PCI0.0.0_SKPD : {'name': 'PCI0.0.0_SKPD', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 220, 'size': 4, 'desc': 'Scratchpad Data', 'FIELDS': {}}

[*] [DEBUG] + PCI0.0.0_CAPID0_A: {'name': 'PCI0.0.0_CAPID0_A', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 228, 'size': 4, 'desc': 'Capabilities A', 'FIELDS': {'VTDD': {'name': 'VTDD', 'bit': 23, 'size': 1, 'desc': 'VTD Disable'}, 'IGD': {'name': 'IGD', 'bit': 11, 'size': 1, 'desc': 'Internal Graphics Disable'}}}

[*] [DEBUG] + PCI0.0.0_CAPID0_B: {'name': 'PCI0.0.0_CAPID0_B', 'type': 'pcicfg', 'device': 'HOSTCTRL', 'offset': 232, 'size': 4, 'desc': 'Capabilities B', 'FIELDS': {}}

[*] [DEBUG] + PCI0.2.0_DID : {'name': 'PCI0.2.0_DID', 'type': 'pcicfg', 'device': 'IGD', 'offset': 2, 'size': 2, 'desc': 'Device Identification Number', 'FIELDS': {}}

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'type': 'pcicfg', 'device': 'LPC', 'offset': 64, 'size': 4, 'desc': 'ACPI Base Address', 'FIELDS': {'Base': {'name': 'Base', 'bit': 7, 'size': 9, 'desc': 'Base Address'}}}

[*] [DEBUG] + GPIOBASE : {'name': 'GPIOBASE', 'type': 'pcicfg', 'device': 'LPC', 'offset': 72, 'size': 4, 'desc': 'GPIO Base Address', 'FIELDS': {'Base': {'name': 'Base', 'bit': 7, 'size': 9, 'desc': 'Base Address'}}}

[*] [DEBUG] + GC : {'name': 'GC', 'type': 'pcicfg', 'device': 'LPC', 'offset': 76, 'size': 1, 'desc': 'GPIO Control', 'FIELDS': {'GLE': {'name': 'GLE', 'bit': 0, 'size': 1, 'desc': 'GPIO Lockdown Enable'}, 'EN': {'name': 'EN', 'bit': 4, 'size': 1, 'desc': 'GPIO Enable'}}}

[*] [DEBUG] + GEN_PMCON_1 : {'name': 'GEN_PMCON_1', 'type': 'pcicfg', 'device': 'LPC', 'offset': 160, 'size': 2, 'desc': 'General PM Configuration 1', 'FIELDS': {'SMI_LOCK': {'name': 'SMI_LOCK', 'bit': 4, 'size': 1, 'desc': 'SMI_LOCK'}}}

[*] [DEBUG] + BC : {'name': 'BC', 'type': 'pcicfg', 'device': 'LPC', 'offset': 220, 'size': 1, 'desc': 'BIOS Control', 'FIELDS': {'BIOSWE': {'name': 'BIOSWE', 'bit': 0, 'size': 1, 'desc': 'BIOS Write Enable'}, 'BLE': {'name': 'BLE', 'bit': 1, 'size': 1, 'desc': 'BIOS Lock Enable'}, 'SRC': {'name': 'SRC', 'bit': 2, 'size': 2, 'desc': 'SPI Read Configuration'}, 'TSS': {'name': 'TSS', 'bit': 4, 'size': 1, 'desc': 'Top Swap Status'}, 'SMM_BWP': {'name': 'SMM_BWP', 'bit': 5, 'size': 1, 'desc': 'SMM BIOS Write Protection'}}}

[*] [DEBUG] + SMBUS_VID : {'name': 'SMBUS_VID', 'type': 'pcicfg', 'device': 'SMBUS', 'offset': 0, 'size': 2, 'desc': 'VID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_DID : {'name': 'SMBUS_DID', 'type': 'pcicfg', 'device': 'SMBUS', 'offset': 2, 'size': 2, 'desc': 'DID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_CMD : {'name': 'SMBUS_CMD', 'type': 'pcicfg', 'device': 'SMBUS', 'offset': 4, 'size': 2, 'desc': 'CMD', 'FIELDS': {}}

[*] [DEBUG] + SMB_BASE : {'name': 'SMB_BASE', 'type': 'pcicfg', 'device': 'SMBUS', 'offset': 32, 'size': 4, 'desc': 'SMBus Base Address', 'FIELDS': {'Base': {'name': 'Base', 'bit': 5, 'size': 11, 'desc': 'Base Address'}}}

[*] [DEBUG] + SMBUS_HCFG : {'name': 'SMBUS_HCFG', 'type': 'pcicfg', 'device': 'SMBUS', 'offset': 64, 'size': 1, 'desc': 'Host Configuration', 'FIELDS': {'HST_EN': {'name': 'HST_EN', 'bit': 0, 'size': 1, 'desc': 'HST_EN'}, 'SMB_SMI_EN': {'name': 'SMB_SMI_EN', 'bit': 1, 'size': 1, 'desc': 'SMB_SMI_EN'}, 'I2C_EN': {'name': 'I2C_EN', 'bit': 2, 'size': 1, 'desc': 'I2C_EN'}, 'SSRESET': {'name': 'SSRESET', 'bit': 3, 'size': 1, 'desc': 'SSRESET'}, 'SPD_WD': {'name': 'SPD_WD', 'bit': 4, 'size': 1, 'desc': 'SPD_WD'}}}

[*] [DEBUG] + HFS : {'name': 'HFS', 'type': 'pcicfg', 'device': 'MEI1', 'offset': 64, 'size': 4, 'desc': 'ME Host Firmware Status', 'FIELDS': {'MFG_MODE': {'name': 'MFG_MODE', 'bit': 4, 'size': 1, 'desc': 'ME Manufacturing Mode'}, 'FW_INIT_COMPLETE': {'name': 'FW_INIT_COMPLETE', 'bit': 9, 'size': 1, 'desc': 'ME Firmware Initialization Complete'}, 'UPDATE_IN_PROGRESS': {'name': 'UPDATE_IN_PROGRESS', 'bit': 11, 'size': 1, 'desc': 'ME Update In Progress'}}}

[*] [DEBUG] + BFPR : {'name': 'BFPR', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 0, 'size': 4, 'desc': 'BIOS Flash Primary Region Register (= FREG1)', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'BIOS Flash Primary Region Base'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'BIOS Flash Primary Region Limit'}}}

[*] [DEBUG] + HSFS : {'name': 'HSFS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 4, 'size': 2, 'desc': 'Hardware Sequencing Flash Status Register', 'FIELDS': {'FDONE': {'name': 'FDONE', 'bit': 0, 'size': 1, 'desc': 'Flash Cycle Done'}, 'FCERR': {'name': 'FCERR', 'bit': 1, 'size': 1, 'desc': 'Flash Cycle Error'}, 'AEL': {'name': 'AEL', 'bit': 2, 'size': 1, 'desc': 'Access Error Log'}, 'BERASE': {'name': 'BERASE', 'bit': 3, 'size': 2, 'desc': 'Block/Sector Erase Size'}, 'SCIP': {'name': 'SCIP', 'bit': 5, 'size': 1, 'desc': 'SPI cycle in progress'}, 'FDOPSS': {'name': 'FDOPSS', 'bit': 13, 'size': 1, 'desc': 'Flash Descriptor Override Pin-Strap Status'}, 'FDV': {'name': 'FDV', 'bit': 14, 'size': 1, 'desc': 'Flash Descriptor Valid'}, 'FLOCKDN': {'name': 'FLOCKDN', 'bit': 15, 'size': 1, 'desc': 'Flash Configuration Lock-Down'}}}

[*] [DEBUG] + HSFC : {'name': 'HSFC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 6, 'size': 2, 'desc': 'Hardware Sequencing Flash Control Register', 'FIELDS': {'FGO': {'name': 'FGO', 'bit': 0, 'size': 1, 'desc': 'Flash Cycle GO'}, 'FCYCLE': {'name': 'FCYCLE', 'bit': 1, 'size': 2, 'desc': 'Flash Cycle'}, 'FDBC': {'name': 'FDBC', 'bit': 8, 'size': 6, 'desc': 'Flash Data Byte Count, Count = FDBC + 1'}, 'FSMIE': {'name': 'FSMIE', 'bit': 15, 'size': 1, 'desc': 'Flash SPI SMI Enable'}}}

[*] [DEBUG] + FADDR : {'name': 'FADDR', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 8, 'size': 4, 'desc': 'Flash Address Register', 'FIELDS': {}}

[*] [DEBUG] + FDATA0 : {'name': 'FDATA0', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 16, 'size': 4, 'desc': 'Flash Data 0', 'FIELDS': {}}

[*] [DEBUG] + FDATA1 : {'name': 'FDATA1', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 20, 'size': 4, 'desc': 'Flash Data 1', 'FIELDS': {}}

[*] [DEBUG] + FDATA2 : {'name': 'FDATA2', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 24, 'size': 4, 'desc': 'Flash Data 2', 'FIELDS': {}}

[*] [DEBUG] + FDATA3 : {'name': 'FDATA3', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 28, 'size': 4, 'desc': 'Flash Data 3', 'FIELDS': {}}

[*] [DEBUG] + FDATA4 : {'name': 'FDATA4', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 32, 'size': 4, 'desc': 'Flash Data 4', 'FIELDS': {}}

[*] [DEBUG] + FDATA5 : {'name': 'FDATA5', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 36, 'size': 4, 'desc': 'Flash Data 5', 'FIELDS': {}}

[*] [DEBUG] + FDATA6 : {'name': 'FDATA6', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 40, 'size': 4, 'desc': 'Flash Data 6', 'FIELDS': {}}

[*] [DEBUG] + FDATA7 : {'name': 'FDATA7', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 44, 'size': 4, 'desc': 'Flash Data 7', 'FIELDS': {}}

[*] [DEBUG] + FDATA8 : {'name': 'FDATA8', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 48, 'size': 4, 'desc': 'Flash Data 8', 'FIELDS': {}}

[*] [DEBUG] + FDATA9 : {'name': 'FDATA9', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 52, 'size': 4, 'desc': 'Flash Data 9', 'FIELDS': {}}

[*] [DEBUG] + FDATA10 : {'name': 'FDATA10', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 56, 'size': 4, 'desc': 'Flash Data 10', 'FIELDS': {}}

[*] [DEBUG] + FDATA11 : {'name': 'FDATA11', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 60, 'size': 4, 'desc': 'Flash Data 11', 'FIELDS': {}}

[*] [DEBUG] + FDATA12 : {'name': 'FDATA12', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 64, 'size': 4, 'desc': 'Flash Data 12', 'FIELDS': {}}

[*] [DEBUG] + FDATA13 : {'name': 'FDATA13', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 68, 'size': 4, 'desc': 'Flash Data 13', 'FIELDS': {}}

[*] [DEBUG] + FDATA14 : {'name': 'FDATA14', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 72, 'size': 4, 'desc': 'Flash Data 14', 'FIELDS': {}}

[*] [DEBUG] + FDATA15 : {'name': 'FDATA15', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 76, 'size': 4, 'desc': 'Flash Data 15', 'FIELDS': {}}

[*] [DEBUG] + FRAP : {'name': 'FRAP', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 80, 'size': 4, 'desc': 'SPI Flash Regions Access Permissions Register', 'FIELDS': {'BRRA': {'name': 'BRRA', 'bit': 0, 'size': 8, 'desc': 'BIOS Region Read Access'}, 'BRWA': {'name': 'BRWA', 'bit': 8, 'size': 8, 'desc': 'BIOS Region Write Access'}, 'BMRAG': {'name': 'BMRAG', 'bit': 16, 'size': 8, 'desc': 'BIOS Master Read Access Grant'}, 'BMWAG': {'name': 'BMWAG', 'bit': 24, 'size': 8, 'desc': 'BIOS Master Write Access Grant'}}}

[*] [DEBUG] + FREG0_FLASHD : {'name': 'FREG0_FLASHD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 84, 'size': 4, 'desc': 'Flash Region 0 (Flash Descriptor)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG1_BIOS : {'name': 'FREG1_BIOS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 88, 'size': 4, 'desc': 'Flash Region 1 (BIOS)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG2_ME : {'name': 'FREG2_ME', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 92, 'size': 4, 'desc': 'Flash Region 2 (ME)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG3_GBE : {'name': 'FREG3_GBE', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 96, 'size': 4, 'desc': 'Flash Region 3 (GBe)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG4_PD : {'name': 'FREG4_PD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 100, 'size': 4, 'desc': 'Flash Region 4 (Platform Data)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG5 : {'name': 'FREG5', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 104, 'size': 4, 'desc': 'Flash Region 5', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG6 : {'name': 'FREG6', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 108, 'size': 4, 'desc': 'Flash Region 6', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 12, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 12, 'desc': 'Region Limit'}}}

[*] [DEBUG] + PR0 : {'name': 'PR0', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 116, 'size': 4, 'desc': 'Protected Range 0', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'Protected Range Base'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'Read Protection Enabled'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'Protected Range Limit'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'Write Protection Enabled'}}}

[*] [DEBUG] + PR1 : {'name': 'PR1', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 120, 'size': 4, 'desc': 'Protected Range 1', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'Protected Range Base'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'Read Protection Enabled'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'Protected Range Limit'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'Write Protection Enabled'}}}

[*] [DEBUG] + PR2 : {'name': 'PR2', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 124, 'size': 4, 'desc': 'Protected Range 2', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'Protected Range Base'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'Read Protection Enabled'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'Protected Range Limit'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'Write Protection Enabled'}}}

[*] [DEBUG] + PR3 : {'name': 'PR3', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 128, 'size': 4, 'desc': 'Protected Range 3', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'Protected Range Base'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'Read Protection Enabled'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'Protected Range Limit'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'Write Protection Enabled'}}}

[*] [DEBUG] + PR4 : {'name': 'PR4', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 132, 'size': 4, 'desc': 'Protected Range 4', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 13, 'desc': 'Protected Range Base'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'Read Protection Enabled'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 13, 'desc': 'Protected Range Limit'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'Write Protection Enabled'}}}

[*] [DEBUG] + PREOP : {'name': 'PREOP', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 148, 'size': 2, 'desc': 'Prefix Opcode Configuration Register', 'FIELDS': {'PREOP0': {'name': 'PREOP0', 'bit': 0, 'size': 8, 'desc': 'Prefix Opcode 0'}, 'PREOP1': {'name': 'PREOP1', 'bit': 8, 'size': 8, 'desc': 'Prefix Opcode 1'}}}

[*] [DEBUG] + OPTYPE : {'name': 'OPTYPE', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 150, 'size': 2, 'desc': 'Opcode Type Configuration Register', 'FIELDS': {'OPTYPE0': {'name': 'OPTYPE0', 'bit': 0, 'size': 2, 'desc': 'Opcode Type 0'}, 'OPTYPE1': {'name': 'OPTYPE1', 'bit': 2, 'size': 2, 'desc': 'Opcode Type 1'}, 'OPTYPE2': {'name': 'OPTYPE2', 'bit': 4, 'size': 2, 'desc': 'Opcode Type 2'}, 'OPTYPE3': {'name': 'OPTYPE3', 'bit': 6, 'size': 2, 'desc': 'Opcode Type 3'}, 'OPTYPE4': {'name': 'OPTYPE4', 'bit': 8, 'size': 2, 'desc': 'Opcode Type 4'}, 'OPTYPE5': {'name': 'OPTYPE5', 'bit': 10, 'size': 2, 'desc': 'Opcode Type 5'}, 'OPTYPE6': {'name': 'OPTYPE6', 'bit': 12, 'size': 2, 'desc': 'Opcode Type 6'}, 'OPTYPE7': {'name': 'OPTYPE7', 'bit': 14, 'size': 2, 'desc': 'Opcode Type 7'}}}

[*] [DEBUG] + OPMENU : {'name': 'OPMENU', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 152, 'size': 8, 'desc': 'Opcode Menu Configuration Register', 'FIELDS': {'OPCODE0': {'name': 'OPCODE0', 'bit': 0, 'size': 8, 'desc': 'Allowable Opcode 0'}, 'OPCODE1': {'name': 'OPCODE1', 'bit': 8, 'size': 8, 'desc': 'Allowable Opcode 1'}, 'OPCODE2': {'name': 'OPCODE2', 'bit': 16, 'size': 8, 'desc': 'Allowable Opcode 2'}, 'OPCODE3': {'name': 'OPCODE3', 'bit': 24, 'size': 8, 'desc': 'Allowable Opcode 3'}, 'OPCODE4': {'name': 'OPCODE4', 'bit': 32, 'size': 8, 'desc': 'Allowable Opcode 4'}, 'OPCODE5': {'name': 'OPCODE5', 'bit': 40, 'size': 8, 'desc': 'Allowable Opcode 5'}, 'OPCODE6': {'name': 'OPCODE6', 'bit': 48, 'size': 8, 'desc': 'Allowable Opcode 6'}, 'OPCODE7': {'name': 'OPCODE7', 'bit': 56, 'size': 8, 'desc': 'Allowable Opcode 7'}}}

[*] [DEBUG] + OPMENU_LO : {'name': 'OPMENU_LO', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 152, 'size': 4, 'desc': 'Opcode Menu Configuration Register Low', 'FIELDS': {'OPCODE0': {'name': 'OPCODE0', 'bit': 0, 'size': 8, 'desc': 'Allowable Opcode 0'}, 'OPCODE1': {'name': 'OPCODE1', 'bit': 8, 'size': 8, 'desc': 'Allowable Opcode 1'}, 'OPCODE2': {'name': 'OPCODE2', 'bit': 16, 'size': 8, 'desc': 'Allowable Opcode 2'}, 'OPCODE3': {'name': 'OPCODE3', 'bit': 24, 'size': 8, 'desc': 'Allowable Opcode 3'}}}

[*] [DEBUG] + OPMENU_HI : {'name': 'OPMENU_HI', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 156, 'size': 4, 'desc': 'Opcode Menu Configuration Register High', 'FIELDS': {'OPCODE4': {'name': 'OPCODE4', 'bit': 0, 'size': 8, 'desc': 'Allowable Opcode 4'}, 'OPCODE5': {'name': 'OPCODE5', 'bit': 8, 'size': 8, 'desc': 'Allowable Opcode 5'}, 'OPCODE6': {'name': 'OPCODE6', 'bit': 16, 'size': 8, 'desc': 'Allowable Opcode 6'}, 'OPCODE7': {'name': 'OPCODE7', 'bit': 24, 'size': 8, 'desc': 'Allowable Opcode 7'}}}

[*] [DEBUG] + FDOC : {'name': 'FDOC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 176, 'size': 4, 'desc': 'Flash Descriptor Observability Control Register', 'FIELDS': {'FDSI': {'name': 'FDSI', 'bit': 2, 'size': 10, 'desc': 'Flash Descriptor Section Index'}, 'FDSS': {'name': 'FDSS', 'bit': 12, 'size': 3, 'desc': 'Flash Descriptor Section Select'}}}

[*] [DEBUG] + FDOD : {'name': 'FDOD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 180, 'size': 4, 'desc': 'Flash Descriptor Observability Data Register', 'FIELDS': {'FDSD': {'name': 'FDSD', 'bit': 0, 'size': 32, 'desc': 'Flash Descriptor Section Data'}}}

[*] [DEBUG] + LVSCC : {'name': 'LVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 196, 'size': 4, 'desc': 'Host Lower Vendor Specific Component Capabilities', 'FIELDS': {'LBES': {'name': 'LBES', 'bit': 0, 'size': 2, 'desc': 'Lower Block/Sector Erase Size'}, 'LWG': {'name': 'LWG', 'bit': 2, 'size': 1, 'desc': 'Lower Write Granularity'}, 'LWSR': {'name': 'LWSR', 'bit': 3, 'size': 1, 'desc': 'Lower Write Status Required'}, 'LWEWS': {'name': 'LWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'LEO': {'name': 'LEO', 'bit': 8, 'size': 8, 'desc': 'Lower Erase Opcode'}}}

[*] [DEBUG] + UVSCC : {'name': 'UVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 200, 'size': 4, 'desc': 'Host Upper Vendor Specific Component Capabilities', 'FIELDS': {'UBES': {'name': 'UBES', 'bit': 0, 'size': 2, 'desc': 'Upper Block/Sector Erase Size'}, 'UWG': {'name': 'UWG', 'bit': 2, 'size': 1, 'desc': 'Upper Write Granularity'}, 'UWSR': {'name': 'UWSR', 'bit': 3, 'size': 1, 'desc': 'Upper Write Status Required'}, 'UWEWS': {'name': 'UWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'UEO': {'name': 'UEO', 'bit': 8, 'size': 8, 'desc': 'Upper Erase Opcode'}}}

[*] [DEBUG] + BIOS_PTINX : {'name': 'BIOS_PTINX', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 204, 'size': 4, 'desc': 'Parameter Table Index', 'FIELDS': {}}

[*] [DEBUG] + BIOS_PTDATA : {'name': 'BIOS_PTDATA', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 208, 'size': 4, 'desc': 'Parameter Table Data', 'FIELDS': {}}

[*] [DEBUG] + FLMAP0 : {'name': 'FLMAP0', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 20, 'size': 4, 'desc': 'Flash Map 0 Register', 'FIELDS': {'FCBA': {'name': 'FCBA', 'bit': 0, 'size': 8, 'desc': 'Flash Component Base Address'}, 'NC': {'name': 'NC', 'bit': 8, 'size': 2, 'desc': 'Number of Components'}, 'FRBA': {'name': 'FRBA', 'bit': 16, 'size': 8, 'desc': 'Flash Region Base Address'}, 'NR': {'name': 'NR', 'bit': 24, 'size': 3, 'desc': 'Number of Regions'}}}

[*] [DEBUG] + FLMAP1 : {'name': 'FLMAP1', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 24, 'size': 4, 'desc': 'Flash Map 1 Register', 'FIELDS': {'FMBA': {'name': 'FMBA', 'bit': 0, 'size': 8, 'desc': 'Flash Master Base Address'}, 'NM': {'name': 'NM', 'bit': 8, 'size': 2, 'desc': 'Number of Masters'}, 'FPSBA': {'name': 'FPSBA', 'bit': 16, 'size': 8, 'desc': 'Flash PCH Strap Base Address'}, 'PSL': {'name': 'PSL', 'bit': 24, 'size': 8, 'desc': 'PCH Strap Length'}}}

[*] [DEBUG] + FLMAP2 : {'name': 'FLMAP2', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 28, 'size': 4, 'desc': 'Flash Map 2 Register', 'FIELDS': {'FCPUSBA': {'name': 'FCPUSBA', 'bit': 0, 'size': 8, 'desc': 'Flash CPU Strap Base Address'}, 'CPUSL': {'name': 'CPUSL', 'bit': 8, 'size': 8, 'desc': 'Processor Strap Length'}, 'ICCRIBA': {'name': 'ICCRIBA', 'bit': 16, 'size': 8, 'desc': 'ICC Register Init Base Address'}}}

[*] [DEBUG] + FLREG0 : {'name': 'FLREG0', 'type': 'mmio', 'bar': 'FRBA', 'offset': 0, 'size': 4, 'desc': 'Flash Region 0 (Flash Descriptor) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 13, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 13, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG1 : {'name': 'FLREG1', 'type': 'mmio', 'bar': 'FRBA', 'offset': 4, 'size': 4, 'desc': 'Flash Region 1 (BIOS) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 13, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 13, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG2 : {'name': 'FLREG2', 'type': 'mmio', 'bar': 'FRBA', 'offset': 8, 'size': 4, 'desc': 'Flash Region 2 (Intel ME) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 13, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 13, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG3 : {'name': 'FLREG3', 'type': 'mmio', 'bar': 'FRBA', 'offset': 12, 'size': 4, 'desc': 'Flash Region 3 (GBe) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 13, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 13, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG4 : {'name': 'FLREG4', 'type': 'mmio', 'bar': 'FRBA', 'offset': 16, 'size': 4, 'desc': 'Flash Region 4 (Platform Data) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 13, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 13, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLMSTR1 : {'name': 'FLMSTR1', 'type': 'mmio', 'bar': 'FMBA', 'offset': 0, 'size': 4, 'desc': 'Flash Master 1', 'FIELDS': {'MRRA': {'name': 'MRRA', 'bit': 16, 'size': 8, 'desc': 'Master Region Read Access'}, 'MRWA': {'name': 'MRWA', 'bit': 24, 'size': 8, 'desc': 'Master Region Write Access'}}}

[*] [DEBUG] + RC : {'name': 'RC', 'type': 'mmio', 'bar': 'RCBA', 'offset': 13312, 'size': 4, 'desc': 'RTC Configuration', 'FIELDS': {'UE': {'name': 'UE', 'bit': 2, 'size': 1, 'desc': 'Upper 128 Byte Enable'}, 'LL': {'name': 'LL', 'bit': 3, 'size': 1, 'desc': 'Lower 128 Byte Lock'}, 'UL': {'name': 'UL', 'bit': 4, 'size': 1, 'desc': 'Upper 128 Byte Lock'}}}

[*] [DEBUG] + GCS : {'name': 'GCS', 'type': 'mmio', 'bar': 'RCBA', 'offset': 13328, 'size': 4, 'desc': 'General Control and Status', 'FIELDS': {'BILD': {'name': 'BILD', 'bit': 0, 'size': 1, 'desc': 'BIOS Interface Lock Down'}, 'BBS': {'name': 'BBS', 'bit': 10, 'size': 2, 'desc': 'Boot BIOS Straps'}}}

[*] [DEBUG] + BUC : {'name': 'BUC', 'type': 'mmio', 'bar': 'RCBA', 'offset': 13332, 'size': 4, 'desc': 'Backed Up Control', 'FIELDS': {'TS': {'name': 'TS', 'bit': 0, 'size': 1, 'desc': 'Top Swap'}}}

[*] [DEBUG] + GFXVTBAR : {'name': 'GFXVTBAR', 'type': 'mmio', 'bar': 'MCHBAR', 'offset': 21504, 'size': 8, 'desc': 'Processor Graphics VT-d MMIO Base Address', 'FIELDS': {'Enable': {'name': 'Enable', 'bit': 0, 'size': 1, 'desc': 'Enable'}, 'Base': {'name': 'Base', 'bit': 12, 'size': 27, 'desc': 'GFX VTD Base Address'}}}

[*] [DEBUG] + VTBAR : {'name': 'VTBAR', 'type': 'mmio', 'bar': 'MCHBAR', 'offset': 21520, 'size': 8, 'desc': 'VT-d MMIO Base Address', 'FIELDS': {'Enable': {'name': 'Enable', 'bit': 0, 'size': 1, 'desc': 'Enable'}, 'Base': {'name': 'Base', 'bit': 12, 'size': 27, 'desc': 'VTD Base Address'}}}

[*] [DEBUG] + RST_CNT : {'name': 'RST_CNT', 'type': 'io', 'port': 3321, 'size': 1, 'desc': 'Reset Control', 'FIELDS': {'SYS_RST': {'name': 'SYS_RST', 'bit': 1, 'size': 1, 'desc': 'System Reset'}, 'RST_CPU': {'name': 'RST_CPU', 'bit': 2, 'size': 1, 'desc': 'Reset Processor'}, 'FULL_RST': {'name': 'FULL_RST', 'bit': 3, 'size': 1, 'desc': 'Full Reset'}}}

[*] [DEBUG] + PM1_STS : {'name': 'PM1_STS', 'type': 'iobar', 'bar': 'ABASE', 'offset': 0, 'size': 2, 'desc': 'PM1 Status', 'FIELDS': {'WAK_STS': {'name': 'WAK_STS', 'bit': 15, 'size': 1, 'desc': 'Wake Status'}, 'PCIEXPWAK_STS': {'name': 'PCIEXPWAK_STS', 'bit': 14, 'size': 1, 'desc': 'PCI Express Wake Status'}, 'PWRBTNOR_STS': {'name': 'PWRBTNOR_STS', 'bit': 11, 'size': 1, 'desc': 'Power Button Override Status'}, 'RTC_STS': {'name': 'RTC_STS', 'bit': 10, 'size': 1, 'desc': 'RTC Status'}, 'PWRBTN_STS': {'name': 'PWRBTN_STS', 'bit': 8, 'size': 1, 'desc': 'Power Button Status'}, 'GBL_STS': {'name': 'GBL_STS', 'bit': 5, 'size': 1, 'desc': 'Global Status'}, 'BM_STS': {'name': 'BM_STS', 'bit': 4, 'size': 1, 'desc': 'Bus Master Status'}, 'TMROF_STS': {'name': 'TMROF_STS', 'bit': 0, 'size': 1, 'desc': 'Timer Overflow Status'}}}

[*] [DEBUG] + PM1_EN : {'name': 'PM1_EN', 'type': 'iobar', 'bar': 'ABASE', 'offset': 2, 'size': 2, 'desc': 'PM1 Enable', 'FIELDS': {'PCIEXPWAK_DIS': {'name': 'PCIEXPWAK_DIS', 'bit': 14, 'size': 1, 'desc': 'PCI Express Wake Disable'}, 'RTC_EN': {'name': 'RTC_EN', 'bit': 10, 'size': 1, 'desc': 'RTC Event Enable'}, 'PWRBTN_EN': {'name': 'PWRBTN_EN', 'bit': 8, 'size': 1, 'desc': 'Power Button Enable'}, 'GBL_EN': {'name': 'GBL_EN', 'bit': 5, 'size': 1, 'desc': 'Global Enable'}, 'TMROF_EN': {'name': 'TMROF_EN', 'bit': 0, 'size': 1, 'desc': 'Timer Overflow Interrupt Enable'}}}

[*] [DEBUG] + PM1_CNT : {'name': 'PM1_CNT', 'type': 'iobar', 'bar': 'ABASE', 'offset': 4, 'size': 4, 'desc': 'PM1 Control', 'FIELDS': {'SLP_EN': {'name': 'SLP_EN', 'bit': 13, 'size': 1, 'desc': 'Sleep Enable'}, 'SLP_TYP': {'name': 'SLP_TYP', 'bit': 10, 'size': 3, 'desc': 'Sleep Type'}, 'GBL_RLS': {'name': 'GBL_RLS', 'bit': 2, 'size': 1, 'desc': 'Global Release'}, 'BM_RLD': {'name': 'BM_RLD', 'bit': 1, 'size': 1, 'desc': 'Bus Master Reload'}, 'SCI_EN': {'name': 'SCI_EN', 'bit': 0, 'size': 1, 'desc': 'SCI Enable'}}}

[*] [DEBUG] + PM1_TMR : {'name': 'PM1_TMR', 'type': 'iobar', 'bar': 'ABASE', 'offset': 8, 'size': 4, 'desc': 'PM1 Timer', 'FIELDS': {'TMR_VAL': {'name': 'TMR_VAL', 'bit': 0, 'size': 24, 'desc': 'Timer Value'}}}

[*] [DEBUG] + SMI_EN : {'name': 'SMI_EN', 'type': 'iobar', 'bar': 'ABASE', 'offset': 48, 'size': 4, 'desc': 'SMI Control and Enable', 'FIELDS': {'GBL_SMI_EN': {'name': 'GBL_SMI_EN', 'bit': 0, 'size': 1, 'desc': 'GBL_SMI_EN'}, 'EOS': {'name': 'EOS', 'bit': 1, 'size': 1, 'desc': 'EOS'}, 'BIOS_EN': {'name': 'BIOS_EN', 'bit': 2, 'size': 1, 'desc': 'BIOS_EN'}, 'LEGACY_USB_EN': {'name': 'LEGACY_USB_EN', 'bit': 3, 'size': 1, 'desc': 'LEGACY_USB_EN'}, 'SLP_SMI_EN': {'name': 'SLP_SMI_EN', 'bit': 4, 'size': 1, 'desc': 'SLP_SMI_EN'}, 'APMC_EN': {'name': 'APMC_EN', 'bit': 5, 'size': 1, 'desc': 'APMC_EN'}, 'SWSMI_TMR_EN': {'name': 'SWSMI_TMR_EN', 'bit': 6, 'size': 1, 'desc': 'SWSMI_TMR_EN'}, 'BIOS_RLS': {'name': 'BIOS_RLS', 'bit': 7, 'size': 1, 'desc': 'BIOS_RLS'}, 'MCSMI_EN': {'name': 'MCSMI_EN', 'bit': 11, 'size': 1, 'desc': 'MCSMI_EN'}, 'TCO_EN': {'name': 'TCO_EN', 'bit': 13, 'size': 1, 'desc': 'TCO_EN'}, 'PERIODIC_EN': {'name': 'PERIODIC_EN', 'bit': 14, 'size': 1, 'desc': 'PERIODIC_EN'}, 'LEGACY_USB2_EN': {'name': 'LEGACY_USB2_EN', 'bit': 17, 'size': 1, 'desc': 'LEGACY_USB2_EN'}, 'INTEL_USB2_EN': {'name': 'INTEL_USB2_EN', 'bit': 18, 'size': 1, 'desc': 'INTEL_USB2_EN'}, 'GPIO_UNLOCK_SMI_EN': {'name': 'GPIO_UNLOCK_SMI_EN', 'bit': 27, 'size': 1, 'desc': 'GPIO_UNLOCK_SMI_EN'}, 'ME_SMI_EN': {'name': 'ME_SMI_EN', 'bit': 30, 'size': 1, 'desc': 'ME_SMI_EN'}, 'xHCI_SMI_EN': {'name': 'xHCI_SMI_EN', 'bit': 31, 'size': 1, 'desc': 'xHCI_SMI_EN'}}}

[*] [DEBUG] + TCO1_CNT : {'name': 'TCO1_CNT', 'type': 'iobar', 'bar': 'ABASE', 'offset': 104, 'size': 2, 'desc': 'TCO1 Control', 'FIELDS': {'TCO_LOCK': {'name': 'TCO_LOCK', 'bit': 12, 'size': 1, 'desc': 'TCO_LOCK'}}}

[*] [DEBUG] + SMBUS_HST_STS : {'name': 'SMBUS_HST_STS', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 0, 'size': 1, 'desc': 'SMBus Host Status', 'FIELDS': {'BUSY': {'name': 'BUSY', 'bit': 0, 'size': 1, 'desc': 'SMBus Busy'}, 'INTR': {'name': 'INTR', 'bit': 1, 'size': 1, 'desc': 'Interrupt'}, 'DEV_ERR': {'name': 'DEV_ERR', 'bit': 2, 'size': 1, 'desc': 'Device Error'}, 'BUS_ERR': {'name': 'BUS_ERR', 'bit': 3, 'size': 1, 'desc': 'Bus Error'}, 'FAILED': {'name': 'FAILED', 'bit': 4, 'size': 1, 'desc': 'SMBus Error/Failed'}, 'SMBALERT_STS': {'name': 'SMBALERT_STS', 'bit': 5, 'size': 1, 'desc': 'SMBALERT# Signal Status'}, 'INUSE_STS': {'name': 'INUSE_STS', 'bit': 6, 'size': 1, 'desc': 'InUse Semaphore Status'}, 'DS': {'name': 'DS', 'bit': 7, 'size': 1, 'desc': 'Done Status'}}}

[*] [DEBUG] + SMBUS_HST_CNT : {'name': 'SMBUS_HST_CNT', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 2, 'size': 1, 'desc': 'SMBus Host Control', 'FIELDS': {'INTREN': {'name': 'INTREN', 'bit': 0, 'size': 1, 'desc': 'Interrupt Enable'}, 'KILL': {'name': 'KILL', 'bit': 1, 'size': 1, 'desc': 'Kill'}, 'SMB_CMD': {'name': 'SMB_CMD', 'bit': 2, 'size': 3, 'desc': 'Command'}, 'LAST_BYTE': {'name': 'LAST_BYTE', 'bit': 5, 'size': 1, 'desc': 'Last Byte (for Block Read commands)'}, 'START': {'name': 'START', 'bit': 6, 'size': 1, 'desc': 'Start/Trigger'}, 'PEC_EN': {'name': 'PEC_EN', 'bit': 7, 'size': 1, 'desc': 'Packet Error Checking Enable'}}}

[*] [DEBUG] + SMBUS_HST_CMD : {'name': 'SMBUS_HST_CMD', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 3, 'size': 1, 'desc': 'SMBus Host Command', 'FIELDS': {'DataOffset': {'name': 'DataOffset', 'bit': 0, 'size': 8, 'desc': 'Command Data'}}}

[*] [DEBUG] + SMBUS_HST_SLVA : {'name': 'SMBUS_HST_SLVA', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 4, 'size': 1, 'desc': 'SMBus Host Slave Address', 'FIELDS': {'RW': {'name': 'RW', 'bit': 0, 'size': 1, 'desc': 'Read/Write Command'}, 'Address': {'name': 'Address', 'bit': 1, 'size': 7, 'desc': 'Slave Address'}}}

[*] [DEBUG] + SMBUS_HST_D0 : {'name': 'SMBUS_HST_D0', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 5, 'size': 1, 'desc': 'SMBus Host Data 0', 'FIELDS': {'Data': {'name': 'Data', 'bit': 0, 'size': 8, 'desc': 'Data0/Count'}}}

[*] [DEBUG] + SMBUS_HST_D1 : {'name': 'SMBUS_HST_D1', 'type': 'iobar', 'bar': 'SMBUS_BASE', 'offset': 6, 'size': 1, 'desc': 'SMBus Host Data 1', 'FIELDS': {'Data': {'name': 'Data', 'bit': 0, 'size': 8, 'desc': 'Data1'}}}

[*] [DEBUG] Missing size entry for IA32_MSR_CORE_THREAD_COUNT: {'name': 'IA32_MSR_CORE_THREAD_COUNT', 'type': 'msr', 'msr': 53, 'desc': 'Core Thread Count'}. Assuming 4 bytes

[*] [DEBUG] + IA32_MSR_CORE_THREAD_COUNT: {'name': 'IA32_MSR_CORE_THREAD_COUNT', 'type': 'msr', 'msr': 53, 'desc': 'Core Thread Count', 'size': 4, 'FIELDS': {'Thread_Count': {'name': 'Thread_Count', 'bit': 0, 'size': 16, 'desc': 'Number of Logical Processors currently enabled'}, 'Core_Count': {'name': 'Core_Count', 'bit': 16, 'size': 16, 'desc': 'Number of Processor Cores currently enabled'}}}

[*] [DEBUG] Missing size entry for IA32_BIOS_SIGN_ID: {'name': 'IA32_BIOS_SIGN_ID', 'type': 'msr', 'msr': 139, 'desc': 'Microcode Update Signature Register'}. Assuming 4 bytes

[*] [DEBUG] + IA32_BIOS_SIGN_ID: {'name': 'IA32_BIOS_SIGN_ID', 'type': 'msr', 'msr': 139, 'desc': 'Microcode Update Signature Register', 'size': 4, 'FIELDS': {'Microcode': {'name': 'Microcode', 'bit': 32, 'size': 32, 'desc': 'Microcode update signature'}}}

[*] [DEBUG] Missing size entry for IA32_SMRR_PHYSBASE: {'name': 'IA32_SMRR_PHYSBASE', 'type': 'msr', 'msr': 498, 'desc': 'SMRR Base Address MSR'}. Assuming 4 bytes

[*] [DEBUG] + IA32_SMRR_PHYSBASE: {'name': 'IA32_SMRR_PHYSBASE', 'type': 'msr', 'msr': 498, 'desc': 'SMRR Base Address MSR', 'size': 4, 'FIELDS': {'Type': {'name': 'Type', 'bit': 0, 'size': 8, 'desc': 'SMRR memory type'}, 'PhysBase': {'name': 'PhysBase', 'bit': 12, 'size': 20, 'desc': 'SMRR physical base address'}}}

[*] [DEBUG] Missing size entry for IA32_SMRR_PHYSMASK: {'name': 'IA32_SMRR_PHYSMASK', 'type': 'msr', 'msr': 499, 'desc': 'SMRR Range Mask MSR'}. Assuming 4 bytes

[*] [DEBUG] + IA32_SMRR_PHYSMASK: {'name': 'IA32_SMRR_PHYSMASK', 'type': 'msr', 'msr': 499, 'desc': 'SMRR Range Mask MSR', 'size': 4, 'FIELDS': {'Valid': {'name': 'Valid', 'bit': 11, 'size': 1, 'desc': 'SMRR valid'}, 'PhysMask': {'name': 'PhysMask', 'bit': 12, 'size': 20, 'desc': 'SMRR address range mask'}}}

[*] [DEBUG] Missing size entry for MTRRCAP : {'name': 'MTRRCAP', 'type': 'msr', 'msr': 254, 'desc': 'MTRR Capabilities MSR'}. Assuming 4 bytes

[*] [DEBUG] + MTRRCAP : {'name': 'MTRRCAP', 'type': 'msr', 'msr': 254, 'desc': 'MTRR Capabilities MSR', 'size': 4, 'FIELDS': {'Fixed_Range_MTRR': {'name': 'Fixed_Range_MTRR', 'bit': 8, 'size': 1, 'desc': 'Fixed range MTRRs Supported'}, 'WC': {'name': 'WC', 'bit': 10, 'size': 1, 'desc': 'WC Supported'}, 'SMRR': {'name': 'SMRR', 'bit': 11, 'size': 1, 'desc': 'SMRR Supported'}, 'PRMRR': {'name': 'PRMRR', 'bit': 12, 'size': 1, 'desc': 'PRMRR Supported'}}}

[*] [DEBUG] Missing size entry for IA32_FEATURE_CONTROL: {'name': 'IA32_FEATURE_CONTROL', 'type': 'msr', 'msr': 58, 'desc': 'Processor Feature Control'}. Assuming 4 bytes

[*] [DEBUG] + IA32_FEATURE_CONTROL: {'name': 'IA32_FEATURE_CONTROL', 'type': 'msr', 'msr': 58, 'desc': 'Processor Feature Control', 'size': 4, 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock'}, 'EN_VMX_INSIDE_SMX': {'name': 'EN_VMX_INSIDE_SMX', 'bit': 1, 'size': 1, 'desc': 'Enable VMX inside SMX operation'}, 'EN_VMX_OUTSIDE_SMX': {'name': 'EN_VMX_OUTSIDE_SMX', 'bit': 2, 'size': 1, 'desc': 'Enable VMX outside SMX operation'}, 'Reserved0': {'name': 'Reserved0', 'bit': 3, 'size': 5, 'desc': 'Reserved'}, 'SENTER_LOCAL_EN': {'name': 'SENTER_LOCAL_EN', 'bit': 8, 'size': 7, 'desc': 'SENTER Local Functions Enable'}, 'SENTER_GLOBAL_EN': {'name': 'SENTER_GLOBAL_EN', 'bit': 15, 'size': 1, 'desc': 'SENTER Global Enable'}, 'Reserved1': {'name': 'Reserved1', 'bit': 16, 'size': 1, 'desc': 'Reserved'}, 'SGX_LAUNCH_CTRL_EN': {'name': 'SGX_LAUNCH_CTRL_EN', 'bit': 17, 'size': 1, 'desc': 'SGX Launch Control Enable'}, 'SGX_GLOBAL_EN': {'name': 'SGX_GLOBAL_EN', 'bit': 18, 'size': 1, 'desc': 'SGX Global Enable'}, 'Reserved2': {'name': 'Reserved2', 'bit': 19, 'size': 1, 'desc': 'Reserved'}, 'LMCE_ON': {'name': 'LMCE_ON', 'bit': 20, 'size': 1, 'desc': 'Turn Local Machine Check On'}}}

[*] [DEBUG] Missing size entry for IA32_APIC_BASE : {'name': 'IA32_APIC_BASE', 'type': 'msr', 'msr': 27, 'desc': 'Local APIC Base'}. Assuming 4 bytes

[*] [DEBUG] + IA32_APIC_BASE : {'name': 'IA32_APIC_BASE', 'type': 'msr', 'msr': 27, 'desc': 'Local APIC Base', 'size': 4, 'FIELDS': {'BSP': {'name': 'BSP', 'bit': 8, 'size': 1, 'desc': 'Bootstrap Processor'}, 'x2APICEn': {'name': 'x2APICEn', 'bit': 10, 'size': 1, 'desc': 'Enable x2APIC mode'}, 'En': {'name': 'En', 'bit': 11, 'size': 1, 'desc': 'APIC Global Enable'}, 'APICBase': {'name': 'APICBase', 'bit': 12, 'size': 20, 'desc': 'APIC Base'}}}

[*] [DEBUG] Missing size entry for MSR_SMI_COUNT : {'name': 'MSR_SMI_COUNT', 'type': 'msr', 'msr': 52, 'desc': 'SMI Count'}. Assuming 4 bytes

[*] [DEBUG] + MSR_SMI_COUNT : {'name': 'MSR_SMI_COUNT', 'type': 'msr', 'msr': 52, 'desc': 'SMI Count', 'size': 4, 'FIELDS': {'Count': {'name': 'Count', 'bit': 0, 'size': 64, 'desc': 'Count'}}}

[*] [DEBUG] Missing size entry for IA32_ARCH_CAPABILITIES: {'name': 'IA32_ARCH_CAPABILITIES', 'type': 'msr', 'msr': 266, 'desc': 'Architectural Capabilities MSR'}. Assuming 4 bytes

[*] [DEBUG] + IA32_ARCH_CAPABILITIES: {'name': 'IA32_ARCH_CAPABILITIES', 'type': 'msr', 'msr': 266, 'desc': 'Architectural Capabilities MSR', 'size': 4, 'FIELDS': {'RDCL_NO': {'name': 'RDCL_NO', 'bit': 0, 'size': 1, 'desc': 'Processor is not susceptible to RDCL (Rogue Data Cache Load)'}, 'IBRS_ALL': {'name': 'IBRS_ALL', 'bit': 1, 'size': 1, 'desc': 'Processor supports enhanced Indirect Branch Restricted Speculation (IBRS)'}}}

[*] [DEBUG] Missing size entry for IA32_SPEC_CTRL : {'name': 'IA32_SPEC_CTRL', 'type': 'msr', 'msr': 72, 'desc': 'Speculation Control MSR'}. Assuming 4 bytes

[*] [DEBUG] + IA32_SPEC_CTRL : {'name': 'IA32_SPEC_CTRL', 'type': 'msr', 'msr': 72, 'desc': 'Speculation Control MSR', 'size': 4, 'FIELDS': {'IBRS': {'name': 'IBRS', 'bit': 0, 'size': 1, 'desc': 'Enable Indirect Branch Restricted Speculation (IBRS)'}, 'STIBP': {'name': 'STIBP', 'bit': 1, 'size': 1, 'desc': 'Enable Single Thread Indirect Branch Predictors (STIBP)'}, 'SSBD': {'name': 'SSBD', 'bit': 2, 'size': 1, 'desc': 'Delays speculative execution of load until the addr for all older stores are known'}}}

[*] [DEBUG] Missing size entry for IA32_PRED_CMD : {'name': 'IA32_PRED_CMD', 'type': 'msr', 'msr': 73, 'desc': 'Prediction Command MSR'}. Assuming 4 bytes

[*] [DEBUG] + IA32_PRED_CMD : {'name': 'IA32_PRED_CMD', 'type': 'msr', 'msr': 73, 'desc': 'Prediction Command MSR', 'size': 4, 'FIELDS': {'IBPB': {'name': 'IBPB', 'bit': 0, 'size': 1, 'desc': 'IBPB Command'}}}

[*] [DEBUG] Missing size entry for MSR_LT_LOCK_MEMORY: {'name': 'MSR_LT_LOCK_MEMORY', 'type': 'msr', 'msr': 743, 'desc': 'LT lock memory configuration MSR'}. Assuming 4 bytes

[*] [DEBUG] + MSR_LT_LOCK_MEMORY: {'name': 'MSR_LT_LOCK_MEMORY', 'type': 'msr', 'msr': 743, 'desc': 'LT lock memory configuration MSR', 'size': 4, 'FIELDS': {'LT_LOCK': {'name': 'LT_LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock bit'}}}

[*] [DEBUG] Missing size entry for IA32_DEBUG_INTERFACE: {'name': 'IA32_DEBUG_INTERFACE', 'type': 'msr', 'msr': 3200, 'desc': 'Silicon Debug Feature Control'}. Assuming 4 bytes

[*] [DEBUG] + IA32_DEBUG_INTERFACE: {'name': 'IA32_DEBUG_INTERFACE', 'type': 'msr', 'msr': 3200, 'desc': 'Silicon Debug Feature Control', 'size': 4, 'FIELDS': {'ENABLE': {'name': 'ENABLE', 'bit': 0, 'size': 1, 'desc': 'Enable'}, 'LOCK': {'name': 'LOCK', 'bit': 30, 'size': 1, 'desc': 'Lock (set automatically on the first SMI)'}, 'DEBUG_OCCURRED': {'name': 'DEBUG_OCCURRED', 'bit': 31, 'size': 1, 'desc': 'Debug Occurred (set by hardware)'}}}

[*] [DEBUG] Missing size entry for BIOS_SE_SVN : {'name': 'BIOS_SE_SVN', 'type': 'msr', 'msr': 770, 'desc': 'BIOS SGX SVN values'}. Assuming 4 bytes

[*] [DEBUG] + BIOS_SE_SVN : {'name': 'BIOS_SE_SVN', 'type': 'msr', 'msr': 770, 'desc': 'BIOS SGX SVN values', 'size': 4, 'FIELDS': {'PFAT_SE_SVN': {'name': 'PFAT_SE_SVN', 'bit': 40, 'size': 8, 'desc': 'PFAT_SE_SVN'}, 'ANC_SE_SVN': {'name': 'ANC_SE_SVN', 'bit': 32, 'size': 8, 'desc': 'ANC_SE_SVN'}, 'SCLEAN_SE_SVN': {'name': 'SCLEAN_SE_SVN', 'bit': 24, 'size': 8, 'desc': 'SCLEAN_SE_SVN'}, 'SINIT_SE_SVN': {'name': 'SINIT_SE_SVN', 'bit': 16, 'size': 8, 'desc': 'SINIT_SE_SVN'}}}

[*] [DEBUG] Missing size entry for BIOS_SE_SVN_STATUS: {'name': 'BIOS_SE_SVN_STATUS', 'type': 'msr', 'msr': 1280, 'desc': 'BIOS SGX SVN status register'}. Assuming 4 bytes

[*] [DEBUG] + BIOS_SE_SVN_STATUS: {'name': 'BIOS_SE_SVN_STATUS', 'type': 'msr', 'msr': 1280, 'desc': 'BIOS SGX SVN status register', 'size': 4, 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'ACM threshold locked'}, 'SINIT_SE_SVN': {'name': 'SINIT_SE_SVN', 'bit': 16, 'size': 8, 'desc': 'SINIT_SE_SVN'}}}

[*] [DEBUG] Missing size entry for PRMRR_VALID_CONFIG: {'name': 'PRMRR_VALID_CONFIG', 'type': 'msr', 'msr': 507, 'desc': 'PRMRR VALID register'}. Assuming 4 bytes

[*] [DEBUG] + PRMRR_VALID_CONFIG: {'name': 'PRMRR_VALID_CONFIG', 'type': 'msr', 'msr': 507, 'desc': 'PRMRR VALID register', 'size': 4, 'FIELDS': {'PRMRR_SIZE_SUPPORT': {'name': 'PRMRR_SIZE_SUPPORT', 'bit': 5, 'size': 4, 'desc': 'PRMRR size support'}}}

[*] [DEBUG] Missing size entry for PRMRR_PHYBASE : {'name': 'PRMRR_PHYBASE', 'type': 'msr', 'msr': 500, 'desc': 'PRMRR BASE Address'}. Assuming 4 bytes

[*] [DEBUG] + PRMRR_PHYBASE : {'name': 'PRMRR_PHYBASE', 'type': 'msr', 'msr': 500, 'desc': 'PRMRR BASE Address', 'size': 4, 'FIELDS': {'PRMRR_MEMTYPE': {'name': 'PRMRR_MEMTYPE', 'bit': 0, 'size': 3, 'desc': 'PRMRR Memory Type'}, 'PRMRR_base_address_fields': {'name': 'PRMRR_base_address_fields', 'bit': 12, 'size': 34, 'desc': 'PRMRR base address bits'}}}

[*] [DEBUG] Missing size entry for PRMRR_MASK : {'name': 'PRMRR_MASK', 'type': 'msr', 'msr': 501, 'desc': 'PRMRR MASK register'}. Assuming 4 bytes

[*] [DEBUG] + PRMRR_MASK : {'name': 'PRMRR_MASK', 'type': 'msr', 'msr': 501, 'desc': 'PRMRR MASK register', 'size': 4, 'FIELDS': {'PRMRR_LOCK': {'name': 'PRMRR_LOCK', 'bit': 10, 'size': 1, 'desc': 'PRMRR Lock Bit'}, 'PRMRR_VLD': {'name': 'PRMRR_VLD', 'bit': 11, 'size': 1, 'desc': 'PRMRR Valid Bit set by mcheck'}, 'PRMRR_mask_bits': {'name': 'PRMRR_mask_bits', 'bit': 12, 'size': 34, 'desc': 'PRMRR mask bits'}}}

[*] [DEBUG] Missing size entry for PRMRR_UNCORE_PHYBASE: {'name': 'PRMRR_UNCORE_PHYBASE', 'type': 'msr', 'msr': 756, 'desc': 'PRMRR uncore BASE Address'}. Assuming 4 bytes

[*] [DEBUG] + PRMRR_UNCORE_PHYBASE: {'name': 'PRMRR_UNCORE_PHYBASE', 'type': 'msr', 'msr': 756, 'desc': 'PRMRR uncore BASE Address', 'size': 4, 'FIELDS': {'PRMRR_base_address_fields': {'name': 'PRMRR_base_address_fields', 'bit': 12, 'size': 27, 'desc': 'PRMRR uncore base address bits'}}}

[*] [DEBUG] Missing size entry for PRMRR_UNCORE_MASK: {'name': 'PRMRR_UNCORE_MASK', 'type': 'msr', 'msr': 757, 'desc': 'PRMRR uncore MASK register'}. Assuming 4 bytes

[*] [DEBUG] + PRMRR_UNCORE_MASK: {'name': 'PRMRR_UNCORE_MASK', 'type': 'msr', 'msr': 757, 'desc': 'PRMRR uncore MASK register', 'size': 4, 'FIELDS': {'PRMRR_LOCK': {'name': 'PRMRR_LOCK', 'bit': 10, 'size': 1, 'desc': 'PRMRR uncore Lock Bit'}, 'PRMRR_VLD': {'name': 'PRMRR_VLD', 'bit': 11, 'size': 1, 'desc': 'PRMRR uncore Valid Bit set by mcheck'}, 'PRMRR_mask_bits': {'name': 'PRMRR_mask_bits', 'bit': 12, 'size': 27, 'desc': 'PRMRR uncore mask bits'}}}

[*] [DEBUG] Missing size entry for SGX_DEBUG_MODE : {'name': 'SGX_DEBUG_MODE', 'type': 'msr', 'msr': 1283, 'desc': 'SGX debug mode resiter'}. Assuming 4 bytes

[*] [DEBUG] + SGX_DEBUG_MODE : {'name': 'SGX_DEBUG_MODE', 'type': 'msr', 'msr': 1283, 'desc': 'SGX debug mode resiter', 'size': 4, 'FIELDS': {'SGX_DEBUG_MODE_STATUS_BIT': {'name': 'SGX_DEBUG_MODE_STATUS_BIT', 'bit': 1, 'size': 1, 'desc': 'Debug mode status but'}}}

[*] [DEBUG] Missing size entry for IA32_U_CET : {'name': 'IA32_U_CET', 'type': 'msr', 'msr': 1696, 'desc': 'CET User configuration'}. Assuming 4 bytes

[*] [DEBUG] + IA32_U_CET : {'name': 'IA32_U_CET', 'type': 'msr', 'msr': 1696, 'desc': 'CET User configuration', 'size': 4, 'FIELDS': {'SH_STK_EN': {'name': 'SH_STK_EN', 'bit': 0, 'size': 1, 'desc': 'Enable shadow stacks at CPL3'}, 'WR_SHSTK_EN': {'name': 'WR_SHSTK_EN', 'bit': 1, 'size': 1, 'desc': 'Enables the WRSSD/WRSSQ instructions'}, 'ENDBR_EN': {'name': 'ENDBR_EN', 'bit': 2, 'size': 1, 'desc': 'Enable indirect branch tracking'}, 'LEG_IW_EN': {'name': 'LEG_IW_EN', 'bit': 3, 'size': 1, 'desc': 'Enable legacy compatibility treatment for indirect branch tracking'}, 'NO_TRACK_EN': {'name': 'NO_TRACK_EN', 'bit': 4, 'size': 1, 'desc': 'Enables use of no track prefix for indirect branch tracking'}, 'SUPPRESS_DIS': {'name': 'SUPPRESS_DIS', 'bit': 5, 'size': 1, 'desc': 'Disables suppression of CET indirect branch tracking on legacy compatibility'}, 'RESERVED': {'name': 'RESERVED', 'bit': 6, 'size': 4, 'desc': 'RESERVED'}, 'SUPPRESS': {'name': 'SUPPRESS', 'bit': 10, 'size': 1, 'desc': 'Indirect branch tracking is suppressed'}, 'TRACKER': {'name': 'TRACKER', 'bit': 11, 'size': 1, 'desc': 'Value of the indirect branch tracking state machine'}, 'EB_LEG_BITMAP_BASE': {'name': 'EB_LEG_BITMAP_BASE', 'bit': 12, 'size': 52, 'desc': 'Linear address bits of legacy code page bitmap'}}}

[*] [DEBUG] Missing size entry for IA32_S_CET : {'name': 'IA32_S_CET', 'type': 'msr', 'msr': 1698, 'desc': 'CET supervisor configuration'}. Assuming 4 bytes

[*] [DEBUG] + IA32_S_CET : {'name': 'IA32_S_CET', 'type': 'msr', 'msr': 1698, 'desc': 'CET supervisor configuration', 'size': 4, 'FIELDS': {'SH_STK_EN': {'name': 'SH_STK_EN', 'bit': 0, 'size': 1, 'desc': 'Enable shadow stacks at CPL3'}, 'WR_SHSTK_EN': {'name': 'WR_SHSTK_EN', 'bit': 1, 'size': 1, 'desc': 'Enables the WRSSD/WRSSQ instructions'}, 'ENDBR_EN': {'name': 'ENDBR_EN', 'bit': 2, 'size': 1, 'desc': 'Enable indirect branch tracking'}, 'LEG_IW_EN': {'name': 'LEG_IW_EN', 'bit': 3, 'size': 1, 'desc': 'Enable legacy compatibility treatment for indirect branch tracking'}, 'NO_TRACK_EN': {'name': 'NO_TRACK_EN', 'bit': 4, 'size': 1, 'desc': 'Enables use of no track prefix for indirect branch tracking'}, 'SUPPRESS_DIS': {'name': 'SUPPRESS_DIS', 'bit': 5, 'size': 1, 'desc': 'Disables suppression of CET indirect branch tracking on legacy compatibility'}, 'RESERVED': {'name': 'RESERVED', 'bit': 6, 'size': 4, 'desc': 'RESERVED'}, 'SUPPRESS': {'name': 'SUPPRESS', 'bit': 10, 'size': 1, 'desc': 'Indirect branch tracking is suppressed'}, 'TRACKER': {'name': 'TRACKER', 'bit': 11, 'size': 1, 'desc': 'Value of the indirect branch tracking state machine'}, 'EB_LEG_BITMAP_BASE': {'name': 'EB_LEG_BITMAP_BASE', 'bit': 12, 'size': 52, 'desc': 'Linear address bits of legacy code page bitmap'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] + SmmBiosWriteProtection: {'name': 'SmmBiosWriteProtection', 'register': 'BC', 'field': 'SMM_BWP', 'desc': 'SMM BIOS Write Protection'}

[*] [DEBUG] + BiosLockEnable : {'name': 'BiosLockEnable', 'register': 'BC', 'field': 'BLE', 'desc': 'BIOS Lock Enable'}

[*] [DEBUG] + BiosWriteEnable : {'name': 'BiosWriteEnable', 'register': 'BC', 'field': 'BIOSWE', 'desc': 'BIOS Write Enable'}

[*] [DEBUG] + TopSwapStatus : {'name': 'TopSwapStatus', 'register': 'BC', 'field': 'TSS', 'desc': 'Top Swap Status'}

[*] [DEBUG] + TopSwap : {'name': 'TopSwap', 'register': 'BUC', 'field': 'TS', 'desc': 'Top Swap'}

[*] [DEBUG] + FlashLockDown : {'name': 'FlashLockDown', 'register': 'HSFS', 'field': 'FLOCKDN', 'desc': 'Flash Configuration Lock-Down'}

[*] [DEBUG] + BiosInterfaceLockDown: {'name': 'BiosInterfaceLockDown', 'register': 'GCS', 'field': 'BILD', 'desc': 'BIOS Interface Lock-Down'}

[*] [DEBUG] + GlobalSMIEnable : {'name': 'GlobalSMIEnable', 'register': 'SMI_EN', 'field': 'GBL_SMI_EN', 'desc': 'Global SMI Enable'}

[*] [DEBUG] + GPIOSMIEnable : {'name': 'GPIOSMIEnable', 'register': 'SMI_EN', 'field': 'GPIO_UNLOCK_SMI_EN', 'desc': 'GPIO Config SMI Enable'}

[*] [DEBUG] + SMILock : {'name': 'SMILock', 'register': 'GEN_PMCON_1', 'field': 'SMI_LOCK', 'desc': 'SMI Global Configuration Lock'}

[*] [DEBUG] + TCOSMIEnable : {'name': 'TCOSMIEnable', 'register': 'SMI_EN', 'field': 'TCO_EN', 'desc': 'TCO SMI Enable'}

[*] [DEBUG] + TCOSMILock : {'name': 'TCOSMILock', 'register': 'TCO1_CNT', 'field': 'TCO_LOCK', 'desc': 'TCO SMI Lock'}

[*] [DEBUG] + SMRAMDLock : {'name': 'SMRAMDLock', 'register': 'PCI0.0.0_SMRAMC', 'field': 'D_LCK', 'desc': 'SMRAM D_LCK'}

[*] [DEBUG] + TSEGBaseLock : {'name': 'TSEGBaseLock', 'register': 'PCI0.0.0_TSEGMB', 'field': 'LOCK', 'desc': 'TSEG Base Lock'}

[*] [DEBUG] + TSEGLimitLock : {'name': 'TSEGLimitLock', 'register': 'PCI0.0.0_BGSM', 'field': 'LOCK', 'desc': 'TSEG Limit Lock'}

[*] [DEBUG] + Ia32FeatureControlLock: {'name': 'Ia32FeatureControlLock', 'register': 'IA32_FEATURE_CONTROL', 'field': 'LOCK', 'desc': 'Lock IA32 Feature Control'}

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/kbl.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] + P2SBC : {'name': 'P2SBC', 'bus': [0], 'dev': 31, 'fun': 1, 'vid': 32902}

[*] [DEBUG] + SMBUS : {'name': 'SMBUS', 'bus': [0], 'dev': 31, 'fun': 4, 'vid': 32902}

[*] [DEBUG] + SPI : {'name': 'SPI', 'bus': [0], 'dev': 31, 'fun': 5, 'vid': 32902}

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] + GTTMMADR : {'name': 'GTTMMADR', 'bus': [0], 'dev': 2, 'fun': 0, 'reg': 16, 'width': 8, 'mask': 549739036672, 'desc': 'Graphics Translation Table Range'}

[*] [DEBUG] + HDABAR : {'name': 'HDABAR', 'bus': [0], 'dev': 31, 'fun': 3, 'reg': 16, 'width': 8, 'mask': 18446744073709535232, 'size': 4096, 'desc': 'HD Audio Base'}

[*] [DEBUG] + SPIBAR : {'name': 'SPIBAR', 'bus': [0], 'dev': 31, 'fun': 5, 'reg': 16, 'width': 4, 'mask': 4294963200, 'size': 4096, 'desc': 'SPI Controller Register Range', 'offset': 0}

[*] [DEBUG] + PWRMBASE : {'name': 'PWRMBASE', 'register': 'PWRMBASE', 'base_field': 'BA', 'size': 4096, 'fixed_address': 4261412864, 'desc': 'Power Management Register Range'}

[*] [DEBUG] + SBREGBAR : {'name': 'SBREGBAR', 'register': 'SBREG_BAR', 'base_field': 'RBA', 'size': 16777216, 'fixed_address': 4244635648, 'desc': 'Sideband Register Access BAR'}

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'register': 'ABASE', 'base_field': 'BA', 'size': 256, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + PMBASE : {'name': 'PMBASE', 'register': 'ABASE', 'base_field': 'BA', 'size': 256, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + TCOBASE : {'name': 'TCOBASE', 'register': 'TCOBASE', 'base_field': 'TCOBA', 'size': 32, 'desc': 'TCO Base Address'}

[*] [DEBUG] + SMBUS_BASE : {'name': 'SMBUS_BASE', 'bus': [0], 'dev': 31, 'fun': 4, 'reg': 32, 'mask': 65504, 'size': 128, 'desc': 'SMBus Base Address'}

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + SBREG_BAR : {'name': 'SBREG_BAR', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 16, 'size': 4, 'desc': 'Sideband Register Access BAR', 'FIELDS': {'RBA': {'name': 'RBA', 'bit': 24, 'size': 8, 'desc': 'Register Base Address'}}}

[*] [DEBUG] + P2SBC : {'name': 'P2SBC', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 224, 'size': 2, 'desc': 'P2SB Configuration Register', 'FIELDS': {'HIDE': {'name': 'HIDE', 'bit': 8, 'size': 1, 'desc': 'Hide SBREG_BAR'}}}

[*] [DEBUG] + P2SB_HIDE : {'name': 'P2SB_HIDE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 225, 'size': 1, 'desc': 'P2SB Configuration Register hide-unhide', 'FIELDS': {'HIDE': {'name': 'HIDE', 'bit': 0, 'size': 1, 'desc': 'Hide SBREG_BAR'}}}

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 64, 'size': 4, 'desc': 'ACPI Base Address', 'FIELDS': {'Base': {'name': 'Base', 'bit': 7, 'size': 9, 'desc': 'Base Address'}, 'STYPE': {'name': 'STYPE', 'bit': 0, 'size': 1, 'desc': 'Space Type (always 1 - I/O space)'}, 'BA': {'name': 'BA', 'bit': 8, 'size': 8, 'desc': 'Base Address'}}}

[*] [DEBUG] + ACTL : {'name': 'ACTL', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 68, 'size': 4, 'desc': 'ACPI Control', 'FIELDS': {'SCIS': {'name': 'SCIS', 'bit': 0, 'size': 2, 'desc': 'SCI IRQ Select'}, 'EN': {'name': 'EN', 'bit': 7, 'size': 1, 'desc': 'ACPI Enable'}, 'PWRM_EN': {'name': 'PWRM_EN', 'bit': 8, 'size': 1, 'desc': 'PWRM Enable'}}}

[*] [DEBUG] + PWRMBASE : {'name': 'PWRMBASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 72, 'size': 4, 'desc': 'PM Base Address', 'FIELDS': {'STYPE': {'name': 'STYPE', 'bit': 0, 'size': 1, 'desc': 'Space Type (always 0 - memory space)'}, 'BA': {'name': 'BA', 'bit': 12, 'size': 20, 'desc': 'Base Address'}}}

[*] [DEBUG] + GEN_PMCON_1 : {'name': 'GEN_PMCON_1', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 160, 'size': 2, 'desc': 'General PM Configuration A', 'FIELDS': {'SMI_LOCK': {'name': 'SMI_LOCK', 'bit': 4, 'size': 1, 'desc': 'SMI_LOCK'}}}

[*] [DEBUG] + SMBUS_VID : {'name': 'SMBUS_VID', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 0, 'size': 2, 'desc': 'VID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_DID : {'name': 'SMBUS_DID', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 2, 'size': 2, 'desc': 'DID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_CMD : {'name': 'SMBUS_CMD', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 4, 'size': 2, 'desc': 'CMD', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_HCFG : {'name': 'SMBUS_HCFG', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 64, 'size': 1, 'desc': 'Host Configuration', 'FIELDS': {'HST_EN': {'name': 'HST_EN', 'bit': 0, 'size': 1, 'desc': 'HST_EN'}, 'SMB_SMI_EN': {'name': 'SMB_SMI_EN', 'bit': 1, 'size': 1, 'desc': 'SMB_SMI_EN'}, 'I2C_EN': {'name': 'I2C_EN', 'bit': 2, 'size': 1, 'desc': 'I2C_EN'}, 'SSRESET': {'name': 'SSRESET', 'bit': 3, 'size': 1, 'desc': 'SSRESET'}, 'SPD_WD': {'name': 'SPD_WD', 'bit': 4, 'size': 1, 'desc': 'SPD_WD'}}}

[*] [DEBUG] + TCOBASE : {'name': 'TCOBASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 80, 'size': 4, 'desc': 'TCO Base Address', 'FIELDS': {'IOS': {'name': 'IOS', 'bit': 0, 'size': 1, 'desc': 'I/O space'}, 'TCOBA': {'name': 'TCOBA', 'bit': 5, 'size': 11, 'desc': 'TCO Base Address'}}}

[*] [DEBUG] + TCOCTL : {'name': 'TCOCTL', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 84, 'size': 4, 'desc': 'TCO Control', 'FIELDS': {'TCO_BASE_LOCK': {'name': 'TCO_BASE_LOCK', 'bit': 0, 'size': 1, 'desc': 'TCO Base Lock'}, 'TCO_BASE_EN': {'name': 'TCO_BASE_EN', 'bit': 8, 'size': 1, 'desc': 'TCO Base Enable'}}}

[*] [DEBUG] + BC : {'name': 'BC', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 5, 'offset': 220, 'size': 4, 'desc': 'BIOS Control', 'FIELDS': {'BIOSWE': {'name': 'BIOSWE', 'bit': 0, 'size': 1, 'desc': 'BIOS Write Enable'}, 'BLE': {'name': 'BLE', 'bit': 1, 'size': 1, 'desc': 'BIOS Lock Enable'}, 'SRC': {'name': 'SRC', 'bit': 2, 'size': 2, 'desc': 'SPI Read Configuration'}, 'TSS': {'name': 'TSS', 'bit': 4, 'size': 1, 'desc': 'Top Swap Status'}, 'SMM_BWP': {'name': 'SMM_BWP', 'bit': 5, 'size': 1, 'desc': 'SMM BIOS Write Protection'}, 'BBS': {'name': 'BBS', 'bit': 6, 'size': 1, 'desc': 'Boot BIOS Strap'}, 'BILD': {'name': 'BILD', 'bit': 7, 'size': 1, 'desc': 'BIOS Interface Lock Down'}}}

[*] [DEBUG] + HSFS : {'name': 'HSFS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 4, 'size': 4, 'desc': 'Hardware Sequencing Flash Status Register', 'FIELDS': {'FDONE': {'name': 'FDONE', 'bit': 0, 'size': 1, 'desc': 'Flash Cycle Done'}, 'FCERR': {'name': 'FCERR', 'bit': 1, 'size': 1, 'desc': 'Flash Cycle Error'}, 'AEL': {'name': 'AEL', 'bit': 2, 'size': 1, 'desc': 'Access Error Log'}, 'BERASE': {'name': 'BERASE', 'bit': 3, 'size': 2, 'desc': 'Block/Sector Erase Size'}, 'SCIP': {'name': 'SCIP', 'bit': 5, 'size': 1, 'desc': 'SPI cycle in progress'}, 'FDOPSS': {'name': 'FDOPSS', 'bit': 13, 'size': 1, 'desc': 'Flash Descriptor Override Pin-Strap Status'}, 'FDV': {'name': 'FDV', 'bit': 14, 'size': 1, 'desc': 'Flash Descriptor Valid'}, 'FLOCKDN': {'name': 'FLOCKDN', 'bit': 15, 'size': 1, 'desc': 'Flash Configuration Lock-Down'}, 'WRSDIS': {'name': 'WRSDIS', 'bit': 11, 'size': 1, 'desc': 'Write status disable'}, 'PR34LKD': {'name': 'PR34LKD', 'bit': 12, 'size': 1, 'desc': 'PRR3 PRR4 Lock-Down'}, 'FGO': {'name': 'FGO', 'bit': 16, 'size': 1, 'desc': 'Flash cycle go'}, 'FCYCLE': {'name': 'FCYCLE', 'bit': 17, 'size': 4, 'desc': 'Flash Cycle Type'}, 'WET': {'name': 'WET', 'bit': 21, 'size': 1, 'desc': 'Write Enable Type'}, 'FDBC': {'name': 'FDBC', 'bit': 24, 'size': 6, 'desc': 'Flash Data Byte Count'}, 'FSMIE': {'name': 'FSMIE', 'bit': 31, 'size': 1, 'desc': 'Flash SPI SMI# Enable'}}}

[*] [DEBUG] + FREG0_FLASHD : {'name': 'FREG0_FLASHD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 84, 'size': 4, 'desc': 'Flash Region 0 (Flash Descriptor)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG1_BIOS : {'name': 'FREG1_BIOS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 88, 'size': 4, 'desc': 'Flash Region 1 (BIOS)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG2_ME : {'name': 'FREG2_ME', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 92, 'size': 4, 'desc': 'Flash Region 2 (ME)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG3_GBE : {'name': 'FREG3_GBE', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 96, 'size': 4, 'desc': 'Flash Region 3 (GBe)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG4_PD : {'name': 'FREG4_PD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 100, 'size': 4, 'desc': 'Flash Region 4 (Platform Data)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG5 : {'name': 'FREG5', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 104, 'size': 4, 'desc': 'Flash Region 5', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] - FREG6 : Flash Region 6 not defined for this platform

[*] [DEBUG] + PR0 : {'name': 'PR0', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 132, 'size': 4, 'desc': 'Protected Range 0', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR1 : {'name': 'PR1', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 136, 'size': 4, 'desc': 'Protected Range 1', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR2 : {'name': 'PR2', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 140, 'size': 4, 'desc': 'Protected Range 2', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR3 : {'name': 'PR3', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 144, 'size': 4, 'desc': 'Protected Range 3', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR4 : {'name': 'PR4', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 148, 'size': 4, 'desc': 'Protected Range 4', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + FDOC : {'name': 'FDOC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 180, 'size': 4, 'desc': 'Flash Descriptor Observability Control Register', 'FIELDS': {'FDSI': {'name': 'FDSI', 'bit': 2, 'size': 10, 'desc': 'Flash Descriptor Section Index'}, 'FDSS': {'name': 'FDSS', 'bit': 12, 'size': 3, 'desc': 'Flash Descriptor Section Select'}}}

[*] [DEBUG] + FDOD : {'name': 'FDOD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 184, 'size': 4, 'desc': 'Flash Descriptor Observability Data Register', 'FIELDS': {'FDSD': {'name': 'FDSD', 'bit': 0, 'size': 32, 'desc': 'Flash Descriptor Section Data'}}}

[*] [DEBUG] + LVSCC : {'name': 'LVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 196, 'size': 4, 'desc': 'Vendor Specific Component Capabilities', 'FIELDS': {'LBES': {'name': 'LBES', 'bit': 0, 'size': 2, 'desc': 'Lower Block/Sector Erase Size'}, 'LWG': {'name': 'LWG', 'bit': 2, 'size': 1, 'desc': 'Lower Write Granularity'}, 'LWSR': {'name': 'LWSR', 'bit': 3, 'size': 1, 'desc': 'Lower Write Status Required'}, 'LWEWS': {'name': 'LWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'LEO': {'name': 'LEO', 'bit': 8, 'size': 8, 'desc': 'Lower Erase Opcode'}, 'WG': {'name': 'WG', 'bit': 2, 'size': 1, 'desc': 'Write Granularity'}, 'WSR': {'name': 'WSR', 'bit': 3, 'size': 1, 'desc': 'Write Status Required'}, 'WEWS': {'name': 'WEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'QER': {'name': 'QER', 'bit': 5, 'size': 3, 'desc': 'Quad Enable Requirements'}, 'EO_4k': {'name': 'EO_4k', 'bit': 8, 'size': 8, 'desc': '4k Erase Opcode'}, 'EO_64k': {'name': 'EO_64k', 'bit': 16, 'size': 8, 'desc': '64k Erase Opcode'}, 'SOFT_RST_SUP': {'name': 'SOFT_RST_SUP', 'bit': 24, 'size': 1, 'desc': 'Soft Reset Supported'}, 'SUSPEND_RESUME_SUP': {'name': 'SUSPEND_RESUME_SUP', 'bit': 25, 'size': 1, 'desc': 'Suspend/Resume Supported'}, 'DEEP_PWRDN_SUP': {'name': 'DEEP_PWRDN_SUP', 'bit': 26, 'size': 1, 'desc': 'Deep Powerdown Supported'}, 'RPMC_SUP': {'name': 'RPMC_SUP', 'bit': 27, 'size': 1, 'desc': 'RPMC Supported'}, 'EO_4k_VALID': {'name': 'EO_4k_VALID', 'bit': 28, 'size': 1, 'desc': '4k Erase Valid'}, 'EO_64k_VALID': {'name': 'EO_64k_VALID', 'bit': 29, 'size': 1, 'desc': '64k Erase Valid'}, 'VCL': {'name': 'VCL', 'bit': 30, 'size': 1, 'desc': 'Vendor Component Lock'}, 'CPPTV': {'name': 'CPPTV', 'bit': 31, 'size': 1, 'desc': 'Component Property Parameter Table Valid'}}}

[*] [DEBUG] + UVSCC : {'name': 'UVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 200, 'size': 4, 'desc': 'Vendor Specific Component Capabilities', 'FIELDS': {'UBES': {'name': 'UBES', 'bit': 0, 'size': 2, 'desc': 'Upper Block/Sector Erase Size'}, 'UWG': {'name': 'UWG', 'bit': 2, 'size': 1, 'desc': 'Upper Write Granularity'}, 'UWSR': {'name': 'UWSR', 'bit': 3, 'size': 1, 'desc': 'Upper Write Status Required'}, 'UWEWS': {'name': 'UWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'UEO': {'name': 'UEO', 'bit': 8, 'size': 8, 'desc': 'Upper Erase Opcode'}, 'WG': {'name': 'WG', 'bit': 2, 'size': 1, 'desc': 'Write Granularity'}, 'WSR': {'name': 'WSR', 'bit': 3, 'size': 1, 'desc': 'Write Status Required'}, 'WEWS': {'name': 'WEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'QER': {'name': 'QER', 'bit': 5, 'size': 3, 'desc': 'Quad Enable Requirements'}, 'EO_4k': {'name': 'EO_4k', 'bit': 8, 'size': 8, 'desc': '4k Erase Opcode'}, 'EO_64k': {'name': 'EO_64k', 'bit': 16, 'size': 8, 'desc': '64k Erase Opcode'}, 'SOFT_RST_SUP': {'name': 'SOFT_RST_SUP', 'bit': 24, 'size': 1, 'desc': 'Soft Reset Supported'}, 'SUSPEND_RESUME_SUP': {'name': 'SUSPEND_RESUME_SUP', 'bit': 25, 'size': 1, 'desc': 'Suspend/Resume Supported'}, 'DEEP_PWRDN_SUP': {'name': 'DEEP_PWRDN_SUP', 'bit': 26, 'size': 1, 'desc': 'Deep Powerdown Supported'}, 'RPMC_SUP': {'name': 'RPMC_SUP', 'bit': 27, 'size': 1, 'desc': 'RPMC Supported'}, 'EO_4k_VALID': {'name': 'EO_4k_VALID', 'bit': 28, 'size': 1, 'desc': '4k Erase Valid'}, 'EO_64k_VALID': {'name': 'EO_64k_VALID', 'bit': 29, 'size': 1, 'desc': '64k Erase Valid'}, 'CPPTV': {'name': 'CPPTV', 'bit': 31, 'size': 1, 'desc': 'Component Property Parameter Table Valid'}}}

[*] [DEBUG] + RC : {'name': 'RC', 'type': 'mm_msgbus', 'port': 195, 'offset': 13312, 'size': 4, 'desc': 'RTC Configuration', 'FIELDS': {'UE': {'name': 'UE', 'bit': 2, 'size': 1, 'desc': 'Upper 128 Byte Enable'}, 'LL': {'name': 'LL', 'bit': 3, 'size': 1, 'desc': 'Lower 128 Byte Lock'}, 'UL': {'name': 'UL', 'bit': 4, 'size': 1, 'desc': 'Upper 128 Byte Lock'}, 'BILD': {'name': 'BILD', 'bit': 31, 'size': 1, 'desc': 'BIOS Interface Lock-Down'}}}

[*] [DEBUG] + BUC : {'name': 'BUC', 'type': 'mm_msgbus', 'port': 195, 'offset': 13332, 'size': 4, 'desc': 'Backed Up Control', 'FIELDS': {'TS': {'name': 'TS', 'bit': 0, 'size': 1, 'desc': 'Top Swap'}}}

[*] [DEBUG] + PM_CFG : {'name': 'PM_CFG', 'type': 'mmio', 'bar': 'PWRMBASE', 'offset': 24, 'size': 4, 'desc': 'Power Management Configuration Reg 1', 'FIELDS': {}}

[*] [DEBUG] + FLMAP0 : {'name': 'FLMAP0', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 20, 'size': 4, 'desc': 'Flash Map 0 Register', 'FIELDS': {'FCBA': {'name': 'FCBA', 'bit': 0, 'size': 8, 'desc': 'Flash Component Base Address'}, 'NC': {'name': 'NC', 'bit': 8, 'size': 2, 'desc': 'Number of Components'}, 'FRBA': {'name': 'FRBA', 'bit': 16, 'size': 8, 'desc': 'Flash Region Base Address'}, 'NR': {'name': 'NR', 'bit': 24, 'size': 3, 'desc': 'Number of Regions'}}}

[*] [DEBUG] + FLMAP1 : {'name': 'FLMAP1', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 24, 'size': 4, 'desc': 'Flash Map 1 Register', 'FIELDS': {'FMBA': {'name': 'FMBA', 'bit': 0, 'size': 8, 'desc': 'Flash Master Base Address'}, 'NM': {'name': 'NM', 'bit': 8, 'size': 3, 'desc': 'Number of Masters'}, 'FPSBA': {'name': 'FPSBA', 'bit': 16, 'size': 8, 'desc': 'Flash PCH Strap Base Address'}, 'PSL': {'name': 'PSL', 'bit': 24, 'size': 8, 'desc': 'PCH Strap Length'}}}

[*] [DEBUG] + FLMAP2 : {'name': 'FLMAP2', 'type': 'mmio', 'bar': 'FDBAR', 'offset': 28, 'size': 4, 'desc': 'Flash Map 2 Register', 'FIELDS': {'FCPUSBA': {'name': 'FCPUSBA', 'bit': 0, 'size': 8, 'desc': 'Flash CPU Strap Base Address'}, 'CPUSL': {'name': 'CPUSL', 'bit': 8, 'size': 8, 'desc': 'CPU Strap Length'}, 'ICCRIBA': {'name': 'ICCRIBA', 'bit': 16, 'size': 8, 'desc': 'ICC Register Init Base Address'}}}

[*] [DEBUG] + FLREG0 : {'name': 'FLREG0', 'type': 'mmio', 'bar': 'FRBA', 'offset': 0, 'size': 4, 'desc': 'Flash Region 0 (Flash Descriptor) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG1 : {'name': 'FLREG1', 'type': 'mmio', 'bar': 'FRBA', 'offset': 4, 'size': 4, 'desc': 'Flash Region 1 (BIOS) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG2 : {'name': 'FLREG2', 'type': 'mmio', 'bar': 'FRBA', 'offset': 8, 'size': 4, 'desc': 'Flash Region 2 (Intel ME) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG3 : {'name': 'FLREG3', 'type': 'mmio', 'bar': 'FRBA', 'offset': 12, 'size': 4, 'desc': 'Flash Region 3 (GBe) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG4 : {'name': 'FLREG4', 'type': 'mmio', 'bar': 'FRBA', 'offset': 16, 'size': 4, 'desc': 'Flash Region 4 (Platform Data) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLREG8 : {'name': 'FLREG8', 'type': 'mmio', 'bar': 'FRBA', 'offset': 32, 'size': 4, 'desc': 'Flash Region 8 (Embedded Controller) Register', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FLMSTR1 : {'name': 'FLMSTR1', 'type': 'mmio', 'bar': 'FMBA', 'offset': 0, 'size': 4, 'desc': 'Flash Master 1', 'FIELDS': {'MRRA': {'name': 'MRRA', 'bit': 8, 'size': 12, 'desc': 'Master Region Read Access'}, 'MRWA': {'name': 'MRWA', 'bit': 20, 'size': 12, 'desc': 'Master Region Write Access'}}}

[*] [DEBUG] + ECTRL : {'name': 'ECTRL', 'type': 'mm_msgbus', 'port': 184, 'offset': 4, 'size': 4, 'desc': 'DCI Control Register', 'FIELDS': {'ENABLE': {'name': 'ENABLE', 'bit': 4, 'size': 1, 'desc': 'ENABLE'}}}

[*] [DEBUG] + TCO1_CNT : {'name': 'TCO1_CNT', 'type': 'iobar', 'bar': 'TCOBASE', 'offset': 8, 'size': 2, 'desc': 'TCO1 Control', 'FIELDS': {'TCO_LOCK': {'name': 'TCO_LOCK', 'bit': 12, 'size': 1, 'desc': 'TCO Lock'}}}

[*] [DEBUG] Missing size entry for MSR_SMM_FEATURE_CONTROL: {'name': 'MSR_SMM_FEATURE_CONTROL', 'type': 'msr', 'msr': 1248, 'desc': 'Enhanced SMM Feature Control'}. Assuming 4 bytes

[*] [DEBUG] + MSR_SMM_FEATURE_CONTROL: {'name': 'MSR_SMM_FEATURE_CONTROL', 'type': 'msr', 'msr': 1248, 'desc': 'Enhanced SMM Feature Control', 'size': 4, 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock bit'}, 'SMM_CODE_CHK_EN': {'name': 'SMM_CODE_CHK_EN', 'bit': 2, 'size': 1, 'desc': 'Prevents SMM from executing code outside the ranges defined by the SMRR'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] + BiosInterfaceLockDown: {'name': 'BiosInterfaceLockDown', 'register': 'BC', 'field': 'BILD', 'desc': 'BIOS Interface Lock-Down'}

[*] [DEBUG] + SpiWriteStatusDis: {'name': 'SpiWriteStatusDis', 'register': 'HSFS', 'field': 'WRSDIS', 'desc': 'Write Status Disable'}

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/pch_3xxlp.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] + P2SBC : {'name': 'P2SBC', 'bus': [0], 'dev': 31, 'fun': 1, 'vid': 32902}

[*] [DEBUG] + PMC : {'name': 'PMC', 'bus': [0], 'dev': 31, 'fun': 2, 'vid': 32902}

[*] [DEBUG] + SMBUS : {'name': 'SMBUS', 'bus': [0], 'dev': 31, 'fun': 4, 'vid': 32902}

[*] [DEBUG] + SPI : {'name': 'SPI', 'bus': [0], 'dev': 31, 'fun': 5, 'vid': 32902}

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] + HDABAR : {'name': 'HDABAR', 'bus': [0], 'dev': 31, 'fun': 3, 'reg': 16, 'width': 8, 'mask': 18446744073709535232, 'size': 4096, 'desc': 'HD Audio Base'}

[*] [DEBUG] + SPIBAR : {'name': 'SPIBAR', 'bus': [0], 'dev': 31, 'fun': 5, 'reg': 16, 'width': 4, 'mask': 4294963200, 'size': 4096, 'desc': 'SPI Controller Register Range', 'offset': 0}

[*] [DEBUG] + PWRMBASE : {'name': 'PWRMBASE', 'register': 'PWRMBASE', 'base_field': 'BA', 'size': 4096, 'fixed_address': 4261412864, 'desc': 'Power Management Register Range'}

[*] [DEBUG] + SBREGBAR : {'name': 'SBREGBAR', 'register': 'SBREG_BAR', 'base_field': 'RBA', 'size': 16777216, 'fixed_address': 4244635648, 'desc': 'Sideband Register Access BAR'}

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'register': 'ABASE', 'base_field': 'BA', 'size': 256, 'fixed_address': 6144, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + PMBASE : {'name': 'PMBASE', 'register': 'ABASE', 'base_field': 'BA', 'size': 256, 'fixed_address': 6144, 'desc': 'ACPI Base Address'}

[*] [DEBUG] + TCOBASE : {'name': 'TCOBASE', 'register': 'TCOBASE', 'base_field': 'TCOBA', 'size': 32, 'desc': 'TCO Base Address'}

[*] [DEBUG] + SMBUS_BASE : {'name': 'SMBUS_BASE', 'bus': [0], 'dev': 31, 'fun': 4, 'reg': 32, 'mask': 65504, 'size': 128, 'desc': 'SMBus Base Address'}

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + SBREG_BAR : {'name': 'SBREG_BAR', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 16, 'size': 4, 'desc': 'Sideband Register Access BAR', 'FIELDS': {'RBA': {'name': 'RBA', 'bit': 24, 'size': 8, 'desc': 'Register Base Address'}}}

[*] [DEBUG] + P2SBC : {'name': 'P2SBC', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 224, 'size': 2, 'desc': 'P2SB Configuration Register', 'FIELDS': {'HIDE': {'name': 'HIDE', 'bit': 8, 'size': 1, 'desc': 'Hide SBREG_BAR'}}}

[*] [DEBUG] + P2SB_HIDE : {'name': 'P2SB_HIDE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 1, 'offset': 225, 'size': 1, 'desc': 'P2SB Configuration Register hide-unhide', 'FIELDS': {'HIDE': {'name': 'HIDE', 'bit': 0, 'size': 1, 'desc': 'Hide SBREG_BAR'}}}

[*] [DEBUG] + ABASE : {'name': 'ABASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 64, 'size': 4, 'desc': 'ACPI Base Address', 'FIELDS': {'Base': {'name': 'Base', 'bit': 7, 'size': 9, 'desc': 'Base Address'}, 'STYPE': {'name': 'STYPE', 'bit': 0, 'size': 1, 'desc': 'Space Type (always 1 - I/O space)'}, 'BA': {'name': 'BA', 'bit': 8, 'size': 24, 'desc': 'Base Address'}}}

[*] [DEBUG] + PWRMBASE : {'name': 'PWRMBASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 16, 'size': 4, 'desc': 'PM Base Address', 'FIELDS': {'STYPE': {'name': 'STYPE', 'bit': 0, 'size': 1, 'desc': 'Space Type (always 0 - memory space)'}, 'BA': {'name': 'BA', 'bit': 14, 'size': 18, 'desc': 'Base Address'}}}

[*] [DEBUG] + GEN_PMCON_1 : {'name': 'GEN_PMCON_1', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 160, 'size': 4, 'desc': 'General PM Configuration A', 'FIELDS': {'SMI_LOCK': {'name': 'SMI_LOCK', 'bit': 4, 'size': 1, 'desc': 'SMI_LOCK'}}}

[*] [DEBUG] + GEN_PMCON_2 : {'name': 'GEN_PMCON_2', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 164, 'size': 4, 'desc': 'General PM Configuration B', 'FIELDS': {}}

[*] [DEBUG] + ACTL : {'name': 'ACTL', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 2, 'offset': 68, 'size': 4, 'desc': 'ACPI Control', 'FIELDS': {'SCIS': {'name': 'SCIS', 'bit': 0, 'size': 3, 'desc': 'SCI IRQ Select'}, 'EN': {'name': 'EN', 'bit': 7, 'size': 1, 'desc': 'ACPI Enable'}, 'PWRM_EN': {'name': 'PWRM_EN', 'bit': 8, 'size': 1, 'desc': 'PWRM Enable'}}}

[*] [DEBUG] + PM_CFG : {'name': 'PM_CFG', 'type': 'mmio', 'bar': 'PWRMBASE', 'offset': 24, 'size': 4, 'desc': 'Power Management Configuration Reg 1', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_VID : {'name': 'SMBUS_VID', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 0, 'size': 2, 'desc': 'VID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_DID : {'name': 'SMBUS_DID', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 2, 'size': 2, 'desc': 'DID', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_CMD : {'name': 'SMBUS_CMD', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 4, 'size': 2, 'desc': 'CMD', 'FIELDS': {}}

[*] [DEBUG] + SMBUS_HCFG : {'name': 'SMBUS_HCFG', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 64, 'size': 1, 'desc': 'Host Configuration', 'FIELDS': {'HST_EN': {'name': 'HST_EN', 'bit': 0, 'size': 1, 'desc': 'HST_EN'}, 'SMB_SMI_EN': {'name': 'SMB_SMI_EN', 'bit': 1, 'size': 1, 'desc': 'SMB_SMI_EN'}, 'I2C_EN': {'name': 'I2C_EN', 'bit': 2, 'size': 1, 'desc': 'I2C_EN'}, 'SSRESET': {'name': 'SSRESET', 'bit': 3, 'size': 1, 'desc': 'SSRESET'}, 'SPD_WD': {'name': 'SPD_WD', 'bit': 4, 'size': 1, 'desc': 'SPD_WD'}}}

[*] [DEBUG] + TCOBASE : {'name': 'TCOBASE', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 80, 'size': 4, 'desc': 'TCO Base Address', 'FIELDS': {'IOS': {'name': 'IOS', 'bit': 0, 'size': 1, 'desc': 'I/O space'}, 'TCOBA': {'name': 'TCOBA', 'bit': 5, 'size': 11, 'desc': 'TCO Base Address'}}}

[*] [DEBUG] + TCOCTL : {'name': 'TCOCTL', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 4, 'offset': 84, 'size': 4, 'desc': 'TCO Control', 'FIELDS': {'TCO_BASE_LOCK': {'name': 'TCO_BASE_LOCK', 'bit': 0, 'size': 1, 'desc': 'TCO Base Lock'}, 'TCO_BASE_EN': {'name': 'TCO_BASE_EN', 'bit': 8, 'size': 1, 'desc': 'TCO Base Enable'}}}

[*] [DEBUG] + BC : {'name': 'BC', 'type': 'pcicfg', 'bus': [0], 'dev': 31, 'fun': 5, 'offset': 220, 'size': 4, 'desc': 'BIOS Control', 'FIELDS': {'BIOSWE': {'name': 'BIOSWE', 'bit': 0, 'size': 1, 'desc': 'BIOS Write Enable'}, 'BLE': {'name': 'BLE', 'bit': 1, 'size': 1, 'desc': 'BIOS Lock Enable'}, 'SRC': {'name': 'SRC', 'bit': 2, 'size': 2, 'desc': 'SPI Read Configuration'}, 'TSS': {'name': 'TSS', 'bit': 4, 'size': 1, 'desc': 'Top Swap Status'}, 'SMM_BWP': {'name': 'SMM_BWP', 'bit': 5, 'size': 1, 'desc': 'SMM BIOS Write Protection'}, 'BBS': {'name': 'BBS', 'bit': 6, 'size': 1, 'desc': 'Boot BIOS Strap'}, 'BILD': {'name': 'BILD', 'bit': 7, 'size': 1, 'desc': 'BIOS Interface Lock Down'}}}

[*] [DEBUG] + HSFS : {'name': 'HSFS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 4, 'size': 4, 'desc': 'Hardware Sequencing Flash Status Register', 'FIELDS': {'FDONE': {'name': 'FDONE', 'bit': 0, 'size': 1, 'desc': 'Flash Cycle Done'}, 'FCERR': {'name': 'FCERR', 'bit': 1, 'size': 1, 'desc': 'Flash Cycle Error'}, 'AEL': {'name': 'AEL', 'bit': 2, 'size': 1, 'desc': 'Access Error Log'}, 'BERASE': {'name': 'BERASE', 'bit': 3, 'size': 2, 'desc': 'Block/Sector Erase Size'}, 'SCIP': {'name': 'SCIP', 'bit': 5, 'size': 1, 'desc': 'SPI cycle in progress'}, 'FDOPSS': {'name': 'FDOPSS', 'bit': 13, 'size': 1, 'desc': 'Flash Descriptor Override Pin-Strap Status'}, 'FDV': {'name': 'FDV', 'bit': 14, 'size': 1, 'desc': 'Flash Descriptor Valid'}, 'FLOCKDN': {'name': 'FLOCKDN', 'bit': 15, 'size': 1, 'desc': 'Flash Configuration Lock-Down'}, 'WRSDIS': {'name': 'WRSDIS', 'bit': 11, 'size': 1, 'desc': 'Write status disable'}, 'PR34LKD': {'name': 'PR34LKD', 'bit': 12, 'size': 1, 'desc': 'PRR3 PRR4 Lock-Down'}, 'FGO': {'name': 'FGO', 'bit': 16, 'size': 1, 'desc': 'Flash cycle go'}, 'FCYCLE': {'name': 'FCYCLE', 'bit': 17, 'size': 4, 'desc': 'Flash Cycle Type'}, 'WET': {'name': 'WET', 'bit': 21, 'size': 1, 'desc': 'Write Enable Type'}, 'FDBC': {'name': 'FDBC', 'bit': 24, 'size': 6, 'desc': 'Flash Data Byte Count'}, 'FSMIE': {'name': 'FSMIE', 'bit': 31, 'size': 1, 'desc': 'Flash SPI SMI# Enable'}}}

[*] [DEBUG] + FREG0_FLASHD : {'name': 'FREG0_FLASHD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 84, 'size': 4, 'desc': 'Flash Region 0 (Flash Descriptor)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG1_BIOS : {'name': 'FREG1_BIOS', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 88, 'size': 4, 'desc': 'Flash Region 1 (BIOS)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG2_ME : {'name': 'FREG2_ME', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 92, 'size': 4, 'desc': 'Flash Region 2 (ME)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG3_GBE : {'name': 'FREG3_GBE', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 96, 'size': 4, 'desc': 'Flash Region 3 (GBe)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG4_PD : {'name': 'FREG4_PD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 100, 'size': 4, 'desc': 'Flash Region 4 (Platform Data)', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + FREG5 : {'name': 'FREG5', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 104, 'size': 4, 'desc': 'Flash Region 5', 'FIELDS': {'RB': {'name': 'RB', 'bit': 0, 'size': 15, 'desc': 'Region Base'}, 'RL': {'name': 'RL', 'bit': 16, 'size': 15, 'desc': 'Region Limit'}}}

[*] [DEBUG] + PR0 : {'name': 'PR0', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 132, 'size': 4, 'desc': 'Protected Range 0', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR1 : {'name': 'PR1', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 136, 'size': 4, 'desc': 'Protected Range 1', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR2 : {'name': 'PR2', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 140, 'size': 4, 'desc': 'Protected Range 2', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR3 : {'name': 'PR3', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 144, 'size': 4, 'desc': 'Protected Range 3', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + PR4 : {'name': 'PR4', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 148, 'size': 4, 'desc': 'Protected Range 4', 'FIELDS': {'PRB': {'name': 'PRB', 'bit': 0, 'size': 15, 'desc': 'PRB'}, 'RPE': {'name': 'RPE', 'bit': 15, 'size': 1, 'desc': 'RPE'}, 'PRL': {'name': 'PRL', 'bit': 16, 'size': 15, 'desc': 'PRL'}, 'WPE': {'name': 'WPE', 'bit': 31, 'size': 1, 'desc': 'WPE'}}}

[*] [DEBUG] + FDOC : {'name': 'FDOC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 180, 'size': 4, 'desc': 'Flash Descriptor Observability Control Register', 'FIELDS': {'FDSI': {'name': 'FDSI', 'bit': 2, 'size': 10, 'desc': 'Flash Descriptor Section Index'}, 'FDSS': {'name': 'FDSS', 'bit': 12, 'size': 3, 'desc': 'Flash Descriptor Section Select'}}}

[*] [DEBUG] + FDOD : {'name': 'FDOD', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 184, 'size': 4, 'desc': 'Flash Descriptor Observability Data Register', 'FIELDS': {'FDSD': {'name': 'FDSD', 'bit': 0, 'size': 32, 'desc': 'Flash Descriptor Section Data'}}}

[*] [DEBUG] + LVSCC : {'name': 'LVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 196, 'size': 4, 'desc': 'Vendor Specific Component Capabilities', 'FIELDS': {'LBES': {'name': 'LBES', 'bit': 0, 'size': 2, 'desc': 'Lower Block/Sector Erase Size'}, 'LWG': {'name': 'LWG', 'bit': 2, 'size': 1, 'desc': 'Lower Write Granularity'}, 'LWSR': {'name': 'LWSR', 'bit': 3, 'size': 1, 'desc': 'Lower Write Status Required'}, 'LWEWS': {'name': 'LWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'LEO': {'name': 'LEO', 'bit': 8, 'size': 8, 'desc': 'Lower Erase Opcode'}, 'WG': {'name': 'WG', 'bit': 2, 'size': 1, 'desc': 'Write Granularity'}, 'WSR': {'name': 'WSR', 'bit': 3, 'size': 1, 'desc': 'Write Status Required'}, 'WEWS': {'name': 'WEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'QER': {'name': 'QER', 'bit': 5, 'size': 3, 'desc': 'Quad Enable Requirements'}, 'EO_4k': {'name': 'EO_4k', 'bit': 8, 'size': 8, 'desc': '4k Erase Opcode'}, 'EO_64k': {'name': 'EO_64k', 'bit': 16, 'size': 8, 'desc': '64k Erase Opcode'}, 'SOFT_RST_SUP': {'name': 'SOFT_RST_SUP', 'bit': 24, 'size': 1, 'desc': 'Soft Reset Supported'}, 'SUSPEND_RESUME_SUP': {'name': 'SUSPEND_RESUME_SUP', 'bit': 25, 'size': 1, 'desc': 'Suspend/Resume Supported'}, 'DEEP_PWRDN_SUP': {'name': 'DEEP_PWRDN_SUP', 'bit': 26, 'size': 1, 'desc': 'Deep Powerdown Supported'}, 'RPMC_SUP': {'name': 'RPMC_SUP', 'bit': 27, 'size': 1, 'desc': 'RPMC Supported'}, 'EO_4k_VALID': {'name': 'EO_4k_VALID', 'bit': 28, 'size': 1, 'desc': '4k Erase Valid'}, 'EO_64k_VALID': {'name': 'EO_64k_VALID', 'bit': 29, 'size': 1, 'desc': '64k Erase Valid'}, 'VCL': {'name': 'VCL', 'bit': 30, 'size': 1, 'desc': 'Vendor Component Lock'}, 'CPPTV': {'name': 'CPPTV', 'bit': 31, 'size': 1, 'desc': 'Component Property Parameter Table Valid'}}}

[*] [DEBUG] + UVSCC : {'name': 'UVSCC', 'type': 'mmio', 'bar': 'SPIBAR', 'offset': 200, 'size': 4, 'desc': 'Vendor Specific Component Capabilities', 'FIELDS': {'UBES': {'name': 'UBES', 'bit': 0, 'size': 2, 'desc': 'Upper Block/Sector Erase Size'}, 'UWG': {'name': 'UWG', 'bit': 2, 'size': 1, 'desc': 'Upper Write Granularity'}, 'UWSR': {'name': 'UWSR', 'bit': 3, 'size': 1, 'desc': 'Upper Write Status Required'}, 'UWEWS': {'name': 'UWEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'UEO': {'name': 'UEO', 'bit': 8, 'size': 8, 'desc': 'Upper Erase Opcode'}, 'WG': {'name': 'WG', 'bit': 2, 'size': 1, 'desc': 'Write Granularity'}, 'WSR': {'name': 'WSR', 'bit': 3, 'size': 1, 'desc': 'Write Status Required'}, 'WEWS': {'name': 'WEWS', 'bit': 4, 'size': 1, 'desc': 'Write Enable on Write Status'}, 'QER': {'name': 'QER', 'bit': 5, 'size': 3, 'desc': 'Quad Enable Requirements'}, 'EO_4k': {'name': 'EO_4k', 'bit': 8, 'size': 8, 'desc': '4k Erase Opcode'}, 'EO_64k': {'name': 'EO_64k', 'bit': 16, 'size': 8, 'desc': '64k Erase Opcode'}, 'SOFT_RST_SUP': {'name': 'SOFT_RST_SUP', 'bit': 24, 'size': 1, 'desc': 'Soft Reset Supported'}, 'SUSPEND_RESUME_SUP': {'name': 'SUSPEND_RESUME_SUP', 'bit': 25, 'size': 1, 'desc': 'Suspend/Resume Supported'}, 'DEEP_PWRDN_SUP': {'name': 'DEEP_PWRDN_SUP', 'bit': 26, 'size': 1, 'desc': 'Deep Powerdown Supported'}, 'RPMC_SUP': {'name': 'RPMC_SUP', 'bit': 27, 'size': 1, 'desc': 'RPMC Supported'}, 'EO_4k_VALID': {'name': 'EO_4k_VALID', 'bit': 28, 'size': 1, 'desc': '4k Erase Valid'}, 'EO_64k_VALID': {'name': 'EO_64k_VALID', 'bit': 29, 'size': 1, 'desc': '64k Erase Valid'}, 'CPPTV': {'name': 'CPPTV', 'bit': 31, 'size': 1, 'desc': 'Component Property Parameter Table Valid'}}}

[*] [DEBUG] + RC : {'name': 'RC', 'type': 'mm_msgbus', 'port': 195, 'offset': 13312, 'size': 4, 'desc': 'RTC Configuration', 'FIELDS': {'UE': {'name': 'UE', 'bit': 2, 'size': 1, 'desc': 'Upper 128 Byte Enable'}, 'LL': {'name': 'LL', 'bit': 3, 'size': 1, 'desc': 'Lower 128 Byte Lock'}, 'UL': {'name': 'UL', 'bit': 4, 'size': 1, 'desc': 'Upper 128 Byte Lock'}, 'BILD': {'name': 'BILD', 'bit': 31, 'size': 1, 'desc': 'BIOS Interface Lock-Down'}}}

[*] [DEBUG] + BUC : {'name': 'BUC', 'type': 'mm_msgbus', 'port': 195, 'offset': 13332, 'size': 4, 'desc': 'Backed Up Control', 'FIELDS': {'TS': {'name': 'TS', 'bit': 0, 'size': 1, 'desc': 'Top Swap'}}}

[*] [DEBUG] + ECTRL : {'name': 'ECTRL', 'type': 'mm_msgbus', 'port': 184, 'offset': 4, 'size': 4, 'desc': 'DCI Control Register', 'FIELDS': {'ENABLE': {'name': 'ENABLE', 'bit': 4, 'size': 1, 'desc': 'ENABLE'}}}

[*] [DEBUG] + TCO1_CNT : {'name': 'TCO1_CNT', 'type': 'iobar', 'bar': 'TCOBASE', 'offset': 8, 'size': 2, 'desc': 'TCO1 Control', 'FIELDS': {'TCO_LOCK': {'name': 'TCO_LOCK', 'bit': 12, 'size': 1, 'desc': 'TCO Lock'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] + BiosInterfaceLockDown: {'name': 'BiosInterfaceLockDown', 'register': 'BC', 'field': 'BILD', 'desc': 'BIOS Interface Lock-Down'}

[*] [DEBUG] + SpiWriteStatusDis: {'name': 'SpiWriteStatusDis', 'register': 'HSFS', 'field': 'WRSDIS', 'desc': 'Write Status Disable'}

[*] [DEBUG] + SMILock : {'name': 'SMILock', 'register': 'GEN_PMCON_1', 'field': 'SMI_LOCK', 'desc': 'SMI Global Configuration Lock'}

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/iommu.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + VTBAR_VER : {'name': 'VTBAR_VER', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 0, 'size': 4, 'desc': 'Version', 'FIELDS': {'MIN': {'name': 'MIN', 'bit': 0, 'size': 4, 'desc': 'Minor Version Number'}, 'MAX': {'name': 'MAX', 'bit': 4, 'size': 4, 'desc': 'Major Version Number'}}}

[*] [DEBUG] + VTBAR_CAP : {'name': 'VTBAR_CAP', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 8, 'size': 8, 'desc': 'Capability', 'FIELDS': {'ND': {'name': 'ND', 'bit': 0, 'size': 2, 'desc': 'Number of Domains Supported'}, 'Rsvd': {'name': 'Rsvd', 'bit': 3, 'size': 1, 'desc': 'Reserved'}, 'RWBF': {'name': 'RWBF', 'bit': 4, 'size': 1, 'desc': 'Required Write-Buffer Flushing'}, 'PLMR': {'name': 'PLMR', 'bit': 5, 'size': 1, 'desc': 'Protected Low-Memory Region'}, 'PHMR': {'name': 'PHMR', 'bit': 6, 'size': 1, 'desc': 'Protected High-Memory Region'}, 'CM': {'name': 'CM', 'bit': 7, 'size': 1, 'desc': 'Caching Mode'}, 'SAGAW': {'name': 'SAGAW', 'bit': 8, 'size': 5, 'desc': 'Supported Adjusted Guest Address Width'}, 'R0': {'name': 'R0', 'bit': 13, 'size': 3, 'desc': 'Reserved'}, 'MGAW': {'name': 'MGAW', 'bit': 16, 'size': 6, 'desc': 'Maximum Guest Address Width'}, 'ZLR': {'name': 'ZLR', 'bit': 22, 'size': 1, 'desc': 'Zero Length Read'}, 'R1': {'name': 'R1', 'bit': 23, 'size': 1, 'desc': 'Reserved'}, 'FRO': {'name': 'FRO', 'bit': 24, 'size': 10, 'desc': 'Fault-Recording Registrer Offset'}, 'SLLPS': {'name': 'SLLPS', 'bit': 34, 'size': 4, 'desc': 'Second Level Large Page Support'}, 'R2': {'name': 'R2', 'bit': 38, 'size': 1, 'desc': 'Reserved'}, 'PSI': {'name': 'PSI', 'bit': 39, 'size': 1, 'desc': 'Page Selective Invalidation'}, 'NFR': {'name': 'NFR', 'bit': 40, 'size': 8, 'desc': 'Number of Fault-Recording Registers'}, 'MAMV': {'name': 'MAMV', 'bit': 48, 'size': 6, 'desc': 'Maximum Address Mask Value'}, 'DWD': {'name': 'DWD', 'bit': 54, 'size': 1, 'desc': 'Write Draining'}, 'DRD': {'name': 'DRD', 'bit': 55, 'size': 1, 'desc': 'Read Draining'}, 'FL1GP': {'name': 'FL1GP', 'bit': 56, 'size': 1, 'desc': 'First Level 1-GB Page Support'}, 'R3': {'name': 'R3', 'bit': 57, 'size': 2, 'desc': 'Reserved'}, 'PI': {'name': 'PI', 'bit': 59, 'size': 1, 'desc': 'Posted Interrupts Support'}, 'R4': {'name': 'R4', 'bit': 60, 'size': 4, 'desc': 'Reserved'}}}

[*] [DEBUG] + VTBAR_ECAP : {'name': 'VTBAR_ECAP', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 16, 'size': 8, 'desc': 'Global Command', 'FIELDS': {'C': {'name': 'C', 'bit': 0, 'size': 1, 'desc': 'Page-walk Coherency'}, 'QI': {'name': 'QI', 'bit': 1, 'size': 1, 'desc': 'Queued Invalidation Support'}, 'DT': {'name': 'DT', 'bit': 2, 'size': 1, 'desc': 'Device-TLB Support'}, 'IR': {'name': 'IR', 'bit': 3, 'size': 1, 'desc': 'Interrupt Remapping Support'}, 'EIM': {'name': 'EIM', 'bit': 4, 'size': 1, 'desc': 'Extended Interrupt Mode'}, 'R0': {'name': 'R0', 'bit': 5, 'size': 1, 'desc': 'Reserved'}, 'PT': {'name': 'PT', 'bit': 6, 'size': 1, 'desc': 'Pass Through'}, 'SC': {'name': 'SC', 'bit': 7, 'size': 1, 'desc': 'Snoop Control'}, 'IRO': {'name': 'IRO', 'bit': 8, 'size': 10, 'desc': 'IOTLB Register Offset'}, 'R1': {'name': 'R1', 'bit': 18, 'size': 2, 'desc': 'Reserved'}, 'MHMV': {'name': 'MHMV', 'bit': 20, 'size': 4, 'desc': 'Maximum Handle Mask Value'}, 'ECS': {'name': 'ECS', 'bit': 24, 'size': 1, 'desc': 'Extended Context Support'}, 'MTS': {'name': 'MTS', 'bit': 25, 'size': 1, 'desc': 'Memory Type Support'}, 'NEST': {'name': 'NEST', 'bit': 26, 'size': 1, 'desc': 'Nested Translation Support'}, 'DIS': {'name': 'DIS', 'bit': 27, 'size': 1, 'desc': 'Deferred Invalidate Support'}, 'PASID': {'name': 'PASID', 'bit': 28, 'size': 1, 'desc': 'Process Address Space ID Support'}, 'PRS': {'name': 'PRS', 'bit': 29, 'size': 1, 'desc': 'Page Request Support'}, 'ERS': {'name': 'ERS', 'bit': 30, 'size': 1, 'desc': 'Execute Request Support'}, 'SRS': {'name': 'SRS', 'bit': 31, 'size': 1, 'desc': 'Supervisor Request Support'}, 'R2': {'name': 'R2', 'bit': 32, 'size': 1, 'desc': 'Reserved'}, 'NWFS': {'name': 'NWFS', 'bit': 33, 'size': 1, 'desc': 'No Write Flag Support'}, 'EAFS': {'name': 'EAFS', 'bit': 34, 'size': 1, 'desc': 'Extended Accessed Flag Support'}, 'PSS': {'name': 'PSS', 'bit': 35, 'size': 5, 'desc': 'PASID Size Supported'}, 'R3': {'name': 'R3', 'bit': 40, 'size': 24, 'desc': 'Reserved'}}}

[*] [DEBUG] + VTBAR_GCMD : {'name': 'VTBAR_GCMD', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 24, 'size': 4, 'desc': 'Global Command', 'FIELDS': {'Rsvd': {'name': 'Rsvd', 'bit': 28, 'size': 1, 'desc': 'Reserved'}, 'CFI': {'name': 'CFI', 'bit': 23, 'size': 1, 'desc': 'Compatibility Format Interrupt'}, 'SIRTP': {'name': 'SIRTP', 'bit': 24, 'size': 1, 'desc': 'Set Interrupt Remap Table Pointer'}, 'IRE': {'name': 'IRE', 'bit': 25, 'size': 1, 'desc': 'Interrupt Remapping Enable'}, 'QIE': {'name': 'QIE', 'bit': 26, 'size': 1, 'desc': 'Queued Invalidation Enable'}, 'WBF': {'name': 'WBF', 'bit': 27, 'size': 1, 'desc': 'Write Buffer Flush'}, 'SFL': {'name': 'SFL', 'bit': 29, 'size': 1, 'desc': 'Set Fault Log'}, 'SRTP': {'name': 'SRTP', 'bit': 30, 'size': 1, 'desc': 'Set Root Table Pointer'}, 'TE': {'name': 'TE', 'bit': 31, 'size': 1, 'desc': 'Translation Enable'}}}

[*] [DEBUG] + VTBAR_GSTS : {'name': 'VTBAR_GSTS', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 28, 'size': 4, 'desc': 'Global Status', 'FIELDS': {'Rsvd': {'name': 'Rsvd', 'bit': 28, 'size': 1, 'desc': 'Reserved'}, 'CFIS': {'name': 'CFIS', 'bit': 23, 'size': 1, 'desc': 'Compatibility Format Interrupt Status'}, 'IRTPS': {'name': 'IRTPS', 'bit': 24, 'size': 1, 'desc': 'Interrupt Remap Table Pointer Status'}, 'IRES': {'name': 'IRES', 'bit': 25, 'size': 1, 'desc': 'Interrupt Remapping Enable Status'}, 'QIES': {'name': 'QIES', 'bit': 26, 'size': 1, 'desc': 'Queued Invalidation Enable Status'}, 'WBFS': {'name': 'WBFS', 'bit': 27, 'size': 1, 'desc': 'Write Buffer Flush Status'}, 'FLS': {'name': 'FLS', 'bit': 29, 'size': 1, 'desc': 'Fault Log Status'}, 'RTPS': {'name': 'RTPS', 'bit': 30, 'size': 1, 'desc': 'Root Table Pointer Status'}, 'TES': {'name': 'TES', 'bit': 31, 'size': 1, 'desc': 'Translation Enable Status'}}}

[*] [DEBUG] + VTBAR_RTADDR : {'name': 'VTBAR_RTADDR', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 32, 'size': 8, 'desc': 'Root-Entry Table Address', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 11, 'desc': 'Reserved'}, 'RTT': {'name': 'RTT', 'bit': 11, 'size': 1, 'desc': 'Root Table Type'}, 'RTA': {'name': 'RTA', 'bit': 12, 'size': 52, 'desc': 'Root Table Address'}}}

[*] [DEBUG] + VTBAR_CCMD : {'name': 'VTBAR_CCMD', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 40, 'size': 8, 'desc': 'Context Command', 'FIELDS': {'DID': {'name': 'DID', 'bit': 0, 'size': 16, 'desc': 'Device ID'}, 'SID': {'name': 'SID', 'bit': 16, 'size': 16, 'desc': 'Source ID'}, 'FM': {'name': 'FM', 'bit': 32, 'size': 2, 'desc': 'Function Mask'}, 'R': {'name': 'R', 'bit': 34, 'size': 25, 'desc': 'Reserved'}, 'CAIG': {'name': 'CAIG', 'bit': 59, 'size': 2, 'desc': 'Context Actual Invalidation Granularity'}, 'CIRG': {'name': 'CIRG', 'bit': 61, 'size': 2, 'desc': 'Context Invalidation Request Granularity'}, 'ICC': {'name': 'ICC', 'bit': 63, 'size': 1, 'desc': 'Invalidate Context-Cache'}}}

[*] [DEBUG] + VTBAR_IVA : {'name': 'VTBAR_IVA', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 0, 'size': 8, 'desc': 'Invalidate Address', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_IOTLB : {'name': 'VTBAR_IOTLB', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 8, 'size': 8, 'desc': 'IOTLB Invalidate', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_FSTS : {'name': 'VTBAR_FSTS', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 52, 'size': 4, 'desc': 'Fault Status', 'FIELDS': {'PFO': {'name': 'PFO', 'bit': 0, 'size': 1, 'desc': 'Primary Fault Overflow'}, 'PPF': {'name': 'PPF', 'bit': 1, 'size': 1, 'desc': 'Primary Pending Fault'}, 'AFO': {'name': 'AFO', 'bit': 2, 'size': 1, 'desc': 'Advanced Fault Overflow'}, 'APF': {'name': 'APF', 'bit': 3, 'size': 1, 'desc': 'Advanced Pending Fault'}, 'IQE': {'name': 'IQE', 'bit': 4, 'size': 1, 'desc': 'Invalidation Queue Error'}, 'ICE': {'name': 'ICE', 'bit': 5, 'size': 1, 'desc': 'Invalidation Completion Error'}, 'ITE': {'name': 'ITE', 'bit': 6, 'size': 1, 'desc': 'Invalidation Time-out Error'}, 'PRO': {'name': 'PRO', 'bit': 7, 'size': 1, 'desc': 'Page Request Overflow'}, 'FRI': {'name': 'FRI', 'bit': 8, 'size': 7, 'desc': 'Fault Record Index'}}}

[*] [DEBUG] + VTBAR_FECTL : {'name': 'VTBAR_FECTL', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 56, 'size': 4, 'desc': 'Fault Event Control', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 30, 'desc': 'Reserved'}, 'IP': {'name': 'IP', 'bit': 30, 'size': 1, 'desc': 'Interrupt Pending'}, 'IM': {'name': 'IM', 'bit': 31, 'size': 1, 'desc': 'Interrupt Mask'}}}

[*] [DEBUG] + VTBAR_FEDATA : {'name': 'VTBAR_FEDATA', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 60, 'size': 4, 'desc': 'Fault Event Data', 'FIELDS': {'IMD': {'name': 'IMD', 'bit': 0, 'size': 16, 'desc': 'Interrupt Message Data'}, 'EIMD': {'name': 'EIMD', 'bit': 16, 'size': 16, 'desc': 'Extended Interrupt Message Data'}}}

[*] [DEBUG] + VTBAR_FEADDR : {'name': 'VTBAR_FEADDR', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 64, 'size': 4, 'desc': 'Fault Event Address', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 2, 'desc': 'Reserved'}, 'MA': {'name': 'MA', 'bit': 2, 'size': 30, 'desc': 'Message Address'}}}

[*] [DEBUG] + VTBAR_FEUADDR : {'name': 'VTBAR_FEUADDR', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 68, 'size': 4, 'desc': 'Fault Event Upper Address', 'FIELDS': {'MUA': {'name': 'MUA', 'bit': 0, 'size': 32, 'desc': 'Message Upper Address'}}}

[*] [DEBUG] + VTBAR_FRCDL : {'name': 'VTBAR_FRCDL', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 0, 'size': 8, 'desc': 'Fault Recording (Low)', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_FRCDH : {'name': 'VTBAR_FRCDH', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 8, 'size': 8, 'desc': 'Fault Recording (High)', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_PMEN : {'name': 'VTBAR_PMEN', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 100, 'size': 4, 'desc': 'Protected Memory Enable', 'FIELDS': {'PRS': {'name': 'PRS', 'bit': 0, 'size': 1, 'desc': 'Protected Region Status'}, 'EPM': {'name': 'EPM', 'bit': 31, 'size': 1, 'desc': 'Enable Protected Memory'}}}

[*] [DEBUG] + VTBAR_PLMBASE : {'name': 'VTBAR_PLMBASE', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 104, 'size': 4, 'desc': 'Protected Memory Low Base', 'FIELDS': {'PLMB': {'name': 'PLMB', 'bit': 12, 'size': 20, 'desc': 'Protected Low-Memory Base'}}}

[*] [DEBUG] + VTBAR_PLMLIMIT : {'name': 'VTBAR_PLMLIMIT', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 108, 'size': 4, 'desc': 'Protected Memory Low Limit', 'FIELDS': {'PLML': {'name': 'PLML', 'bit': 12, 'size': 20, 'desc': 'Protected Low-Memory Limit'}}}

[*] [DEBUG] + VTBAR_PHMBASE : {'name': 'VTBAR_PHMBASE', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 112, 'size': 8, 'desc': 'Protected Memory High Base', 'FIELDS': {'PHMB': {'name': 'PHMB', 'bit': 12, 'size': 52, 'desc': 'Protected High-Memory Base'}}}

[*] [DEBUG] + VTBAR_PHMLIMIT : {'name': 'VTBAR_PHMLIMIT', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 120, 'size': 8, 'desc': 'Protected Memory High Limit', 'FIELDS': {'PHML': {'name': 'PHML', 'bit': 12, 'size': 52, 'desc': 'Protected High-Memory Limit'}}}

[*] [DEBUG] + VTBAR_IQH : {'name': 'VTBAR_IQH', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 128, 'size': 8, 'desc': 'Invalidation Queue Head', 'FIELDS': {'QH': {'name': 'QH', 'bit': 4, 'size': 15, 'desc': 'Queue Head'}}}

[*] [DEBUG] + VTBAR_IQT : {'name': 'VTBAR_IQT', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 136, 'size': 8, 'desc': 'Invalidation Queue Tail', 'FIELDS': {'QT': {'name': 'QT', 'bit': 4, 'size': 15, 'desc': 'Queue Tail'}}}

[*] [DEBUG] + VTBAR_IQA : {'name': 'VTBAR_IQA', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 144, 'size': 8, 'desc': 'Invalidation Queue Address', 'FIELDS': {'QS': {'name': 'QS', 'bit': 0, 'size': 3, 'desc': 'Queue Size'}, 'IQA': {'name': 'IQA', 'bit': 12, 'size': 52, 'desc': 'Invalidation Queue Base Address'}}}

[*] [DEBUG] + VTBAR_ICS : {'name': 'VTBAR_ICS', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 156, 'size': 4, 'desc': 'Invalidation Completion Status', 'FIELDS': {'IWC': {'name': 'IWC', 'bit': 0, 'size': 1, 'desc': 'Invalidation Wait Descriptor Complete'}}}

[*] [DEBUG] + VTBAR_IECTL : {'name': 'VTBAR_IECTL', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 160, 'size': 4, 'desc': 'Invalidation Event Control', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_IEDATA : {'name': 'VTBAR_IEDATA', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 164, 'size': 4, 'desc': 'Invalidation Event Data', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_IEADDR : {'name': 'VTBAR_IEADDR', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 168, 'size': 4, 'desc': 'Invalidation Event Address', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_IEUADDR : {'name': 'VTBAR_IEUADDR', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 172, 'size': 4, 'desc': 'Invalidation Event Address', 'FIELDS': {}}

[*] [DEBUG] + VTBAR_IRTA : {'name': 'VTBAR_IRTA', 'type': 'mmio', 'bar': 'VTBAR', 'offset': 184, 'size': 8, 'desc': 'Invalidation Event Upper Address', 'FIELDS': {'S': {'name': 'S', 'bit': 0, 'size': 4, 'desc': 'Size'}, 'EIME': {'name': 'EIME', 'bit': 11, 'size': 1, 'desc': 'Extended Interrupt Mode Enable'}, 'IRTA': {'name': 'IRTA', 'bit': 12, 'size': 52, 'desc': 'Interrupt Remapping Table Address'}}}

[*] [DEBUG] + GFXVTBAR_VER : {'name': 'GFXVTBAR_VER', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 0, 'size': 4, 'desc': 'Version', 'FIELDS': {'MIN': {'name': 'MIN', 'bit': 0, 'size': 4, 'desc': 'Minor Version Number'}, 'MAX': {'name': 'MAX', 'bit': 4, 'size': 4, 'desc': 'Major Version Number'}}}

[*] [DEBUG] + GFXVTBAR_CAP : {'name': 'GFXVTBAR_CAP', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 8, 'size': 8, 'desc': 'Capability', 'FIELDS': {'ND': {'name': 'ND', 'bit': 0, 'size': 2, 'desc': 'Number of Domains Supported'}, 'Rsvd': {'name': 'Rsvd', 'bit': 3, 'size': 1, 'desc': 'Reserved'}, 'RWBF': {'name': 'RWBF', 'bit': 4, 'size': 1, 'desc': 'Required Write-Buffer Flushing'}, 'PLMR': {'name': 'PLMR', 'bit': 5, 'size': 1, 'desc': 'Protected Low-Memory Region'}, 'PHMR': {'name': 'PHMR', 'bit': 6, 'size': 1, 'desc': 'Protected High-Memory Region'}, 'CM': {'name': 'CM', 'bit': 7, 'size': 1, 'desc': 'Caching Mode'}, 'SAGAW': {'name': 'SAGAW', 'bit': 8, 'size': 5, 'desc': 'Supported Adjusted Guest Address Width'}, 'R0': {'name': 'R0', 'bit': 13, 'size': 3, 'desc': 'Reserved'}, 'MGAW': {'name': 'MGAW', 'bit': 16, 'size': 6, 'desc': 'Maximum Guest Address Width'}, 'ZLR': {'name': 'ZLR', 'bit': 22, 'size': 1, 'desc': 'Zero Length Read'}, 'R1': {'name': 'R1', 'bit': 23, 'size': 1, 'desc': 'Reserved'}, 'FRO': {'name': 'FRO', 'bit': 24, 'size': 10, 'desc': 'Fault-Recording Registrer Offset'}, 'SLLPS': {'name': 'SLLPS', 'bit': 34, 'size': 4, 'desc': 'Second Level Large Page Support'}, 'R2': {'name': 'R2', 'bit': 38, 'size': 1, 'desc': 'Reserved'}, 'PSI': {'name': 'PSI', 'bit': 39, 'size': 1, 'desc': 'Page Selective Invalidation'}, 'NFR': {'name': 'NFR', 'bit': 40, 'size': 8, 'desc': 'Number of Fault-Recording Registers'}, 'MAMV': {'name': 'MAMV', 'bit': 48, 'size': 6, 'desc': 'Maximum Address Mask Value'}, 'DWD': {'name': 'DWD', 'bit': 54, 'size': 1, 'desc': 'Write Draining'}, 'DRD': {'name': 'DRD', 'bit': 55, 'size': 1, 'desc': 'Read Draining'}, 'FL1GP': {'name': 'FL1GP', 'bit': 56, 'size': 1, 'desc': 'First Level 1-GB Page Support'}, 'R3': {'name': 'R3', 'bit': 57, 'size': 2, 'desc': 'Reserved'}, 'PI': {'name': 'PI', 'bit': 59, 'size': 1, 'desc': 'Posted Interrupts Support'}, 'R4': {'name': 'R4', 'bit': 60, 'size': 4, 'desc': 'Reserved'}}}

[*] [DEBUG] + GFXVTBAR_ECAP : {'name': 'GFXVTBAR_ECAP', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 16, 'size': 8, 'desc': 'Global Command', 'FIELDS': {'C': {'name': 'C', 'bit': 0, 'size': 1, 'desc': 'Page-walk Coherency'}, 'QI': {'name': 'QI', 'bit': 1, 'size': 1, 'desc': 'Queued Invalidation Support'}, 'DT': {'name': 'DT', 'bit': 2, 'size': 1, 'desc': 'Device-TLB Support'}, 'IR': {'name': 'IR', 'bit': 3, 'size': 1, 'desc': 'Interrupt Remapping Support'}, 'EIM': {'name': 'EIM', 'bit': 4, 'size': 1, 'desc': 'Extended Interrupt Mode'}, 'R0': {'name': 'R0', 'bit': 5, 'size': 1, 'desc': 'Reserved'}, 'PT': {'name': 'PT', 'bit': 6, 'size': 1, 'desc': 'Pass Through'}, 'SC': {'name': 'SC', 'bit': 7, 'size': 1, 'desc': 'Snoop Control'}, 'IRO': {'name': 'IRO', 'bit': 8, 'size': 10, 'desc': 'IOTLB Register Offset'}, 'R1': {'name': 'R1', 'bit': 18, 'size': 2, 'desc': 'Reserved'}, 'MHMV': {'name': 'MHMV', 'bit': 20, 'size': 4, 'desc': 'Maximum Handle Mask Value'}, 'ECS': {'name': 'ECS', 'bit': 24, 'size': 1, 'desc': 'Extended Context Support'}, 'MTS': {'name': 'MTS', 'bit': 25, 'size': 1, 'desc': 'Memory Type Support'}, 'NEST': {'name': 'NEST', 'bit': 26, 'size': 1, 'desc': 'Nested Translation Support'}, 'DIS': {'name': 'DIS', 'bit': 27, 'size': 1, 'desc': 'Deferred Invalidate Support'}, 'PASID': {'name': 'PASID', 'bit': 28, 'size': 1, 'desc': 'Process Address Space ID Support'}, 'PRS': {'name': 'PRS', 'bit': 29, 'size': 1, 'desc': 'Page Request Support'}, 'ERS': {'name': 'ERS', 'bit': 30, 'size': 1, 'desc': 'Execute Request Support'}, 'SRS': {'name': 'SRS', 'bit': 31, 'size': 1, 'desc': 'Supervisor Request Support'}, 'R2': {'name': 'R2', 'bit': 32, 'size': 1, 'desc': 'Reserved'}, 'NWFS': {'name': 'NWFS', 'bit': 33, 'size': 1, 'desc': 'No Write Flag Support'}, 'EAFS': {'name': 'EAFS', 'bit': 34, 'size': 1, 'desc': 'Extended Accessed Flag Support'}, 'PSS': {'name': 'PSS', 'bit': 35, 'size': 5, 'desc': 'PASID Size Supported'}, 'R3': {'name': 'R3', 'bit': 40, 'size': 24, 'desc': 'Reserved'}}}

[*] [DEBUG] + GFXVTBAR_GCMD : {'name': 'GFXVTBAR_GCMD', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 24, 'size': 4, 'desc': 'Global Command', 'FIELDS': {'Rsvd': {'name': 'Rsvd', 'bit': 28, 'size': 1, 'desc': 'Reserved'}, 'CFI': {'name': 'CFI', 'bit': 23, 'size': 1, 'desc': 'Compatibility Format Interrupt'}, 'SIRTP': {'name': 'SIRTP', 'bit': 24, 'size': 1, 'desc': 'Set Interrupt Remap Table Pointer'}, 'IRE': {'name': 'IRE', 'bit': 25, 'size': 1, 'desc': 'Interrupt Remapping Enable'}, 'QIE': {'name': 'QIE', 'bit': 26, 'size': 1, 'desc': 'Queued Invalidation Enable'}, 'WBF': {'name': 'WBF', 'bit': 27, 'size': 1, 'desc': 'Write Buffer Flush'}, 'SFL': {'name': 'SFL', 'bit': 29, 'size': 1, 'desc': 'Set Fault Log'}, 'SRTP': {'name': 'SRTP', 'bit': 30, 'size': 1, 'desc': 'Set Root Table Pointer'}, 'TE': {'name': 'TE', 'bit': 31, 'size': 1, 'desc': 'Translation Enable'}}}

[*] [DEBUG] + GFXVTBAR_GSTS : {'name': 'GFXVTBAR_GSTS', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 28, 'size': 4, 'desc': 'Global Status', 'FIELDS': {'Rsvd': {'name': 'Rsvd', 'bit': 28, 'size': 1, 'desc': 'Reserved'}, 'CFIS': {'name': 'CFIS', 'bit': 23, 'size': 1, 'desc': 'Compatibility Format Interrupt Status'}, 'IRTPS': {'name': 'IRTPS', 'bit': 24, 'size': 1, 'desc': 'Interrupt Remap Table Pointer Status'}, 'IRES': {'name': 'IRES', 'bit': 25, 'size': 1, 'desc': 'Interrupt Remapping Enable Status'}, 'QIES': {'name': 'QIES', 'bit': 26, 'size': 1, 'desc': 'Queued Invalidation Enable Status'}, 'WBFS': {'name': 'WBFS', 'bit': 27, 'size': 1, 'desc': 'Write Buffer Flush Status'}, 'FLS': {'name': 'FLS', 'bit': 29, 'size': 1, 'desc': 'Fault Log Status'}, 'RTPS': {'name': 'RTPS', 'bit': 30, 'size': 1, 'desc': 'Root Table Pointer Status'}, 'TES': {'name': 'TES', 'bit': 31, 'size': 1, 'desc': 'Translation Enable Status'}}}

[*] [DEBUG] + GFXVTBAR_RTADDR : {'name': 'GFXVTBAR_RTADDR', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 32, 'size': 8, 'desc': 'Root-Entry Table Address', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 11, 'desc': 'Reserved'}, 'RTT': {'name': 'RTT', 'bit': 11, 'size': 1, 'desc': 'Root Table Type'}, 'RTA': {'name': 'RTA', 'bit': 12, 'size': 52, 'desc': 'Root Table Address'}}}

[*] [DEBUG] + GFXVTBAR_CCMD : {'name': 'GFXVTBAR_CCMD', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 40, 'size': 8, 'desc': 'Context Command', 'FIELDS': {'DID': {'name': 'DID', 'bit': 0, 'size': 16, 'desc': 'Device ID'}, 'SID': {'name': 'SID', 'bit': 16, 'size': 16, 'desc': 'Source ID'}, 'FM': {'name': 'FM', 'bit': 32, 'size': 2, 'desc': 'Function Mask'}, 'R': {'name': 'R', 'bit': 34, 'size': 25, 'desc': 'Reserved'}, 'CAIG': {'name': 'CAIG', 'bit': 59, 'size': 2, 'desc': 'Context Actual Invalidation Granularity'}, 'CIRG': {'name': 'CIRG', 'bit': 61, 'size': 2, 'desc': 'Context Invalidation Request Granularity'}, 'ICC': {'name': 'ICC', 'bit': 63, 'size': 1, 'desc': 'Invalidate Context-Cache'}}}

[*] [DEBUG] + GFXVTBAR_IVA : {'name': 'GFXVTBAR_IVA', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 0, 'size': 8, 'desc': 'Invalidate Address', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_IOTLB : {'name': 'GFXVTBAR_IOTLB', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 8, 'size': 8, 'desc': 'IOTLB Invalidate', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_FSTS : {'name': 'GFXVTBAR_FSTS', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 52, 'size': 4, 'desc': 'Fault Status', 'FIELDS': {'PFO': {'name': 'PFO', 'bit': 0, 'size': 1, 'desc': 'Primary Fault Overflow'}, 'PPF': {'name': 'PPF', 'bit': 1, 'size': 1, 'desc': 'Primary Pending Fault'}, 'AFO': {'name': 'AFO', 'bit': 2, 'size': 1, 'desc': 'Advanced Fault Overflow'}, 'APF': {'name': 'APF', 'bit': 3, 'size': 1, 'desc': 'Advanced Pending Fault'}, 'IQE': {'name': 'IQE', 'bit': 4, 'size': 1, 'desc': 'Invalidation Queue Error'}, 'ICE': {'name': 'ICE', 'bit': 5, 'size': 1, 'desc': 'Invalidation Completion Error'}, 'ITE': {'name': 'ITE', 'bit': 6, 'size': 1, 'desc': 'Invalidation Time-out Error'}, 'PRO': {'name': 'PRO', 'bit': 7, 'size': 1, 'desc': 'Page Request Overflow'}, 'FRI': {'name': 'FRI', 'bit': 8, 'size': 7, 'desc': 'Fault Record Index'}}}

[*] [DEBUG] + GFXVTBAR_FECTL : {'name': 'GFXVTBAR_FECTL', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 56, 'size': 4, 'desc': 'Fault Event Control', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 30, 'desc': 'Reserved'}, 'IP': {'name': 'IP', 'bit': 30, 'size': 1, 'desc': 'Interrupt Pending'}, 'IM': {'name': 'IM', 'bit': 31, 'size': 1, 'desc': 'Interrupt Mask'}}}

[*] [DEBUG] + GFXVTBAR_FEDATA : {'name': 'GFXVTBAR_FEDATA', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 60, 'size': 4, 'desc': 'Fault Event Data', 'FIELDS': {'IMD': {'name': 'IMD', 'bit': 0, 'size': 16, 'desc': 'Interrupt Message Data'}, 'EIMD': {'name': 'EIMD', 'bit': 16, 'size': 16, 'desc': 'Extended Interrupt Message Data'}}}

[*] [DEBUG] + GFXVTBAR_FEADDR : {'name': 'GFXVTBAR_FEADDR', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 64, 'size': 4, 'desc': 'Fault Event Address', 'FIELDS': {'R': {'name': 'R', 'bit': 0, 'size': 2, 'desc': 'Reserved'}, 'MA': {'name': 'MA', 'bit': 2, 'size': 30, 'desc': 'Message Address'}}}

[*] [DEBUG] + GFXVTBAR_FEUADDR: {'name': 'GFXVTBAR_FEUADDR', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 68, 'size': 4, 'desc': 'Fault Event Upper Address', 'FIELDS': {'MUA': {'name': 'MUA', 'bit': 0, 'size': 32, 'desc': 'Message Upper Address'}}}

[*] [DEBUG] + GFXVTBAR_FRCDL : {'name': 'GFXVTBAR_FRCDL', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 0, 'size': 8, 'desc': 'Fault Recording (Low)', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_FRCDH : {'name': 'GFXVTBAR_FRCDH', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 8, 'size': 8, 'desc': 'Fault Recording (High)', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_PMEN : {'name': 'GFXVTBAR_PMEN', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 100, 'size': 4, 'desc': 'Protected Memory Enable', 'FIELDS': {'PRS': {'name': 'PRS', 'bit': 0, 'size': 1, 'desc': 'Protected Region Status'}, 'EPM': {'name': 'EPM', 'bit': 31, 'size': 1, 'desc': 'Enable Protected Memory'}}}

[*] [DEBUG] + GFXVTBAR_PLMBASE: {'name': 'GFXVTBAR_PLMBASE', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 104, 'size': 4, 'desc': 'Protected Memory Low Base', 'FIELDS': {'PLMB': {'name': 'PLMB', 'bit': 12, 'size': 20, 'desc': 'Protected Low-Memory Base'}}}

[*] [DEBUG] + GFXVTBAR_PLMLIMIT: {'name': 'GFXVTBAR_PLMLIMIT', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 108, 'size': 4, 'desc': 'Protected Memory Low Limit', 'FIELDS': {'PLML': {'name': 'PLML', 'bit': 12, 'size': 20, 'desc': 'Protected Low-Memory Limit'}}}

[*] [DEBUG] + GFXVTBAR_PHMBASE: {'name': 'GFXVTBAR_PHMBASE', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 112, 'size': 8, 'desc': 'Protected Memory High Base', 'FIELDS': {'PHMB': {'name': 'PHMB', 'bit': 12, 'size': 52, 'desc': 'Protected High-Memory Base'}}}

[*] [DEBUG] + GFXVTBAR_PHMLIMIT: {'name': 'GFXVTBAR_PHMLIMIT', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 120, 'size': 8, 'desc': 'Protected Memory High Limit', 'FIELDS': {'PHML': {'name': 'PHML', 'bit': 12, 'size': 52, 'desc': 'Protected High-Memory Limit'}}}

[*] [DEBUG] + GFXVTBAR_IQH : {'name': 'GFXVTBAR_IQH', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 128, 'size': 8, 'desc': 'Invalidation Queue Head', 'FIELDS': {'QH': {'name': 'QH', 'bit': 4, 'size': 15, 'desc': 'Queue Head'}}}

[*] [DEBUG] + GFXVTBAR_IQT : {'name': 'GFXVTBAR_IQT', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 136, 'size': 8, 'desc': 'Invalidation Queue Tail', 'FIELDS': {'QT': {'name': 'QT', 'bit': 4, 'size': 15, 'desc': 'Queue Tail'}}}

[*] [DEBUG] + GFXVTBAR_IQA : {'name': 'GFXVTBAR_IQA', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 144, 'size': 8, 'desc': 'Invalidation Queue Address', 'FIELDS': {'QS': {'name': 'QS', 'bit': 0, 'size': 3, 'desc': 'Queue Size'}, 'IQA': {'name': 'IQA', 'bit': 12, 'size': 52, 'desc': 'Invalidation Queue Base Address'}}}

[*] [DEBUG] + GFXVTBAR_ICS : {'name': 'GFXVTBAR_ICS', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 156, 'size': 4, 'desc': 'Invalidation Completion Status', 'FIELDS': {'IWC': {'name': 'IWC', 'bit': 0, 'size': 1, 'desc': 'Invalidation Wait Descriptor Complete'}}}

[*] [DEBUG] + GFXVTBAR_IECTL : {'name': 'GFXVTBAR_IECTL', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 160, 'size': 4, 'desc': 'Invalidation Event Control', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_IEDATA : {'name': 'GFXVTBAR_IEDATA', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 164, 'size': 4, 'desc': 'Invalidation Event Data', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_IEADDR : {'name': 'GFXVTBAR_IEADDR', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 168, 'size': 4, 'desc': 'Invalidation Event Address', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_IEUADDR: {'name': 'GFXVTBAR_IEUADDR', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 172, 'size': 4, 'desc': 'Invalidation Event Address', 'FIELDS': {}}

[*] [DEBUG] + GFXVTBAR_IRTA : {'name': 'GFXVTBAR_IRTA', 'type': 'mmio', 'bar': 'GFXVTBAR', 'offset': 184, 'size': 8, 'desc': 'Invalidation Event Upper Address', 'FIELDS': {'S': {'name': 'S', 'bit': 0, 'size': 4, 'desc': 'Size'}, 'EIME': {'name': 'EIME', 'bit': 11, 'size': 1, 'desc': 'Extended Interrupt Mode Enable'}, 'IRTA': {'name': 'IRTA', 'bit': 12, 'size': 52, 'desc': 'Interrupt Remapping Table Address'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/sfdp.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + DWORD1 : {'name': 'DWORD1', 'offset': 0, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 1st DWORD ', 'FIELDS': {'BLK_ERASE_SUPPORT': {'name': 'BLK_ERASE_SUPPORT', 'bit': 0, 'size': 2, 'desc': 'Block Sector Erase Sizes'}, 'WR_GRANULTY': {'name': 'WR_GRANULTY', 'bit': 2, 'size': 1, 'desc': 'Write Granularity'}, 'BLK_PRT_VOL_STATUS': {'name': 'BLK_PRT_VOL_STATUS', 'bit': 3, 'size': 1, 'desc': 'Write Enable Instruction Required for Writing to Volatile Status Register'}, 'WREnable_INST_Select': {'name': 'WREnable_INST_Select', 'bit': 4, 'size': 1, 'desc': 'Write Enable Opcode Select for Writing to Volatile Status Register'}, 'Unused': {'name': 'Unused', 'bit': 5, 'size': 3, 'desc': 'Unused register'}, '4K_Erase_INST': {'name': '4K_Erase_INST', 'bit': 8, 'size': 8, 'desc': '4K Erase Opcode'}, 'FASTREAD_112_SUPPORT': {'name': 'FASTREAD_112_SUPPORT', 'bit': 16, 'size': 1, 'desc': 'Supports (1-1-2) fast read'}, 'ADDR_BYTES': {'name': 'ADDR_BYTES', 'bit': 17, 'size': 2, 'desc': 'Number of bytes used in addressing flash array read, write and erase'}, 'DTR_CLK_SUPPORT': {'name': 'DTR_CLK_SUPPORT', 'bit': 19, 'size': 1, 'desc': 'DTR Clocking Support'}, 'FASTREAD_122_SUPPORT': {'name': 'FASTREAD_122_SUPPORT', 'bit': 20, 'size': 1, 'desc': 'Supports ( 1-2-2) fast read'}, 'FASTREAD_144_SUPPORT': {'name': 'FASTREAD_144_SUPPORT', 'bit': 21, 'size': 1, 'desc': 'Supports ( 1-4-4) fast read'}, 'FASTREAD_114_SUPPORT': {'name': 'FASTREAD_114_SUPPORT', 'bit': 22, 'size': 1, 'desc': 'Supports ( 1-4-4) fast read'}, 'UNUSED': {'name': 'UNUSED', 'bit': 23, 'size': 9, 'desc': 'Unused'}}}

[*] [DEBUG] + DWORD2 : {'name': 'DWORD2', 'offset': 4, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 2nd DWORD ', 'FIELDS': {'FLASH_MEM_DENSITY': {'name': 'FLASH_MEM_DENSITY', 'bit': 0, 'size': 32, 'desc': 'Flash Memory Density'}}}

[*] [DEBUG] + DWORD3 : {'name': 'DWORD3', 'offset': 8, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 3rd DWORD ', 'FIELDS': {'144_FR_NUM_WAIT_STATES': {'name': '144_FR_NUM_WAIT_STATES', 'bit': 0, 'size': 5, 'desc': '(1-4-4) fast read number of wait states (dummy clocks) needed before valid output'}, '144_FR_QUAD_NUM_MODE_CLKS': {'name': '144_FR_QUAD_NUM_MODE_CLKS', 'bit': 5, 'size': 3, 'desc': 'Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode Bits'}, '144_FR_INST': {'name': '144_FR_INST', 'bit': 8, 'size': 8, 'desc': '(1-4-4) fast read Opcode'}, '114_FR_NUM_WAIT_STATES': {'name': '114_FR_NUM_WAIT_STATES', 'bit': 16, 'size': 5, 'desc': '(1-1-4) fast read number of wait states (dummy clocks)'}, '114_FR_NUM_MODE_CLKS': {'name': '114_FR_NUM_MODE_CLKS', 'bit': 21, 'size': 3, 'desc': '(1-1-4) fast read number of Mode Bits'}, '114_FR_INST': {'name': '114_FR_INST', 'bit': 24, 'size': 8, 'desc': '(1-1-4) fast read Opcode'}}}

[*] [DEBUG] + DWORD4 : {'name': 'DWORD4', 'offset': 12, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 4th DWORD ', 'FIELDS': {'112_FR_NUM_WAIT_STATES': {'name': '112_FR_NUM_WAIT_STATES', 'bit': 16, 'size': 5, 'desc': '(1-2-2) fast read Number of Wait states (dummy clocks)'}, '112_FR_NUM_MODE_CLKS': {'name': '112_FR_NUM_MODE_CLKS', 'bit': 5, 'size': 3, 'desc': '(1-1-2) fast read Number of Mode Bits'}, '112_FR_INST': {'name': '112_FR_INST', 'bit': 8, 'size': 8, 'desc': '(1-1-2) fast read Opcode'}, '122_FR_NUM_MODE_CLKS': {'name': '122_FR_NUM_MODE_CLKS', 'bit': 21, 'size': 3, 'desc': '(1-2-2) fast read Number of Mode Bits'}, '122_FR_INST': {'name': '122_FR_INST', 'bit': 24, 'size': 8, 'desc': '(1-2-2) fast read Opcode'}}}

[*] [DEBUG] + DWORD5 : {'name': 'DWORD5', 'offset': 16, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 5th DWORD ', 'FIELDS': {'222_FR_SUPPORT': {'name': '222_FR_SUPPORT', 'bit': 0, 'size': 1, 'desc': 'Supports (2-2-2) fast read'}, 'Reserved': {'name': 'Reserved', 'bit': 1, 'size': 3, 'desc': 'Reserved'}, '444_FR_SUPPORT': {'name': '444_FR_SUPPORT', 'bit': 4, 'size': 1, 'desc': 'Supports ( 4-4-4) fast read'}, 'RESERVED': {'name': 'RESERVED', 'bit': 5, 'size': 27, 'desc': 'Reserved'}}}

[*] [DEBUG] + DWORD6 : {'name': 'DWORD6', 'offset': 20, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 6th DWORD ', 'FIELDS': {'RESERVED': {'name': 'RESERVED', 'bit': 0, 'size': 16, 'desc': 'Reserved'}, '222_FR_NUM_WAIT_STATES': {'name': '222_FR_NUM_WAIT_STATES', 'bit': 16, 'size': 5, 'desc': '(2-2-2) fast read Number of Wait states (dummy clocks) needed before valid output'}, '222_FR_NUM_MOD_CLKS': {'name': '222_FR_NUM_MOD_CLKS', 'bit': 21, 'size': 3, 'desc': '(2-2-2) fast read Number of Mode Bits'}, '222_FR_INST': {'name': '222_FR_INST', 'bit': 24, 'size': 8, 'desc': '(2-2-2) fast read Opcode'}}}

[*] [DEBUG] + DWORD7 : {'name': 'DWORD7', 'offset': 24, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 7th DWORD ', 'FIELDS': {'RESERVED': {'name': 'RESERVED', 'bit': 0, 'size': 16, 'desc': 'Reserved'}, '444_FR_NUM_WAIT_STATES': {'name': '444_FR_NUM_WAIT_STATES', 'bit': 16, 'size': 5, 'desc': '(4-4-4) fast read number of wait states (dummy clocks) needed before valid output'}, '444_FR_NUM_MOD_CLKS': {'name': '444_FR_NUM_MOD_CLKS', 'bit': 21, 'size': 3, 'desc': '(4-4-4) fast read number of mode bits'}, '444_FR_INST': {'name': '444_FR_INST', 'bit': 24, 'size': 8, 'desc': '(4-4-4) fast read Opcode'}}}

[*] [DEBUG] + DWORD8 : {'name': 'DWORD8', 'offset': 28, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 8th DWORD ', 'FIELDS': {'ERASE_TYPE1_SIZE': {'name': 'ERASE_TYPE1_SIZE', 'bit': 0, 'size': 8, 'desc': 'Sector Type 1 size'}, 'ERASE_TYPE1_INST': {'name': 'ERASE_TYPE1_INST', 'bit': 24, 'size': 8, 'desc': 'Sector Type 2 Opcode'}, 'ERASE_TYPE2_SIZE': {'name': 'ERASE_TYPE2_SIZE', 'bit': 16, 'size': 8, 'desc': 'Sector Type 2 size'}}}

[*] [DEBUG] + DWORD9 : {'name': 'DWORD9', 'offset': 32, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 9th DWORD ', 'FIELDS': {'ERASE_TYPE3_SIZE': {'name': 'ERASE_TYPE3_SIZE', 'bit': 0, 'size': 8, 'desc': 'Sector Type 3 size'}, 'ERASE_TYPE3_OPCODE': {'name': 'ERASE_TYPE3_OPCODE', 'bit': 8, 'size': 8, 'desc': 'Sector Type 3 Opcode'}, 'ERASE_TYPE4_SIZE': {'name': 'ERASE_TYPE4_SIZE', 'bit': 16, 'size': 8, 'desc': 'Sector Type 4 size'}, 'ERASE_TYPE4_OPCODE': {'name': 'ERASE_TYPE4_OPCODE', 'bit': 24, 'size': 8, 'desc': 'Sector Type 4 Opcode'}}}

[*] [DEBUG] + DWORD10 : {'name': 'DWORD10', 'offset': 36, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 10th DWORD ', 'FIELDS': {'MULTIPLIER': {'name': 'MULTIPLIER', 'bit': 0, 'size': 4, 'desc': 'Multiplier from typical erase time to maximum erase time'}, 'ERASE_TYPE1_TIME': {'name': 'ERASE_TYPE1_TIME', 'bit': 4, 'size': 7, 'desc': 'Erase Type 1 Erase, Typical time'}, 'ERASE_TYPE2_TIME': {'name': 'ERASE_TYPE2_TIME', 'bit': 11, 'size': 7, 'desc': 'Erase Type 2 Erase, Typical time'}, 'ERASE_TYPE3_TIME': {'name': 'ERASE_TYPE3_TIME', 'bit': 18, 'size': 7, 'desc': 'Erase Type 3 Erase, Typical time'}, 'ERASE_TYPE4_TIME': {'name': 'ERASE_TYPE4_TIME', 'bit': 25, 'size': 7, 'desc': 'Erase Type 4 Erase, Typical time'}}}

[*] [DEBUG] + DWORD11 : {'name': 'DWORD11', 'offset': 40, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 11th DWORD ', 'FIELDS': {'MULTIPLIER': {'name': 'MULTIPLIER', 'bit': 0, 'size': 4, 'desc': 'Multiplier from typical to maximum erase time for page or Byte program'}, 'PAGE_SIZE': {'name': 'PAGE_SIZE', 'bit': 4, 'size': 4, 'desc': 'Page Size'}, 'PAGE_PRG_TYPICAL_TIME': {'name': 'PAGE_PRG_TYPICAL_TIME', 'bit': 8, 'size': 6, 'desc': 'Page Program Typical time'}, 'BYTE_PRG_TYPICAL_TIME_FIRST': {'name': 'BYTE_PRG_TYPICAL_TIME_FIRST', 'bit': 14, 'size': 5, 'desc': 'Byte Program Typical time'}, 'BYTE_PRG_TYPICAL_TIME_ADTNL': {'name': 'BYTE_PRG_TYPICAL_TIME_ADTNL', 'bit': 19, 'size': 5, 'desc': 'Byte Program Typical time, additional byte'}, 'CHIP_ERASE': {'name': 'CHIP_ERASE', 'bit': 24, 'size': 7, 'desc': 'Chip Erase, Typical time'}, 'Reserved': {'name': 'Reserved', 'bit': 31, 'size': 1, 'desc': 'Reserved'}}}

[*] [DEBUG] + DWORD12 : {'name': 'DWORD12', 'offset': 44, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 12th DWORD ', 'FIELDS': {'PO_PRG_SUSPEND': {'name': 'PO_PRG_SUSPEND', 'bit': 0, 'size': 4, 'desc': 'Prohibited Operations During Program Suspend'}, 'PO_ERASE_SUSPEND': {'name': 'PO_ERASE_SUSPEND', 'bit': 4, 'size': 4, 'desc': 'Prohibited Operations During Erase Suspend'}, 'Reserved': {'name': 'Reserved', 'bit': 8, 'size': 1, 'desc': 'Reserved'}, 'PRG_RESUME2SUSPD_INTERVAL': {'name': 'PRG_RESUME2SUSPD_INTERVAL', 'bit': 9, 'size': 4, 'desc': 'Program Resume to Suspend Interval'}, 'SUSPD_INPRG_MAXLATENCY': {'name': 'SUSPD_INPRG_MAXLATENCY', 'bit': 13, 'size': 7, 'desc': 'Suspend in-progress program max latency'}, 'ERASE_RESUME2SUSPD_INTERVAL': {'name': 'ERASE_RESUME2SUSPD_INTERVAL', 'bit': 20, 'size': 4, 'desc': 'Erase Resume to suspend latency'}, 'SUSPD_INPRG_ERASE_MAXLATENCY': {'name': 'SUSPD_INPRG_ERASE_MAXLATENCY', 'bit': 24, 'size': 7, 'desc': 'Suspend in-progress erase max latency'}, 'SUSPEND_RESUME_SUPPORT': {'name': 'SUSPEND_RESUME_SUPPORT', 'bit': 31, 'size': 1, 'desc': 'Suspend/Resume Supported'}}}

[*] [DEBUG] + DWORD13 : {'name': 'DWORD13', 'offset': 48, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 13th DWORD ', 'FIELDS': {'PRG_RESUME_INST': {'name': 'PRG_RESUME_INST', 'bit': 0, 'size': 8, 'desc': 'Program Resume Instruction'}, 'PRG_SUSP_INST': {'name': 'PRG_SUSP_INST', 'bit': 8, 'size': 8, 'desc': 'Program Suspend Instruction'}, 'RESUME_INST': {'name': 'RESUME_INST', 'bit': 16, 'size': 8, 'desc': 'Resume Instruction'}, 'SUSP_INST': {'name': 'SUSP_INST', 'bit': 24, 'size': 8, 'desc': 'Suspend Instruction'}}}

[*] [DEBUG] + DWORD14 : {'name': 'DWORD14', 'offset': 52, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 14th DWORD ', 'FIELDS': {'RESERVED': {'name': 'RESERVED', 'bit': 0, 'size': 2, 'desc': 'Reserved'}, 'STS_POLLING_BUSY': {'name': 'STS_POLLING_BUSY', 'bit': 2, 'size': 6, 'desc': 'Status Register Polling Device Busy'}, 'EXIT_DPWDOWN_DELAY': {'name': 'EXIT_DPWDOWN_DELAY', 'bit': 8, 'size': 7, 'desc': 'Exit Deep Powerdown to next operation delay'}, 'EXIT_DPWDOWN_INST': {'name': 'EXIT_DPWDOWN_INST', 'bit': 15, 'size': 8, 'desc': 'Exit Deep Powerdown Instruction'}, 'ENTER_DPWDOWN_INST': {'name': 'ENTER_DPWDOWN_INST', 'bit': 23, 'size': 8, 'desc': 'Enter Deep Powerdown Instruction'}, 'DPWDOWN_SUPPORT': {'name': 'DPWDOWN_SUPPORT', 'bit': 31, 'size': 1, 'desc': 'Deep Powerdown Supported'}}}

[*] [DEBUG] + DWORD15 : {'name': 'DWORD15', 'offset': 56, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 15th DWORD ', 'FIELDS': {'444_DISABLE_SEQ': {'name': '444_DISABLE_SEQ', 'bit': 0, 'size': 4, 'desc': '4-4-4 mode disable sequences'}, '444_ENABLE_SEQ': {'name': '444_ENABLE_SEQ', 'bit': 4, 'size': 5, 'desc': '4-4-4 mode enable sequences'}, '044_MODE_SUPPORTED': {'name': '044_MODE_SUPPORTED', 'bit': 9, 'size': 1, 'desc': '0-4-4 mode supported'}, '044_EXIT_METHOD': {'name': '044_EXIT_METHOD', 'bit': 10, 'size': 6, 'desc': '0-4-4 Mode Exit Method'}, '044_ENTRY_METHOD': {'name': '044_ENTRY_METHOD', 'bit': 16, 'size': 4, 'desc': '0-4-4 Mode Entry Method'}, 'QUAD_ENABLE_REQ': {'name': 'QUAD_ENABLE_REQ', 'bit': 20, 'size': 3, 'desc': 'Quad Enable Requirements'}, 'HOLD_RESET_DISABLE': {'name': 'HOLD_RESET_DISABLE', 'bit': 23, 'size': 1, 'desc': 'Hold or Reset disable'}, 'RESERVED': {'name': 'RESERVED', 'bit': 24, 'size': 8, 'desc': 'Reserved'}}}

[*] [DEBUG] + DWORD16 : {'name': 'DWORD16', 'offset': 60, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 16th DWORD ', 'FIELDS': {'VLT_WRENABLE_INST': {'name': 'VLT_WRENABLE_INST', 'bit': 0, 'size': 7, 'desc': 'Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1'}, 'RESERVED': {'name': 'RESERVED', 'bit': 7, 'size': 1, 'desc': 'Reserved'}, 'SRESET_RESC_SUPPORT': {'name': 'SRESET_RESC_SUPPORT', 'bit': 8, 'size': 6, 'desc': 'Soft Reset and Rescue Sequence Support'}, 'EXIT_4BYTE_ADDR': {'name': 'EXIT_4BYTE_ADDR', 'bit': 14, 'size': 10, 'desc': 'Exit 4 Byte Addressing'}, 'ENTER_4BYTE_ADDR': {'name': 'ENTER_4BYTE_ADDR', 'bit': 24, 'size': 8, 'desc': 'Enter 4 Byte Addressing'}}}

[*] [DEBUG] + DWORD17 : {'name': 'DWORD17', 'offset': 64, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 17th DWORD ', 'FIELDS': {'188_FR_NUM_WAIT_STATES': {'name': '188_FR_NUM_WAIT_STATES', 'bit': 0, 'size': 5, 'desc': '(1-8-8) Fast Read Number of Wait states (dummy clocks) needed before valid output'}, '188_FR_NUM_MOD_CLKS': {'name': '188_FR_NUM_MOD_CLKS', 'bit': 5, 'size': 3, 'desc': '(1-8-8) Fast Read Number of Mode Clocks'}, '188_FR_INST': {'name': '188_FR_INST', 'bit': 8, 'size': 8, 'desc': '(1-8-8) Fast Read Instruction'}, '118_FR_NUM_WAIT_STATES': {'name': '118_FR_NUM_WAIT_STATES', 'bit': 16, 'size': 5, 'desc': '(1-1-8) Fast Read Number of Wait states (dummy clocks) needed before valid output'}, '118_FR_NUM_MOD_CLKS': {'name': '118_FR_NUM_MOD_CLKS', 'bit': 21, 'size': 3, 'desc': '(1-1-8) Fast Read Number of Mode Clocks'}, '118_FR_INST': {'name': '118_FR_INST', 'bit': 24, 'size': 8, 'desc': '(1-8-8) Fast Read Instruction'}}}

[*] [DEBUG] + DWORD18 : {'name': 'DWORD18', 'offset': 68, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 18th DWORD ', 'FIELDS': {'Reserved': {'name': 'Reserved', 'bit': 28, 'size': 1, 'desc': 'Reserved'}, 'VAR_OUT_DRV_STRENGTH': {'name': 'VAR_OUT_DRV_STRENGTH', 'bit': 18, 'size': 5, 'desc': 'Variable Output Driver Strength'}, 'JEDEC_SPI_RESET': {'name': 'JEDEC_SPI_RESET', 'bit': 23, 'size': 1, 'desc': 'JEDEC SPI Protocol Reset (In-Band Reset)'}, 'DATA_STRB_WAVEFORMS_STR_MODE': {'name': 'DATA_STRB_WAVEFORMS_STR_MODE', 'bit': 24, 'size': 2, 'desc': 'Data Strobe Waveforms in STR Mode'}, '4S4S4S_DATA_STRB_QPI_STR_MODE': {'name': '4S4S4S_DATA_STRB_QPI_STR_MODE', 'bit': 26, 'size': 1, 'desc': 'Data Strobe support for QPI STR mode (4S-4S-4S)'}, '4S4D4D_DATA_STRB_QPI_DTR_MODE': {'name': '4S4D4D_DATA_STRB_QPI_DTR_MODE', 'bit': 27, 'size': 1, 'desc': 'Data Strobe support for QPI DTR mode (4S-4D-4D)'}, '8D8D8D_OCTAL_DTR_CMD_EXT': {'name': '8D8D8D_OCTAL_DTR_CMD_EXT', 'bit': 29, 'size': 2, 'desc': 'Octal DTR (8D-8D-8D) Command and Command Extension'}, '8D8D8D_BYTE_ORDER_MODE': {'name': '8D8D8D_BYTE_ORDER_MODE', 'bit': 31, 'size': 1, 'desc': 'Octal DTR (8D-8D-8D) Command and Command Extension'}}}

[*] [DEBUG] + DWORD19 : {'name': 'DWORD19', 'offset': 72, 'type': 'R Byte', 'size': 4, 'desc': 'JEDEC Basic Flash Parameter Table: 19th DWORD ', 'FIELDS': {'8S8S8S_DISABLE_SEQ': {'name': '8S8S8S_DISABLE_SEQ', 'bit': 0, 'size': 4, 'desc': '8S-8S-8S mode disable sequences'}, '8S8S8S_ENABLE_SEQ': {'name': '8S8S8S_ENABLE_SEQ', 'bit': 4, 'size': 5, 'desc': '8S-8S-8S mode enable sequences'}, '088_MODE_SUPPORTED': {'name': '088_MODE_SUPPORTED', 'bit': 9, 'size': 1, 'desc': '0-8-8 mode supported'}, '088_EXIT_METHOD': {'name': '088_EXIT_METHOD', 'bit': 10, 'size': 6, 'desc': '0-8-8 Mode Exit Method'}, '088_ENTRY_METHOD': {'name': '088_ENTRY_METHOD', 'bit': 16, 'size': 4, 'desc': '0-8-8 Mode Entry Method'}, 'OCTAL_ENABLE_REQ': {'name': 'OCTAL_ENABLE_REQ', 'bit': 20, 'size': 3, 'desc': 'Octal Enable Requirements'}, 'RESERVED': {'name': 'RESERVED', 'bit': 23, 'size': 9, 'desc': 'Reserved'}}}

[*] [DEBUG] + DWORD20 : {'name': 'DWORD20', 'offset': 76, 'type': 'R Byte', 'size': 4, 'desc': ' ', 'FIELDS': {'MAX4SMODE_SPEED_WITHOUT_STRB': {'name': 'MAX4SMODE_SPEED_WITHOUT_STRB', 'bit': 0, 'size': 4, 'desc': 'Maximum operation speed of device in 4S-4S-4S mode when not utilizing Data Strobe'}, 'MAX4SMODE_SPEED_WITH_STRB': {'name': 'MAX4SMODE_SPEED_WITH_STRB', 'bit': 4, 'size': 4, 'desc': 'Maximum operation speed of device in 4S-4S-4S mode when utilizing Data Strobe'}, 'MAX4S4D4DMODE_SPEED_WITHOUT_STRB': {'name': 'MAX4S4D4DMODE_SPEED_WITHOUT_STRB', 'bit': 8, 'size': 4, 'desc': 'Maximum operation speed of device in 4S-4D-4D mode when not utilizing Data Strobe'}, 'MAX4S4D4DMODE_SPEED_WITH_STRB': {'name': 'MAX4S4D4DMODE_SPEED_WITH_STRB', 'bit': 12, 'size': 4, 'desc': 'Maximum operation speed of device in 4S-4D-4D mode when utilizing Data Strobe'}, 'MAX8SMODE_SPEED_WITHOUT_STRB': {'name': 'MAX8SMODE_SPEED_WITHOUT_STRB', 'bit': 16, 'size': 4, 'desc': 'Maximum operation speed of device in 8S-8S-8S mode when not utilizing Data Strobe'}, 'MAX8SMODE_SPEED_WITH_STRB': {'name': 'MAX8SMODE_SPEED_WITH_STRB', 'bit': 20, 'size': 4, 'desc': 'Maximum operation speed of device in 8S-8S-8S mode when utilizing Data Strobe'}, 'MAX8DMODE_SPEED_WITHOUT_STRB': {'name': 'MAX8DMODE_SPEED_WITHOUT_STRB', 'bit': 24, 'size': 4, 'desc': 'Maximum operation speed of device in 8D-8D-8D mode when not utilizing Data Strobe'}, 'MAX8DMODE_SPEED_WITH_STRB': {'name': 'MAX8DMODE_SPEED_WITH_STRB', 'bit': 28, 'size': 4, 'desc': 'Maximum operation speed of device in 8D-8D-8D mode when utilizing Data Strobe'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/tpm12.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + TPM_ACCESS : {'name': 'TPM_ACCESS', 'type': 'memory', 'access': 'mmio', 'address': 4275306496, 'offset': 0, 'size': 1, 'desc': 'TPM ACCESS', 'FIELDS': {'tpmRegValidSts': {'name': 'tpmRegValidSts', 'bit': 7, 'size': 1, 'desc': 'tpmRegValidSts'}, 'reserved': {'name': 'reserved', 'bit': 6, 'size': 1, 'desc': 'reserved'}, 'activeLocality': {'name': 'activeLocality', 'bit': 5, 'size': 1, 'desc': 'activeLocality'}, 'beenSeized': {'name': 'beenSeized', 'bit': 4, 'size': 1, 'desc': 'beenSeized'}, 'Seize': {'name': 'Seize', 'bit': 3, 'size': 1, 'desc': 'Seize'}, 'pendingRequest': {'name': 'pendingRequest', 'bit': 2, 'size': 1, 'desc': 'pendingRequest'}, 'requestUse': {'name': 'requestUse', 'bit': 1, 'size': 1, 'desc': 'requestUse'}, 'tpmEstablishment': {'name': 'tpmEstablishment', 'bit': 0, 'size': 1, 'desc': 'tpmEstablishment'}}}

[*] [DEBUG] + TPM_STS : {'name': 'TPM_STS', 'type': 'memory', 'access': 'mmio', 'address': 4275306520, 'offset': 0, 'size': 4, 'desc': 'TPM STATUS', 'FIELDS': {'burstCount': {'name': 'burstCount', 'bit': 8, 'size': 24, 'desc': 'burstCount'}, 'stsValid': {'name': 'stsValid', 'bit': 7, 'size': 1, 'desc': 'stsValid'}, 'commandReady': {'name': 'commandReady', 'bit': 6, 'size': 1, 'desc': 'commandReady'}, 'tpmGo': {'name': 'tpmGo', 'bit': 5, 'size': 1, 'desc': 'tpmGo'}, 'dataAvail': {'name': 'dataAvail', 'bit': 4, 'size': 1, 'desc': 'dataAvail'}, 'Expect': {'name': 'Expect', 'bit': 3, 'size': 1, 'desc': 'Expect'}, 'Reserved': {'name': 'Reserved', 'bit': 0, 'size': 1, 'desc': 'Reserved'}, 'responseRetry': {'name': 'responseRetry', 'bit': 1, 'size': 1, 'desc': 'responseRetry'}}}

[*] [DEBUG] + TPM_DID_VID : {'name': 'TPM_DID_VID', 'type': 'memory', 'access': 'mmio', 'address': 4275310336, 'offset': 0, 'size': 4, 'desc': 'TPM DID/VID', 'FIELDS': {'did': {'name': 'did', 'bit': 16, 'size': 16, 'desc': 'did'}, 'vid': {'name': 'vid', 'bit': 0, 'size': 16, 'desc': 'vid'}}}

[*] [DEBUG] + TPM_RID : {'name': 'TPM_RID', 'type': 'memory', 'access': 'mmio', 'address': 4275310340, 'offset': 0, 'size': 1, 'desc': 'TPM RID', 'FIELDS': {'rid': {'name': 'rid', 'bit': 0, 'size': 8, 'desc': 'rid'}}}

[*] [DEBUG] + TPM_INTF_CAPABILITY: {'name': 'TPM_INTF_CAPABILITY', 'type': 'memory', 'access': 'mmio', 'address': 4275306516, 'offset': 0, 'size': 4, 'desc': 'TPM INTF CAPABILITY', 'FIELDS': {'Reserved': {'name': 'Reserved', 'bit': 9, 'size': 23, 'desc': 'Reserved'}, 'BurstCountStatic': {'name': 'BurstCountStatic', 'bit': 8, 'size': 1, 'desc': 'BurstCountStatic'}, 'CommandReadyIntSupport': {'name': 'CommandReadyIntSupport', 'bit': 7, 'size': 1, 'desc': 'CommandReadyIntSupport'}, 'InterruptEdgeFalling': {'name': 'InterruptEdgeFalling', 'bit': 6, 'size': 1, 'desc': 'InterruptEdgeFalling'}, 'InterruptEdgeRising': {'name': 'InterruptEdgeRising', 'bit': 5, 'size': 1, 'desc': 'InterruptEdgeRising'}, 'InterruptLevelLow': {'name': 'InterruptLevelLow', 'bit': 4, 'size': 1, 'desc': 'InterruptLevelLow'}, 'InterruptLevelHigh': {'name': 'InterruptLevelHigh', 'bit': 3, 'size': 1, 'desc': 'InterruptLevelHigh'}, 'LocalityChangeIntSupport': {'name': 'LocalityChangeIntSupport', 'bit': 2, 'size': 1, 'desc': 'LocalityChangeIntSupport'}, 'stsValidIntSupport': {'name': 'stsValidIntSupport', 'bit': 1, 'size': 1, 'desc': 'stsValidIntSupport'}, 'dataAvailIntSupport': {'name': 'dataAvailIntSupport', 'bit': 0, 'size': 1, 'desc': 'dataAvailIntSupport'}}}

[*] [DEBUG] + TPM_INT_ENABLE : {'name': 'TPM_INT_ENABLE', 'type': 'memory', 'access': 'mmio', 'address': 4275306504, 'offset': 0, 'size': 4, 'desc': 'TPM INT ENABLE', 'FIELDS': {'globalIntEnable': {'name': 'globalIntEnable', 'bit': 31, 'size': 1, 'desc': 'CommandReadyIntSupport'}, 'Reserved': {'name': 'Reserved', 'bit': 8, 'size': 23, 'desc': 'InterruptEdgeFalling'}, 'commandReadyEnable': {'name': 'commandReadyEnable', 'bit': 7, 'size': 1, 'desc': 'InterruptEdgeRising'}, 'reserved': {'name': 'reserved', 'bit': 5, 'size': 2, 'desc': 'InterruptLevelLow'}, 'typePolarity': {'name': 'typePolarity', 'bit': 3, 'size': 2, 'desc': 'InterruptLevelHigh'}, 'localityChangeIntEnable': {'name': 'localityChangeIntEnable', 'bit': 2, 'size': 1, 'desc': 'LocalityChangeIntSupport'}, 'stsValidIntEnable': {'name': 'stsValidIntEnable', 'bit': 1, 'size': 1, 'desc': 'stsValidIntSupport'}, 'dataAvailIntEnable': {'name': 'dataAvailIntEnable', 'bit': 0, 'size': 1, 'desc': 'dataAvailIntSupport'}}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] [*] Collecting locks configuration data...

[*] [DEBUG] [*] Loading primary config data: /home/cmr/chipsec/chipsec/cfg/8086/txt.xml

[*] [DEBUG] [*] Collecting pci configuration data...

[*] [DEBUG] [*] Collecting mmio configuration data...

[*] [DEBUG] [*] Collecting io configuration data...

[*] [DEBUG] [*] Collecting ima configuration data...

[*] [DEBUG] [*] Collecting memory configuration data...

[*] [DEBUG] [*] Collecting registers configuration data...

[*] [DEBUG] + TXT_STS : {'name': 'TXT_STS', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 0, 'size': 8, 'desc': 'TXT Status', 'FIELDS': {'SENTER_DONE_STS': {'name': 'SENTER_DONE_STS', 'bit': 0, 'size': 1, 'desc': 'SENTER Done'}, 'SEXIT_DONE_STS': {'name': 'SEXIT_DONE_STS', 'bit': 1, 'size': 1, 'desc': 'SEXIT Done'}, 'MEM_UNLOCK_STS': {'name': 'MEM_UNLOCK_STS', 'bit': 4, 'size': 1, 'desc': 'Memory Unlocked'}, 'MEM_BASE_LOCK_STS': {'name': 'MEM_BASE_LOCK_STS', 'bit': 5, 'size': 1, 'desc': 'Memory Base Locked'}, 'MEM_CONFIG_LOCK_STS': {'name': 'MEM_CONFIG_LOCK_STS', 'bit': 6, 'size': 1, 'desc': 'Memory Configuration Locked'}, 'PRIVATE_OPEN_STS': {'name': 'PRIVATE_OPEN_STS', 'bit': 7, 'size': 1, 'desc': 'Open-Private Command Performed'}, 'NTP_ENABLE_STS': {'name': 'NTP_ENABLE_STS', 'bit': 10, 'size': 1, 'desc': 'NTP Enabled'}, 'MEM_CONFIG_OK_STS': {'name': 'MEM_CONFIG_OK_STS', 'bit': 11, 'size': 1, 'desc': 'Mem CFG OK'}, 'PMRC_LOCK_STS': {'name': 'PMRC_LOCK_STS', 'bit': 12, 'size': 1, 'desc': 'PMRC Locked'}, 'SMM_OPEN_STS': {'name': 'SMM_OPEN_STS', 'bit': 13, 'size': 1, 'desc': 'SMM Opened'}, 'TXT_LOCALITY3_OPEN_STS': {'name': 'TXT_LOCALITY3_OPEN_STS', 'bit': 14, 'size': 1, 'desc': 'Locality 3 Opened'}, 'TXT_LOCALITY1_OPEN_STS': {'name': 'TXT_LOCALITY1_OPEN_STS', 'bit': 15, 'size': 1, 'desc': 'Locality 1 Opened'}, 'TXT_LOCALITY2_OPEN_STS': {'name': 'TXT_LOCALITY2_OPEN_STS', 'bit': 16, 'size': 1, 'desc': 'Locality 2 Opened'}, 'SEQ_IN_PROGRESS': {'name': 'SEQ_IN_PROGRESS', 'bit': 17, 'size': 1, 'desc': 'Seq In Progress'}}}

[*] [DEBUG] + TXT_ESTS : {'name': 'TXT_ESTS', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 8, 'size': 8, 'desc': 'TXT Error Status', 'FIELDS': {'TXT_RESET_STS': {'name': 'TXT_RESET_STS', 'bit': 0, 'size': 1, 'desc': 'TXT Reset'}, 'ROGUE_STS': {'name': 'ROGUE_STS', 'bit': 1, 'size': 1, 'desc': 'Rogue Status'}, 'MEMORY_ATTACK': {'name': 'MEMORY_ATTACK', 'bit': 2, 'size': 1, 'desc': 'Memory Attack'}, 'ALIAS_FAULT': {'name': 'ALIAS_FAULT', 'bit': 5, 'size': 1, 'desc': 'Alias Fault'}, 'WAKE_ERROR_STS': {'name': 'WAKE_ERROR_STS', 'bit': 6, 'size': 1, 'desc': 'Wake Error'}}}

[*] [DEBUG] + TXT_THREADS_EXISTS: {'name': 'TXT_THREADS_EXISTS', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 16, 'size': 8, 'desc': 'TXT Threads Exists', 'FIELDS': {}}

[*] [DEBUG] + TXT_THREADS_JOIN: {'name': 'TXT_THREADS_JOIN', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 32, 'size': 8, 'desc': 'TXT Threads Join', 'FIELDS': {}}

[*] [DEBUG] + TXT_ERRORCODE : {'name': 'TXT_ERRORCODE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 48, 'size': 8, 'desc': 'TXT Error Code (0xC0000001 when successful SINIT)', 'FIELDS': {'TYPE2_MODULE_TYPE': {'name': 'TYPE2_MODULE_TYPE', 'bit': 0, 'size': 4, 'desc': 'Module Type (0 for BIOS ACM, 1 for SINIT)'}, 'TYPE2_CLASS_CODE': {'name': 'TYPE2_CLASS_CODE', 'bit': 4, 'size': 6, 'desc': 'Class Code'}, 'TYPE2_MAJOR_ERROR_CODE': {'name': 'TYPE2_MAJOR_ERROR_CODE', 'bit': 10, 'size': 5, 'desc': 'Major Error Code'}, 'SOFTWARE_SOURCE': {'name': 'SOFTWARE_SOURCE', 'bit': 15, 'size': 1, 'desc': 'Software Source (0 for ACM, 1 of MLE)'}, 'TYPE1_MINOR_ERROR_CODE': {'name': 'TYPE1_MINOR_ERROR_CODE', 'bit': 16, 'size': 12, 'desc': 'Minor Error Code'}, 'TYPE1_RESERVED': {'name': 'TYPE1_RESERVED', 'bit': 28, 'size': 2, 'desc': 'Failure Condition Details'}, 'SOFTWARE': {'name': 'SOFTWARE', 'bit': 30, 'size': 1, 'desc': 'Error reported by Software (0 for Processor)'}, 'VALID': {'name': 'VALID', 'bit': 31, 'size': 1, 'desc': 'Valid Register Content'}}}

[*] [DEBUG] + TXT_CRASH2 : {'name': 'TXT_CRASH2', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 80, 'size': 8, 'desc': 'Second Error Code', 'FIELDS': {}}

[*] [DEBUG] + TXT_SPAD : {'name': 'TXT_SPAD', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 160, 'size': 8, 'desc': 'Boot Status', 'FIELDS': {'ACM_INTERNAL': {'name': 'ACM_INTERNAL', 'bit': 0, 'size': 30, 'desc': 'ACM Internal Use'}, 'TXT_STARTUP_SUCCESS': {'name': 'TXT_STARTUP_SUCCESS', 'bit': 30, 'size': 1, 'desc': 'TXT Startup Success'}, 'BOOT_STATUS': {'name': 'BOOT_STATUS', 'bit': 31, 'size': 16, 'desc': 'General Startup ACM to BIOS status communication'}, 'MEM_POWER_DOWN_EXECUTED': {'name': 'MEM_POWER_DOWN_EXECUTED', 'bit': 47, 'size': 1, 'desc': 'Memory content was cleared via power down'}, 'BOOT_STATUS_DETAILS_48': {'name': 'BOOT_STATUS_DETAILS_48', 'bit': 48, 'size': 5, 'desc': 'Startup ACM to BIOS communication in MP platforms'}, 'TXT_POLICY_ENABLE': {'name': 'TXT_POLICY_ENABLE', 'bit': 53, 'size': 1, 'desc': 'Startup ACM indication of run-time enabled status of TXT'}, 'BOOT_STATUS_DETAILS_54': {'name': 'BOOT_STATUS_DETAILS_54', 'bit': 54, 'size': 5, 'desc': 'Startup ACM to BIOS communication in MP platforms'}, 'BIOS_TRUSTED': {'name': 'BIOS_TRUSTED', 'bit': 59, 'size': 1, 'desc': 'BIOS is trusted'}, 'TXT_POLICY_DISABLE': {'name': 'TXT_POLICY_DISABLE', 'bit': 60, 'size': 1, 'desc': 'TXT has been disabled by runtime FIT type 0xA record policy setting'}, 'BOOT_STATUS_DETAILS_61': {'name': 'BOOT_STATUS_DETAILS_61', 'bit': 61, 'size': 1, 'desc': 'Startup ACM to BIOS communication in MP platforms'}, 'CPU_ERROR': {'name': 'CPU_ERROR', 'bit': 62, 'size': 1, 'desc': 'ACM authentication error'}, 'S_ACM_SUCCESS': {'name': 'S_ACM_SUCCESS', 'bit': 63, 'size': 1, 'desc': 'S-ACM successfully enforced its logic for all provisioned technologies'}}}

[*] [DEBUG] + TXT_VER_FSBIF : {'name': 'TXT_VER_FSBIF', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 256, 'size': 4, 'desc': 'TXT Front Side Bus Interface', 'FIELDS': {'DEBUG_FUSE': {'name': 'DEBUG_FUSE', 'bit': 31, 'size': 1, 'desc': 'Chipset is Production Fused (0 for Debug)'}}}

[*] [DEBUG] + TXT_DIDVID : {'name': 'TXT_DIDVID', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 272, 'size': 8, 'desc': 'TXT Device ID', 'FIELDS': {'VID': {'name': 'VID', 'bit': 0, 'size': 16, 'desc': 'Vendor ID'}, 'DID': {'name': 'DID', 'bit': 16, 'size': 16, 'desc': 'Device ID'}, 'RID': {'name': 'RID', 'bit': 32, 'size': 16, 'desc': 'Revision ID'}, 'EXTID': {'name': 'EXTID', 'bit': 48, 'size': 16, 'desc': 'Extended ID'}}}

[*] [DEBUG] + TXT_EID : {'name': 'TXT_EID', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 280, 'size': 8, 'desc': 'TXT EID', 'FIELDS': {}}

[*] [DEBUG] + TXT_VER_QPIIF : {'name': 'TXT_VER_QPIIF', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 512, 'size': 4, 'desc': 'TXT Intel QuickPath Interconnect Interface', 'FIELDS': {'PMRC_CAPABLE': {'name': 'PMRC_CAPABLE', 'bit': 19, 'size': 1, 'desc': 'PMRC Capable'}, 'DPR_CAPABLE': {'name': 'DPR_CAPABLE', 'bit': 26, 'size': 1, 'desc': 'DPR Capable'}, 'DEBUG_FUSE': {'name': 'DEBUG_FUSE', 'bit': 31, 'size': 1, 'desc': 'Chipset is Production Fused (0 for Debug)'}}}

[*] [DEBUG] + TXT_NODMA_BASE : {'name': 'TXT_NODMA_BASE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 608, 'size': 4, 'desc': 'No DMA Base Address', 'FIELDS': {}}

[*] [DEBUG] + TXT_NODMA_SIZE : {'name': 'TXT_NODMA_SIZE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 616, 'size': 4, 'desc': 'No DMA Size', 'FIELDS': {}}

[*] [DEBUG] + TXT_SINIT_BASE : {'name': 'TXT_SINIT_BASE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 624, 'size': 4, 'desc': 'SINIT Base Address', 'FIELDS': {}}

[*] [DEBUG] + TXT_SINIT_SIZE : {'name': 'TXT_SINIT_SIZE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 632, 'size': 4, 'desc': 'SINIT Size', 'FIELDS': {}}

[*] [DEBUG] + TXT_MLE_JOIN : {'name': 'TXT_MLE_JOIN', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 656, 'size': 4, 'desc': 'MLE Join Base Address', 'FIELDS': {}}

[*] [DEBUG] + TXT_BLOCKMAP_CAP: {'name': 'TXT_BLOCKMAP_CAP', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 672, 'size': 8, 'desc': 'Block Map CAP', 'FIELDS': {}}

[*] [DEBUG] + TXT_BLOCKMAP_CNF: {'name': 'TXT_BLOCKMAP_CNF', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 680, 'size': 8, 'desc': 'Block Map CNF', 'FIELDS': {}}

[*] [DEBUG] + TXT_BLOCKMAP_POINTER: {'name': 'TXT_BLOCKMAP_POINTER', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 688, 'size': 8, 'desc': 'Block Map Pointer', 'FIELDS': {}}

[*] [DEBUG] + TXT_HEAP_BASE : {'name': 'TXT_HEAP_BASE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 768, 'size': 4, 'desc': 'TXT Heap Base Address', 'FIELDS': {}}

[*] [DEBUG] + TXT_HEAP_SIZE : {'name': 'TXT_HEAP_SIZE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 776, 'size': 4, 'desc': 'TXT Heap Size', 'FIELDS': {}}

[*] [DEBUG] + TXT_MSEG_BASE : {'name': 'TXT_MSEG_BASE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 784, 'size': 4, 'desc': 'TXT MSEG Base Address', 'FIELDS': {}}

[*] [DEBUG] + TXT_MSEG_SIZE : {'name': 'TXT_MSEG_SIZE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 792, 'size': 4, 'desc': 'TXT MSEG Size', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_0: {'name': 'TXT_SCRATCHPAD_0', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 800, 'size': 8, 'desc': 'TXT Scratchpad 0', 'FIELDS': {}}

[*] [DEBUG] + TXT_ACM_STATUS : {'name': 'TXT_ACM_STATUS', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 808, 'size': 4, 'desc': 'TXT ACM Status', 'FIELDS': {'MODULE_TYPE': {'name': 'MODULE_TYPE', 'bit': 0, 'size': 4, 'desc': 'Module Type'}, 'CLASS_CODE': {'name': 'CLASS_CODE', 'bit': 4, 'size': 6, 'desc': 'Class Code'}, 'MAJOR_ERROR_CODE': {'name': 'MAJOR_ERROR_CODE', 'bit': 10, 'size': 5, 'desc': 'Major Error Code'}, 'ACM_STARTED': {'name': 'ACM_STARTED', 'bit': 15, 'size': 1, 'desc': 'ACM Started'}, 'MINOR_ERROR_CODE': {'name': 'MINOR_ERROR_CODE', 'bit': 16, 'size': 12, 'desc': 'Minor Error Code'}, 'VALID': {'name': 'VALID', 'bit': 31, 'size': 1, 'desc': 'Valid'}}}

[*] [DEBUG] + TXT_ACM_BIOS_POLICY: {'name': 'TXT_ACM_BIOS_POLICY', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 812, 'size': 4, 'desc': 'TXT ACM BIOS Policy', 'FIELDS': {}}

[*] [DEBUG] + TXT_DPR : {'name': 'TXT_DPR', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 816, 'size': 4, 'desc': 'TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR)', 'FIELDS': {'LOCK': {'name': 'LOCK', 'bit': 0, 'size': 1, 'desc': 'Lock Bits 19:0'}, 'SIZE': {'name': 'SIZE', 'bit': 4, 'size': 8, 'desc': 'Protected Memory Size (in MB)'}, 'TOP': {'name': 'TOP', 'bit': 20, 'size': 12, 'desc': 'Top Address+1 of DPR (base of TSEG)'}}}

[*] [DEBUG] + TXT_FIT : {'name': 'TXT_FIT', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 832, 'size': 4, 'desc': 'FIT (Firmware Interface Table)', 'FIELDS': {'FIT_FAILED': {'name': 'FIT_FAILED', 'bit': 0, 'size': 1, 'desc': 'FIT Failed'}, 'S_ACM_FAILED': {'name': 'S_ACM_FAILED', 'bit': 1, 'size': 1, 'desc': 'S-ACM Failed'}, 'FIT_MEASURED': {'name': 'FIT_MEASURED', 'bit': 2, 'size': 1, 'desc': 'FIT Measured'}, 'FIT_FALLBACK': {'name': 'FIT_FALLBACK', 'bit': 3, 'size': 1, 'desc': 'FIT Fallback'}}}

[*] [DEBUG] + TXT_INCREMENT : {'name': 'TXT_INCREMENT', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 848, 'size': 8, 'desc': 'TXT Increment', 'FIELDS': {}}

[*] [DEBUG] + TXT_SPAD_3 : {'name': 'TXT_SPAD_3', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 856, 'size': 8, 'desc': 'TXT Status 3', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_4: {'name': 'TXT_SCRATCHPAD_4', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 864, 'size': 8, 'desc': 'TXT Scratchpad 4', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_5: {'name': 'TXT_SCRATCHPAD_5', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 872, 'size': 8, 'desc': 'TXT Scratchpad 5', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_2 : {'name': 'TXT_INCREMENT_2', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 880, 'size': 8, 'desc': 'TXT Increment 2', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD : {'name': 'TXT_SCRATCHPAD', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 888, 'size': 8, 'desc': 'ACM Policy Status', 'FIELDS': {'KM_ID': {'name': 'KM_ID', 'bit': 0, 'size': 4, 'desc': 'Key Manifest ID used for verified Key Manifest'}, 'MEASURED_BOOT': {'name': 'MEASURED_BOOT', 'bit': 4, 'size': 1, 'desc': 'Perform measured boot'}, 'VERIFIED_BOOT': {'name': 'VERIFIED_BOOT', 'bit': 5, 'size': 1, 'desc': 'Perform verified boot'}, 'HAP': {'name': 'HAP', 'bit': 6, 'size': 1, 'desc': 'High Assurance Platform'}, 'TXT_SUPPORTED': {'name': 'TXT_SUPPORTED', 'bit': 7, 'size': 1, 'desc': 'TXT Supported'}, 'BOOT_MEDIA': {'name': 'BOOT_MEDIA', 'bit': 8, 'size': 1, 'desc': 'Boot media'}, 'DCD': {'name': 'DCD', 'bit': 9, 'size': 1, 'desc': 'Disable CPU Debug'}, 'DBI': {'name': 'DBI', 'bit': 10, 'size': 1, 'desc': 'Disable BSP Init'}, 'PBE': {'name': 'PBE', 'bit': 11, 'size': 1, 'desc': 'Protect BIOS Environment'}, 'BBP': {'name': 'BBP', 'bit': 12, 'size': 1, 'desc': 'Bypass Boot Policy, fast S3 resume'}, 'TPM_TYPE': {'name': 'TPM_TYPE', 'bit': 13, 'size': 2, 'desc': 'TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)'}, 'TPM_SUCCESS': {'name': 'TPM_SUCCESS', 'bit': 15, 'size': 1, 'desc': 'TPM Success'}, 'BOOT_POLICIES_2': {'name': 'BOOT_POLICIES_2', 'bit': 17, 'size': 1, 'desc': 'Boot Policies'}, 'BACKUP_ACTION': {'name': 'BACKUP_ACTION', 'bit': 18, 'size': 2, 'desc': 'Backup Action'}, 'TXT_PROFILE': {'name': 'TXT_PROFILE', 'bit': 20, 'size': 5, 'desc': 'TXT Profile'}, 'MEMORY_SCRUB_POLICY': {'name': 'MEMORY_SCRUB_POLICY', 'bit': 25, 'size': 2, 'desc': 'Memory Scrub Policy'}, 'KM_ARB_EN': {'name': 'KM_ARB_EN', 'bit': 27, 'size': 1, 'desc': 'KM ARB (Key Manifest Anti-Rollback) enable'}, 'BPM_ARB_EN': {'name': 'BPM_ARB_EN', 'bit': 28, 'size': 1, 'desc': 'BPM ARB (Boot Policy Manifest Anti-Rollback) enable'}, 'IBB_DMA_PROTECTION': {'name': 'IBB_DMA_PROTECTION', 'bit': 29, 'size': 1, 'desc': 'IBB (Initial Boot Block) DMA Protection'}, 'S_CRTM_STATUS': {'name': 'S_CRTM_STATUS', 'bit': 32, 'size': 3, 'desc': 'Startup ACM S-CRTM establishment'}, 'CPU_COSIGNING_ENABLE': {'name': 'CPU_COSIGNING_ENABLE', 'bit': 35, 'size': 1, 'desc': 'CPU co-signing enabled'}, 'TPM_STARTUP_LOCALITY': {'name': 'TPM_STARTUP_LOCALITY', 'bit': 36, 'size': 1, 'desc': 'Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)'}}}

[*] [DEBUG] + TXT_PUBLIC_KEY_0: {'name': 'TXT_PUBLIC_KEY_0', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1024, 'size': 8, 'desc': 'ACM Public Key Hash (bits 0:63)', 'FIELDS': {}}

[*] [DEBUG] + TXT_PUBLIC_KEY_1: {'name': 'TXT_PUBLIC_KEY_1', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1032, 'size': 8, 'desc': 'ACM Public Key Hash (bits 64:127)', 'FIELDS': {}}

[*] [DEBUG] + TXT_PUBLIC_KEY_2: {'name': 'TXT_PUBLIC_KEY_2', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1040, 'size': 8, 'desc': 'ACM Public Key Hash (bits 128:191)', 'FIELDS': {}}

[*] [DEBUG] + TXT_PUBLIC_KEY_3: {'name': 'TXT_PUBLIC_KEY_3', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1048, 'size': 8, 'desc': 'ACM Public Key Hash (bits 192:255)', 'FIELDS': {}}

[*] [DEBUG] + TXT_ESTS_SET : {'name': 'TXT_ESTS_SET', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1544, 'size': 8, 'desc': 'TXT ESTS Set', 'FIELDS': {}}

[*] [DEBUG] + TXT_EXISTS_SET : {'name': 'TXT_EXISTS_SET', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1552, 'size': 8, 'desc': 'TXT EXISTS Set', 'FIELDS': {}}

[*] [DEBUG] + TXT_JOINS_SET : {'name': 'TXT_JOINS_SET', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1568, 'size': 8, 'desc': 'TXT JOINS Set', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCLEAN_SET : {'name': 'TXT_SCLEAN_SET', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1648, 'size': 8, 'desc': 'TXT SCLEAN Set', 'FIELDS': {}}

[*] [DEBUG] + TXT_SPAD_SET : {'name': 'TXT_SPAD_SET', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1696, 'size': 8, 'desc': 'TXT SPAD Set', 'FIELDS': {}}

[*] [DEBUG] + TXT_EXISTS_CLEAR: {'name': 'TXT_EXISTS_CLEAR', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1808, 'size': 8, 'desc': 'TXT EXISTS Clear', 'FIELDS': {}}

[*] [DEBUG] + TXT_JOINS_CLEAR : {'name': 'TXT_JOINS_CLEAR', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1824, 'size': 8, 'desc': 'TXT EXISTS Clear', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCLEAN_CLEAR: {'name': 'TXT_SCLEAN_CLEAR', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1904, 'size': 8, 'desc': 'TXT SCLEAN Clear', 'FIELDS': {}}

[*] [DEBUG] + TXT_SPAD_CLEAR : {'name': 'TXT_SPAD_CLEAR', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 1952, 'size': 8, 'desc': 'TXT SPAD Clear', 'FIELDS': {}}

[*] [DEBUG] + TXT_VER_FTIF : {'name': 'TXT_VER_FTIF', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2048, 'size': 4, 'desc': 'TXT FT Interface', 'FIELDS': {'TPM_IF': {'name': 'TPM_IF', 'bit': 16, 'size': 4, 'desc': 'TPM Interface (0 if not present, 1 for LPC, 5 for SPI, 7 for CRB and fTPM)'}}}

[*] [DEBUG] + TXT_PCH_DIDVID : {'name': 'TXT_PCH_DIDVID', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2064, 'size': 8, 'desc': 'TXT Platform Controller Hub Device ID', 'FIELDS': {'VID': {'name': 'VID', 'bit': 0, 'size': 16, 'desc': 'Vendor ID'}, 'DID': {'name': 'DID', 'bit': 16, 'size': 16, 'desc': 'Device ID'}, 'RID': {'name': 'RID', 'bit': 32, 'size': 16, 'desc': 'Revision ID'}}}

[*] [DEBUG] + INSMM : {'name': 'INSMM', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2176, 'size': 4, 'desc': 'InSMM.STS (also known as LT.UCS)', 'FIELDS': {'STS': {'name': 'STS', 'bit': 0, 'size': 1, 'desc': 'BIOS Write Enable when enabled by SPI.BC.EISS=1'}}}

[*] [DEBUG] + TXT_E2STS : {'name': 'TXT_E2STS', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2288, 'size': 8, 'desc': 'TXT Extended Error Status', 'FIELDS': {'SLEEP_ENTRY_ERROR_STS': {'name': 'SLEEP_ENTRY_ERROR_STS', 'bit': 0, 'size': 1, 'desc': 'Sleep Entry Error'}, 'SECRETS_STS': {'name': 'SECRETS_STS', 'bit': 1, 'size': 1, 'desc': 'Secrets in Memory'}, 'BLOCK_MEM_STS': {'name': 'BLOCK_MEM_STS', 'bit': 2, 'size': 1, 'desc': 'Block Memory'}, 'RESET_STS': {'name': 'RESET_STS', 'bit': 3, 'size': 1, 'desc': 'Reset Status'}, 'RESET_POLICY': {'name': 'RESET_POLICY', 'bit': 32, 'size': 1, 'desc': 'Reset Policy'}}}

[*] [DEBUG] + TXT_FT_REGS1 : {'name': 'TXT_FT_REGS1', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2304, 'size': 4, 'desc': 'TXT FT Regs 1', 'FIELDS': {}}

[*] [DEBUG] + TXT_FT_REGS2 : {'name': 'TXT_FT_REGS2', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 2308, 'size': 4, 'desc': 'TXT FT Regs 2', 'FIELDS': {}}

[*] [DEBUG] + TXT_SEQ_START : {'name': 'TXT_SEQ_START', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3456, 'size': 8, 'desc': 'TXT Seq Start', 'FIELDS': {}}

[*] [DEBUG] + TXT_SEQ_DONE : {'name': 'TXT_SEQ_DONE', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3472, 'size': 8, 'desc': 'TXT Seq Done', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_3 : {'name': 'TXT_INCREMENT_3', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3480, 'size': 8, 'desc': 'TXT Increment 3', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_7: {'name': 'TXT_SCRATCHPAD_7', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3488, 'size': 8, 'desc': 'TXT Scratchpad 7', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_4 : {'name': 'TXT_INCREMENT_4', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3496, 'size': 8, 'desc': 'TXT Increment 4', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_8: {'name': 'TXT_SCRATCHPAD_8', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3504, 'size': 8, 'desc': 'TXT Scratchpad 8', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_5 : {'name': 'TXT_INCREMENT_5', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3512, 'size': 8, 'desc': 'TXT Increment 5', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_9: {'name': 'TXT_SCRATCHPAD_9', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3520, 'size': 8, 'desc': 'TXT Scratchpad 9', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_6 : {'name': 'TXT_INCREMENT_6', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3528, 'size': 8, 'desc': 'TXT Increment 6', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_10: {'name': 'TXT_SCRATCHPAD_10', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3536, 'size': 8, 'desc': 'TXT Scratchpad 10', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_7 : {'name': 'TXT_INCREMENT_7', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3544, 'size': 8, 'desc': 'TXT Increment 7', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_11: {'name': 'TXT_SCRATCHPAD_11', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3552, 'size': 8, 'desc': 'TXT Scratchpad 11', 'FIELDS': {}}

[*] [DEBUG] + TXT_INCREMENT_8 : {'name': 'TXT_INCREMENT_8', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3560, 'size': 8, 'desc': 'TXT Increment 8', 'FIELDS': {}}

[*] [DEBUG] + TXT_SCRATCHPAD_12: {'name': 'TXT_SCRATCHPAD_12', 'type': 'memory', 'access': 'mmio', 'address': 4275240960, 'offset': 3568, 'size': 8, 'desc': 'TXT Scratchpad 12', 'FIELDS': {}}

[*] [DEBUG] [*] Collecting controls configuration data...

[*] [DEBUG] [*] Collecting locks configuration data...

[*] Discovering Bus Configuration:

[*] [HAL] [pci] reading B/D/F: 0/0/0, offset: 0x00, value: 0x59148086

[*] [HAL] [pci] reading B/D/F: 0/0/0, offset: 0x08, value: 0x08

[*] [HAL] [pci] reading B/D/F: 0/2/0, offset: 0x00, value: 0x59178086

[*] [HAL] [pci] reading B/D/F: 0/2/0, offset: 0x08, value: 0x07

[*] [HAL] [pci] reading B/D/F: 0/4/0, offset: 0x00, value: 0x19038086

[*] [HAL] [pci] reading B/D/F: 0/4/0, offset: 0x08, value: 0x08

[*] [HAL] [pci] reading B/D/F: 0/8/0, offset: 0x00, value: 0x19118086

[*] [HAL] [pci] reading B/D/F: 0/8/0, offset: 0x08, value: 0x00

[*] [HAL] [pci] reading B/D/F: 0/20/0, offset: 0x00, value: 0x9D2F8086

[*] [HAL] [pci] reading B/D/F: 0/20/0, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/20/2, offset: 0x00, value: 0x9D318086

[*] [HAL] [pci] reading B/D/F: 0/20/2, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/22/0, offset: 0x00, value: 0x9D3A8086

[*] [HAL] [pci] reading B/D/F: 0/22/0, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/28/0, offset: 0x00, value: 0x9D108086

[*] [HAL] [pci] reading B/D/F: 0/28/0, offset: 0x08, value: 0xF1

[*] [HAL] [pci] reading B/D/F: 0/28/6, offset: 0x00, value: 0x9D168086

[*] [HAL] [pci] reading B/D/F: 0/28/6, offset: 0x08, value: 0xF1

[*] [HAL] [pci] reading B/D/F: 0/29/0, offset: 0x00, value: 0x9D188086

[*] [HAL] [pci] reading B/D/F: 0/29/0, offset: 0x08, value: 0xF1

[*] [HAL] [pci] reading B/D/F: 0/29/2, offset: 0x00, value: 0x9D1A8086

[*] [HAL] [pci] reading B/D/F: 0/29/2, offset: 0x08, value: 0xF1

[*] [HAL] [pci] reading B/D/F: 0/31/0, offset: 0x00, value: 0x9D4E8086

[*] [HAL] [pci] reading B/D/F: 0/31/0, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x00, value: 0x9D218086

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/31/3, offset: 0x00, value: 0x9D718086

[*] [HAL] [pci] reading B/D/F: 0/31/3, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/31/4, offset: 0x00, value: 0x9D238086

[*] [HAL] [pci] reading B/D/F: 0/31/4, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 0/31/6, offset: 0x00, value: 0x15D78086

[*] [HAL] [pci] reading B/D/F: 0/31/6, offset: 0x08, value: 0x21

[*] [HAL] [pci] reading B/D/F: 3/0/0, offset: 0x00, value: 0x24FD8086

[*] [HAL] [pci] reading B/D/F: 3/0/0, offset: 0x08, value: 0x78

[*] [HAL] [pci] reading B/D/F: 61/0/0, offset: 0x00, value: 0x576510EC

[*] [HAL] [pci] reading B/D/F: 61/0/0, offset: 0x08, value: 0x01

BDF | VID:DID | Vendor | Device

-------------------------------------------------------------------------

00:00.0 | 8086:5914 | Intel Corporation | Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers

00:02.0 | 8086:5917 | Intel Corporation | UHD Graphics 620

00:04.0 | 8086:1903 | Intel Corporation | Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem

00:08.0 | 8086:1911 | Intel Corporation | Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model

00:14.0 | 8086:9D2F | Intel Corporation | Sunrise Point-LP USB 3.0 xHCI Controller

00:14.2 | 8086:9D31 | Intel Corporation | Sunrise Point-LP Thermal subsystem

00:16.0 | 8086:9D3A | Intel Corporation | Sunrise Point-LP CSME HECI #1

00:1C.0 | 8086:9D10 | Intel Corporation | Sunrise Point-LP PCI Express Root Port #1

00:1C.6 | 8086:9D16 | Intel Corporation | Sunrise Point-LP PCI Express Root Port #7

00:1D.0 | 8086:9D18 | Intel Corporation | Sunrise Point-LP PCI Express Root Port #9

00:1D.2 | 8086:9D1A | Intel Corporation | Sunrise Point-LP PCI Express Root Port #11

00:1F.0 | 8086:9D4E | Intel Corporation | Sunrise Point LPC Controller/eSPI Controller

00:1F.2 | 8086:9D21 | Intel Corporation | Sunrise Point-LP PMC

00:1F.3 | 8086:9D71 | Intel Corporation | Sunrise Point-LP HD Audio

00:1F.4 | 8086:9D23 | Intel Corporation | Sunrise Point-LP SMBus

00:1F.6 | 8086:15D7 | Intel Corporation | Ethernet Connection (4) I219-LM

03:00.0 | 8086:24FD | Intel Corporation | Wireless 8265 / 8275

3D:00.0 | 10EC:5765 | Realtek Semiconductor Co., Ltd. |

[CHIPSEC] OS : Linux 6.1.0-12-amd64 #1 SMP PREEMPT_DYNAMIC Debian 6.1.52-1 (2023-09-07) x86_64

[CHIPSEC] Python : 3.11.2 (64-bit) - Enabled GIL

[CHIPSEC] Helper : LinuxHelper (/home/cmr/chipsec/chipsec/helper/linux/chipsec.ko)

[CHIPSEC] Platform: Mobile 8th Generation Core Processor (Kabylake U-Quad Core)

[CHIPSEC] CPUID: 806EA

[CHIPSEC] VID: 8086

[CHIPSEC] DID: 5914

[CHIPSEC] RID: 08

[CHIPSEC] PCH : PCH-U with iHDCP 2.2 Premium

[CHIPSEC] VID: 8086

[CHIPSEC] DID: 9D4E

[CHIPSEC] RID: 21

[*] Running from /home/cmr/chipsec

[+] loaded chipsec.modules.common.bios_smi

[*] running loaded modules ..

[*] Running module: chipsec.modules.common.bios_smi

[+] imported: chipsec.modules.common.bios_smi

[*] Module path: /home/cmr/chipsec/chipsec/modules/common/bios_smi.py

[x][ =======================================================================

[x][ Module: SMI Events Configuration

[x][ =======================================================================

[*] [HAL] [pci] reading B/D/F: 0/31/5, offset: 0xDC, value: 0x00000AAA

[*] BC = 0x00000AAA << BIOS Control (b:d.f 00:31.5 + 0xDC)

[00] BIOSWE = 0 << BIOS Write Enable

[01] BLE = 1 << BIOS Lock Enable

[02] SRC = 2 << SPI Read Configuration

[04] TSS = 0 << Top Swap Status

[05] SMM_BWP = 1 << SMM BIOS Write Protection

[06] BBS = 0 << Boot BIOS Strap

[07] BILD = 1 << BIOS Interface Lock Down

[+] SMM BIOS region write protection is enabled (SMM_BWP is used)

[*] Checking SMI enables..

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x40, value: 0x00001801

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x40, value: 0x00001801

[*] SMI_EN = 0x98002033 << SMI Control and Enable (I/O ABASE + 0x30)

[00] GBL_SMI_EN = 1 << GBL_SMI_EN

[01] EOS = 1 << EOS

[02] BIOS_EN = 0 << BIOS_EN

[03] LEGACY_USB_EN = 0 << LEGACY_USB_EN

[04] SLP_SMI_EN = 1 << SLP_SMI_EN

[05] APMC_EN = 1 << APMC_EN

[06] SWSMI_TMR_EN = 0 << SWSMI_TMR_EN

[07] BIOS_RLS = 0 << BIOS_RLS

[11] MCSMI_EN = 0 << MCSMI_EN

[13] TCO_EN = 1 << TCO_EN

[14] PERIODIC_EN = 0 << PERIODIC_EN

[17] LEGACY_USB2_EN = 0 << LEGACY_USB2_EN

[18] INTEL_USB2_EN = 0 << INTEL_USB2_EN

[27] GPIO_UNLOCK_SMI_EN = 1 << GPIO_UNLOCK_SMI_EN

[30] ME_SMI_EN = 0 << ME_SMI_EN

[31] xHCI_SMI_EN = 1 << xHCI_SMI_EN

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x40, value: 0x00001801

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0x40, value: 0x00001801

[*] SMI_EN = 0x98002033 << SMI Control and Enable (I/O ABASE + 0x30)

[00] GBL_SMI_EN = 1 << GBL_SMI_EN

[01] EOS = 1 << EOS

[02] BIOS_EN = 0 << BIOS_EN

[03] LEGACY_USB_EN = 0 << LEGACY_USB_EN

[04] SLP_SMI_EN = 1 << SLP_SMI_EN

[05] APMC_EN = 1 << APMC_EN

[06] SWSMI_TMR_EN = 0 << SWSMI_TMR_EN

[07] BIOS_RLS = 0 << BIOS_RLS

[11] MCSMI_EN = 0 << MCSMI_EN

[13] TCO_EN = 1 << TCO_EN

[14] PERIODIC_EN = 0 << PERIODIC_EN

[17] LEGACY_USB2_EN = 0 << LEGACY_USB2_EN

[18] INTEL_USB2_EN = 0 << INTEL_USB2_EN

[27] GPIO_UNLOCK_SMI_EN = 1 << GPIO_UNLOCK_SMI_EN

[30] ME_SMI_EN = 0 << ME_SMI_EN

[31] xHCI_SMI_EN = 1 << xHCI_SMI_EN

Global SMI enable: 1

TCO SMI enable : 1

[+] All required SMI events are enabled

[*] Checking SMI configuration locks..

[*] [HAL] [pci] reading B/D/F: 0/31/4, offset: 0x50, value: 0x00000401

[*] [HAL] [pci] reading B/D/F: 0/31/4, offset: 0x50, value: 0x00000401

[*] TCO1_CNT = 0x1800 << TCO1 Control (I/O TCOBASE + 0x8)

[12] TCO_LOCK = 1 << TCO Lock

[+] TCO SMI configuration is locked (TCO SMI Lock)

[*] [HAL] [pci] reading B/D/F: 0/31/2, offset: 0xA0, value: 0x988036F8

[*] GEN_PMCON_1 = 0x988036F8 << General PM Configuration A (b:d.f 00:31.2 + 0xA0)

[04] SMI_LOCK = 1 << SMI_LOCK

[+] SMI events global configuration is locked (SMI Lock)

[+] PASSED: All required SMI sources seem to be enabled and locked

[CHIPSEC] *************************** SUMMARY ***************************

[CHIPSEC] Time elapsed 0.002

[CHIPSEC] Modules failed to run 0:

[CHIPSEC] Modules passed 1:

[+] PASSED: chipsec.modules.common.bios_smi

[CHIPSEC] Modules information 0:

[CHIPSEC] Modules failed 0:

[CHIPSEC] Modules with warnings 0:

[CHIPSEC] Modules not applicable 0:

[CHIPSEC] Modules total 1

[CHIPSEC] *****************************************************************

[*] [DEBUG] Module for /dev/chipsec unloaded successfully

[*] [DEBUG] [helper] Linux Helper stopped/unloaded

[*] [DEBUG] [helper] Linux Helper deleted