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flashrom 1.4.0 (git:v0.2.0-1280-g3691f514) on Linux 5.15.45-heads (x86_64)
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flashrom was built with GCC 8.3.0, little endian
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Command line (8 args): flashrom -p internal -c N25Q128..3E -Vw /media/coreboot-2170p.rom -o /tmp/flashrom_n.log
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Initializing internal programmer
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/sys/class/mtd/mtd0 does not exist
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Found candidate at: 00000500-00000528
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Found coreboot table at 0x00000500.
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Found candidate at: 00000000-000008dc
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Found coreboot table at 0x00000000.
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coreboot table found at 0x7fe4e000.
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coreboot header(24) checksum: be04 table(2244) checksum: a762 entries: 39
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Vendor ID: HP, part ID: EliteBook 2170p
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Using Internal DMI decoder.
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DMI string chassis-type: "Laptop"
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Laptop detected via DMI.
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DMI string system-manufacturer: "HP"
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DMI string system-product-name: "EliteBook 2170p"
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DMI string system-version: "1.0"
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DMI string baseboard-manufacturer: "HP"
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DMI string baseboard-product-name: "EliteBook 2170p"
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DMI string baseboard-version: "1.0"
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Found chipset "Intel QM77" with PCI ID 8086:1e55.
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Enabling flash write... Root Complex Register Block address = 0xfed1c000
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GCS = 0xc20: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI)
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Top Swap: not enabled
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0x7fffffff/0x7fffffff FWH IDSEL: 0x0
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0x7fffffff/0x7fffffff FWH IDSEL: 0x0
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0x7fffffff/0x7fffffff FWH IDSEL: 0x1
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0x7fffffff/0x7fffffff FWH IDSEL: 0x1
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0x7fffffff/0x7fffffff FWH IDSEL: 0x2
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0x7fffffff/0x7fffffff FWH IDSEL: 0x2
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0x7fffffff/0x7fffffff FWH IDSEL: 0x3
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0x7fffffff/0x7fffffff FWH IDSEL: 0x3
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0x7fffffff/0x7fffffff FWH IDSEL: 0x4
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0x7fffffff/0x7fffffff FWH IDSEL: 0x5
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0x7fffffff/0x7fffffff FWH IDSEL: 0x6
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0x7fffffff/0x7fffffff FWH IDSEL: 0x7
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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0x7fffffff/0x7fffffff FWH decode enabled
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Maximum FWH chip size: 0x100000 bytes
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SPI Read Configuration: prefetching enabled, caching enabled,
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BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
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SPIBAR = 0x00007f070490e000 + 0x3800
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0x04: 0x6008 (HSFS)
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HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0
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Programming OPCODES...
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program_opcodes: preop=5006 optype=463b opmenu=05200302c79f0190
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done
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OP Type Pre-OP
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op[0]: 0x02, write w/ addr, none
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op[1]: 0x03, read w/ addr, none
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op[2]: 0x20, write w/ addr, none
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op[3]: 0x05, read w/o addr, none
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op[4]: 0x90, read w/ addr, none
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op[5]: 0x01, write w/o addr, none
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op[6]: 0x9f, read w/o addr, none
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op[7]: 0xc7, write w/o addr, none
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Pre-OP 0: 0x06, Pre-OP 1: 0x50
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0x06: 0x0000 (HSFC)
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HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
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0x08: 0x00000052 (FADDR)
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0x50: 0x0000ffff (FRAP)
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BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff
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0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.
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0x58: 0x0fff0020 FREG1: BIOS region (0x00020000-0x00ffffff) is read-write.
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0x5C: 0x001f0003 FREG2: Management Engine region (0x00003000-0x0001ffff) is read-write.
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0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write.
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0x64: 0x00000fff FREG4: Platform Data region is unused.
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0x74: 0x0fff0000 (PR0 is unused)
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0x78: 0x00000000 (PR1 is unused)
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0x7C: 0x00000000 (PR2 is unused)
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0x80: 0x00000000 (PR3 is unused)
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0x84: 0x00000000 (PR4 is unused)
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0x90: 0x84 (SSFS)
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SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
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0x91: 0xf84220 (SSFC)
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SSFC: SCGO=0, ACS=0, SPOP=0, COP=2, DBC=2, SME=0, SCF=0
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0x94: 0x5006 (PREOP)
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0x96: 0x463b (OPTYPE)
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0x98: 0x05200302 (OPMENU)
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0x9c: 0xc79f0190 (OPMENU+4)
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0xa0: 0x00000000 (BBAR)
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0xc4: 0x00800000 (LVSCC)
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LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1
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0xc8: 0x00002005 (UVSCC)
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UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
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0xd0: 0x00000000 (FPB)
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Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
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=== Content Section ===
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FLVALSIG 0x0ff0a55a
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FLMAP0 0x03040003
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FLMAP1 0x12100206
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FLMAP2 0x00210120
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--- Details ---
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NR (Number of Regions): 4
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FRBA (Flash Region Base Address): 0x040
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NC (Number of Components): 1
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FCBA (Flash Component Base Address): 0x030
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ISL (ICH/PCH/SoC Strap Length): 18
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FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100
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NM (Number of Masters): 3
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FMBA (Flash Master Base Address): 0x060
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MSL/PSL (MCH/PROC Strap Length): 1
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FMSBA (Flash MCH/PROC Strap Base Address): 0x200
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=== Component Section ===
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FLCOMP 0x24900025
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FLILL 0x00000000
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--- Details ---
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Component 1 density: 16 MB
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Component 2 is not used.
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Read Clock Frequency: 20 MHz
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Read ID and Status Clock Freq.: 50 MHz
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Write and Erase Clock Freq.: 50 MHz
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Fast Read is supported.
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Fast Read Clock Frequency: 50 MHz
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Dual Output Fast Read Support: disabled
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No forbidden opcodes.
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=== Region Section ===
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FLREG0 0x00000000
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FLREG1 0x0fff0020
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FLREG2 0x001f0003
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FLREG3 0x00020001
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--- Details ---
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Region 0 (Descr. ) 0x00000000 - 0x00000fff
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Region 1 (BIOS ) 0x00020000 - 0x00ffffff
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Region 2 (ME ) 0x00003000 - 0x0001ffff
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Region 3 (GbE ) 0x00001000 - 0x00002fff
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=== Master Section ===
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FLMSTR1 0xffff0000
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FLMSTR2 0xffff0000
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FLMSTR3 0x08080118
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--- Details ---
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Descr. BIOS ME GbE Platf.
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BIOS rw rw rw rw rw
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ME rw rw rw rw rw
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GbE rw
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OK.
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No board enable found matching coreboot IDs vendor="HP", model="EliteBook 2170p".
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The following protocols are supported: SPI.
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Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: compare_id: id1 0x20, id2 0xba18
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Added layout entry 00000000 - 00ffffff named complete flash
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Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI) mapped at physical address 0x00000000ff000000.
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Chip status register is 0x00.
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Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
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Chip status register: Block Protect 3 (BP3) is not set
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Chip status register: Top/Bottom (TB) is top
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Chip status register: Block Protect 2 (BP2) is not set
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Chip status register: Block Protect 1 (BP1) is not set
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Chip status register: Block Protect 0 (BP0) is not set
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Chip status register: Write Enable Latch (WEL) is not set
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Chip status register: Write In Progress (WIP/BUSY) is not set
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This chip may contain one-time programmable memory. flashrom cannot read
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and may never be able to write it, hence it may not be able to completely
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clone the contents of this chip (see man page for details).
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===
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This flash part has status UNTESTED for operations: WP
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The test status of this chip may have been updated in the latest development
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version of flashrom. If you are running the latest development version,
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please email a report to flashrom@flashrom.org if any of the above operations
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work correctly for you with this flash chip. Please include the flashrom log
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file for all operations you tested (see the man page for details), and mention
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which mainboard or programmer you tested in the subject line.
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You can also try to follow the instructions here:
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https://www.flashrom.org/contrib_howtos/how_to_mark_chip_tested.html
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Thanks for your help!
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coreboot last image size (not ROM size) is 16777216 bytes.
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Manufacturer: HP
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Mainboard ID: EliteBook 2170p
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This coreboot image matches this mainboard.
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Block protection is disabled.
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Reading old flash chip contents... read_flash: region (00000000..0xffffff) is readable, reading range (00000000..0xffffff).
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done.
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erase_write: region (00000000..0xffffff) is writable, erasing range (00000000..0xffffff).
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0x20000..0x20fff verify_range: Verifying region (00000000..0xffffff)
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read_flash: region (00000000..0xffffff) is readable, reading range (0x020000..0x020fff).
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E(20000:20fff)Erase/write done from 0 to ffffff
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Verifying flash... read_flash: region (00000000..0xffffff) is readable, reading range (00000000..0xffffff).
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VERIFIED.
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Restoring MMIO space at 0x7f07049118a0
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Restoring MMIO space at 0x7f0704911874
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Restoring MMIO space at 0x7f070491189c
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Restoring MMIO space at 0x7f0704911898
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Restoring MMIO space at 0x7f0704911896
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Restoring MMIO space at 0x7f0704911894
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