Project

General

Profile

Bug #449 ยป coreboot_t440p_emerg.log

debug info via FT232H - Crazy Fox, 01/14/2023 08:52 PM

 
USB


[NOTE ] coreboot-4.18 Sun Oct 16 20:14:31 UTC 2022 bootblock starting (log level: 7)...
[INFO ] Timestamp - end of bootblock: 1344543182
[INFO ] Timestamp - starting to load romstage: 1360376080
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0xa54000.
[DEBUG] FMAP: base = 0xff400000 size = 0xc00000 #areas = 6
[DEBUG] FMAP: area COREBOOT found @ a54200 (1752576 bytes)
[INFO ] CBFS: mcache @0xff7c2e00 built for 21 files, used 0x444 of 0x4000 bytes
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xc5a8 in mcache @0xff7c2e2c
[INFO ] Timestamp - finished loading romstage: 1472866428
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 59 ms


[NOTE ] coreboot-4.18 Sun Oct 16 20:14:31 UTC 2022 romstage starting (log level: 7)...
[DEBUG] Disabling Watchdog reboot... done.
[DEBUG] SMBus controller enabled
[DEBUG] Setting up static northbridge registers... done.
[DEBUG] Started PEG11 link training.
[DEBUG] Temporarily hiding PEG11.
[DEBUG] Started PEG10 link training.
[DEBUG] Temporarily hiding PEG10.
[DEBUG] Initializing IGD...
[DEBUG] Back from haswell_early_initialization()
[INFO ] POST: 0x3a
[DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4910MQ CPU @ 2.90GHz
[DEBUG] AES supported, TXT supported, VT supported
[DEBUG] PCH type: QM87, device id: 8c4f, rev id 5
[INFO ] Timestamp - before RAM initialization: 1712380386
[DEBUG] Starting UEFI PEI System Agent
[DEBUG] FMAP: area RW_MRC_CACHE found @ a00000 (65536 bytes)
[NOTE ] MRC: no data in 'RW_MRC_CACHE'
[INFO ] CBFS: Found 'mrc.bin' @0x14bdc0 size 0x2e6e4 in mcache @0xff7c31c0
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)USB
[DEBUG] MRC Version 1.6.1 Build 2
[DEBUG] memcfg DDR3 clock 1600 MHz
[DEBUG] memcfg channel assignment: A: 0, B 1, C 2
[DEBUG] memcfg channel[0] config (00620020):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode on
[DEBUG] rank interleave on
[DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected
[DEBUG] DIMMB 0 MB width x8 or x32 single rank
[DEBUG] memcfg channel[1] config (00620020):
[DEBUG] ECC inactive
[DEBUG] enhanced interleave mode on
[DEBUG] rank interleave on
[DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected
[DEBUG] DIMMB 0 MB width x8 or x32 single rank
[INFO ] Timestamp - after RAM initialization: 14802416060
[INFO ] POST: 0x3b
[DEBUG] ME: FW Partition Table : OK
[DEBUG] ME: Bringup Loader Failure : NO
[DEBUG] ME: Firmware Init Complete : NO
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: Boot Options Present : NO
[DEBUG] ME: Update In Progress : NO
[DEBUG] ME: Current Working State : Normal
[DEBUG] ME: Current Operation State : M0 with UMA
[DEBUG] ME: Current Operation Mode : Normal
[DEBUG] ME: Error Code : No Error
[DEBUG] ME: Progress Phase : Host Communication
[DEBUG] ME: Power Management Event : Clean Moff->Mx wake
[DEBUG] ME: Progress Phase State : Host communication established
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x7f7ff000 254 entries.
[DEBUG] IMD: root @ 0x7f7fec00 62 entries.
[INFO ] Timestamp - starting to load ChromeOS VPD: 15052416302
[DEBUG] FMAP: area RO_VPD found @ a50000 (16384 bytes)
[WARN ] RO_VPD is uninitialized or empty.
[ERROR] init_vpd_rdev: No RW_VPD FMAP section.
[DEBUG] External stage cache:
[DEBUG] IMD: root @ 0x7fbff000 254 entries.
[DEBUG] IMD: root @ 0x7fbfec00 62 entries.
[DEBUG] Unhiding PEG10.
[DEBUG] Unhiding PEG11.
[INFO ] POST: 0x3f
[DEBUG] SMM Memory Map
[DEBUG] SMRAM : 0x7f800000 0x800000
[DEBUG] Subregion 0: 0x7f800000 0x300000
[DEBUG] Subregion 1: 0x7fb00000 0x100000
[DEBUG] Subregion 2: 0x7fc00000 0x400000
[DEBUG] Normal boot
[INFO ] CBFS: Found 'fallback/postcar' @0xa7540 size 0x911c in mcache @0xff7c30a4
[DEBUG] Loading module at 0x7f7cb000 with entry 0x7f7cb031. filesize: 0x87e0 memsize: 0xeb98
[DEBUG] Processing 575 relocs. Offset value of 0x7d7cb000
[INFO ] Timestamp - end of romstage: 15325285698
[DEBUG] BS: romstage times (exec / console): total (unknown) / 377 ms
[DEBUG] usbdebug: postcar starting...
[INFO ] Timestamp - start of postcar: 15371020757
[DEBUG] 0x0000000000000d0a: IA32_MTRRCAP: SMRR, WC, FIX, 10 variable MTRRs
[DEBUG] 0x0000000000000800: IA32_MTRR_DEF_TYPE: E, UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: UC
[DEBUG] 0x000000007f000006: PHYBASE0: Address = 0x000000007f000000, WB
[DEBUG] 0x0000007fff000800: PHYMASK0: Length = 0x0000000001000000, Valid
[DEBUG] 0x00000000ff800005: PHYBASE1: Address = 0x00000000ff800000, WP
[DEBUG] 0x0000007fff800800: PHYMASK1: Length = 0x0000000000800000, Valid
[DEBUG] 0x0000000000000000: PHYBASE2
[DEBUG] 0x0000000000000000: PHYMASK2: Disabled
[DEBUG] 0x0000000000000000: PHYBASE3
[DEBUG] 0x0000000000000000: PHYMASK3: Disabled
[DEBUG] 0x0000000000000000: PHYBASE4
[DEBUG] 0x0000000000000000: PHYMASK4: Disabled
[DEBUG] 0x0000000000000000: PHYBASE5
[DEBUG] 0x0000000000000000: PHYMASK5: Disabled
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[DEBUG] 0x0000000000000000: PHYBASE8
[DEBUG] 0x0000000000000000: PHYMASK8: Disabled
[DEBUG] 0x0000000000000000: PHYBASE9
[DEBUG] 0x0000000000000000: PHYMASK9: Disabled
[INFO ] Timestamp - end of postcar: 16019833537
[DEBUG] Normal boot
[INFO ] Timestamp - starting to load ramstage: 16041894461
[INFO ] CBFS: Found 'fallback/ramstage' @0x187c0 size 0x82c8c in mcache @0x7f7dd10c
[INFO ] Timestamp - starting LZMA decompress (ignore for x86): 16084161497
[INFO ] Timestamp - finished LZMA decompress (ignore for x86): 16634322730
[DEBUG] Loading module at 0x7f600000 with entry 0x7f600000. filesize: 0x15e810 memsize: 0x1c8f78
[DEBUG] Processing 109200 relocs. Offset value of 0x7b600000
[DEBUG] Error: Can't add stage_cache 57a9e100 to imd
[INFO ] Timestamp - finished loading ramstage: 16719631725
[DEBUG] BS: postcar times (exec / console): total (unknown) / 288 ms
[DEBUG] usbdebug: ramstage starting...
[INFO ] Timestamp - start of ramstage: 16769512813
[INFO ] POST: 0x6f
[DEBUG] Normal boot
[INFO ] POST: 0x70
[DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 2 ms
[INFO ] POST: 0x71
[INFO ] Timestamp - device enumeration: 16831751844
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 8 ms
[INFO ] POST: 0x72
[INFO ] Enumerating buses...
[DEBUG] Root Device scanning...
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 0000 enabled
[DEBUG] DOMAIN: 0000 scanning...
[DEBUG] PCI: pci_scan_bus for bus 00
[INFO ] POST: 0x24
[DEBUG] PCI: 00:00.0 [8086/0c04] enabled
[INFO ] PCI: Static device PCI: 00:01.0 not found, disabling it.
[ERROR] shift out of bounds src/northbridge/intel/haswell/pcie.c:85:22
[EMERG] ubsan: unrecoverable error.

    (1-1/1)