|
|
|
[NOTE ] coreboot-4.18-1399-g7f5adef634 Tue Jan 03 18:52:14 UTC 2023 bootblock starting (log level: 7)...
|
|
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x600000.
|
|
[DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 3
|
|
[DEBUG] FMAP: area COREBOOT found @ 600200 (2096640 bytes)
|
|
[INFO ] CBFS: mcache @0xfefc2e00 built for 16 files, used 0x364 of 0x4000 bytes
|
|
[INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xdcd8 in mcache @0xfefc2e2c
|
|
[DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
|
|
[DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe00000, size: 0x00010000
|
|
|
|
|
|
[NOTE ] coreboot-4.18-1399-g7f5adef634 Tue Jan 03 18:52:14 UTC 2023 romstage starting (log level: 7)...
|
|
[DEBUG] SMBus controller enabled
|
|
[DEBUG] Stepping B3
|
|
[DEBUG] 0:50:b
|
|
[DEBUG] 2:51:b
|
|
[DEBUG] Setting IGD memory frequencies for VCO #1.
|
|
[DEBUG] Memory configured in dual-channel asymmetric mode.
|
|
[DEBUG] JEDEC init @0x00000000
|
|
[DEBUG] JEDEC init @0x08000000
|
|
[DEBUG] JEDEC init @0x10000000
|
|
[DEBUG] JEDEC init @0x18000000
|
|
[DEBUG] group 0, ch 0: 6.1.0.3.6
|
|
[DEBUG] group 1, ch 0: 6.0.2.6.7
|
|
[DEBUG] group 2, ch 0: 6.1.2.2.2
|
|
[DEBUG] group 3, ch 0: 6.1.0.7.7
|
|
[DEBUG] group 0, ch 1: 6.1.0.0.7
|
|
[DEBUG] group 1, ch 1: 6.0.2.3.7
|
|
[DEBUG] group 2, ch 1: 6.1.2.0.3
|
|
[DEBUG] group 3, ch 1: 6.1.0.6.7
|
|
[DEBUG] byte lane 0, ch 0: 5.1
|
|
[DEBUG] byte lane 1, ch 0: 4.6
|
|
[DEBUG] byte lane 2, ch 0: 5.1
|
|
[DEBUG] byte lane 3, ch 0: 5.1
|
|
[DEBUG] byte lane 4, ch 0: 5.0
|
|
[DEBUG] byte lane 5, ch 0: 4.5
|
|
[DEBUG] byte lane 6, ch 0: 4.6
|
|
[DEBUG] byte lane 7, ch 0: 5.3
|
|
[DEBUG] byte lane 0, ch 1: 5.0
|
|
[DEBUG] byte lane 1, ch 1: 5.2
|
|
[DEBUG] byte lane 2, ch 1: 5.3
|
|
[DEBUG] byte lane 3, ch 1: 4.5
|
|
[DEBUG] byte lane 4, ch 1: 5.1
|
|
[DEBUG] byte lane 5, ch 1: 5.1
|
|
[DEBUG] byte lane 6, ch 1: 4.4
|
|
[DEBUG] byte lane 7, ch 1: 4.6
|
|
[DEBUG] group 0, ch 0: 1.10.3
|
|
[DEBUG] group 1, ch 0: 1.9.4
|
|
[DEBUG] group 2, ch 0: 2.5.0
|
|
[DEBUG] group 3, ch 0: 2.8.3
|
|
[DEBUG] IGD decoded, subtracting 32M UMA and 4M GTT
|
|
[DEBUG] Memory configured in dual-channel interleaved mode.
|
|
[DEBUG] Enabling IGD.
|
|
[DEBUG] Finally disabling PEG in favor of IGD.
|
|
[DEBUG] PEG x1 disabled, SDVO disabled
|
|
[DEBUG] ICH9 waits for VC1 negotiation... done.
|
|
[DEBUG] ICH9 waits for port arbitration table update... done.
|
|
[DEBUG] CBMEM:
|
|
[DEBUG] IMD: root @ 0x7d7ff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7d7fec00 62 entries.
|
|
[DEBUG] FMAP: area COREBOOT found @ 600200 (2096640 bytes)
|
|
[DEBUG] External stage cache:
|
|
[DEBUG] IMD: root @ 0x7dbff000 254 entries.
|
|
[DEBUG] IMD: root @ 0x7dbfec00 62 entries.
|
|
[DEBUG] SMM Memory Map
|
|
[DEBUG] SMRAM : 0x7da00000 0x200000
|
|
[DEBUG] Subregion 0: 0x7da00000 0x100000
|
|
[DEBUG] Subregion 1: 0x7db00000 0x100000
|
|
[DEBUG] Subregion 2: 0x7dc00000 0x0
|
|
[DEBUG] Normal boot
|
|
[INFO ] CBFS: Found 'fallback/postcar' @0x40c00 size 0x5a60 in mcache @0xfefc302c
|
|
[DEBUG] Loading module at 0x7d7d0000 with entry 0x7d7d0031. filesize: 0x5660 memsize: 0xb998
|
|
[DEBUG] Processing 240 relocs. Offset value of 0x7b7d0000
|
|
[DEBUG] BS: romstage times (exec / console): total (unknown) / 2 ms
|
|
|
|
|
|
[NOTE ] coreboot-4.18-1399-g7f5adef634 Tue Jan 03 18:52:14 UTC 2023 postcar starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] FMAP: area COREBOOT found @ 600200 (2096640 bytes)
|
|
[INFO ] CBFS: Found 'fallback/ramstage' @0x19e40 size 0x1add9 in mcache @0x7d7dd0dc
|
|
[DEBUG] Loading module at 0x7d78b000 with entry 0x7d78b000. filesize: 0x35190 memsize: 0x434d0
|
|
[DEBUG] Processing 3891 relocs. Offset value of 0x7978b000
|
|
[DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
|
|
|
|
|
|
[NOTE ] coreboot-4.18-1399-g7f5adef634 Tue Jan 03 18:52:14 UTC 2023 ramstage starting (log level: 7)...
|
|
[DEBUG] Normal boot
|
|
[DEBUG] Initializing i82801ix southbridge...
|
|
[INFO ] Enumerating buses...
|
|
[DEBUG] Root Device scanning...
|
|
[DEBUG] CPU_CLUSTER: 0 enabled
|
|
[DEBUG] DOMAIN: 0000 enabled
|
|
[DEBUG] DOMAIN: 0000 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 00
|
|
[DEBUG] PCI: 00:00.0 [8086/2a40] enabled
|
|
[DEBUG] PCI: 00:02.0 [8086/2a42] enabled
|
|
[DEBUG] PCI: 00:02.1 [8086/2a43] enabled
|
|
[INFO ] PCI: Static device PCI: 00:03.0 not found, disabling it.
|
|
[DEBUG] PCI: 00:19.0 [8086/10f5] enabled
|
|
[DEBUG] PCI: 00:1a.0 [8086/2937] enabled
|
|
[DEBUG] PCI: 00:1a.1 [8086/2938] enabled
|
|
[DEBUG] PCI: 00:1a.2 [8086/2939] enabled
|
|
[DEBUG] PCI: 00:1a.7 [8086/293c] enabled
|
|
[DEBUG] PCI: 00:1b.0 [8086/293e] enabled
|
|
[DEBUG] PCI: 00:1c.0 [8086/2940] enabled
|
|
[DEBUG] PCI: 00:1c.1 [8086/2942] enabled
|
|
[DEBUG] PCI: 00:1c.2 [8086/2944] enabled
|
|
[DEBUG] PCI: 00:1c.3 [8086/2946] enabled
|
|
[DEBUG] PCI: 00:1d.0 [8086/2934] enabled
|
|
[DEBUG] PCI: 00:1d.1 [8086/2935] enabled
|
|
[DEBUG] PCI: 00:1d.2 [8086/2936] enabled
|
|
[DEBUG] PCI: 00:1d.7 [8086/293a] enabled
|
|
[DEBUG] PCI: 00:1e.0 [8086/2448] enabled
|
|
[DEBUG] PCI: 00:1f.0 [8086/2917] enabled
|
|
[DEBUG] PCI: 00:1f.2 [8086/2928] enabled
|
|
[DEBUG] PCI: 00:1f.3 [8086/2930] enabled
|
|
[WARN ] PCI: Leftover static devices:
|
|
[WARN ] PCI: 00:03.0
|
|
[WARN ] PCI: 00:03.1
|
|
[WARN ] PCI: 00:03.2
|
|
[WARN ] PCI: 00:03.3
|
|
[WARN ] PCI: 00:1c.4
|
|
[WARN ] PCI: 00:1c.5
|
|
[WARN ] PCI: 00:1f.5
|
|
[WARN ] PCI: 00:1f.6
|
|
[WARN ] PCI: Check your devicetree.cb.
|
|
[DEBUG] PCI: 00:1c.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 01
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 02
|
|
[DEBUG] PCI: 02:00.0 [168c/ff1c] enabled
|
|
[INFO ] PCIe: Max_Payload_Size adjusted to 128
|
|
[DEBUG] PCI: 02:00.0: No LTR support
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 03
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.3 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 04
|
|
[DEBUG] scan_bus: bus PCI: 00:1c.3 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1e.0 scanning...
|
|
[DEBUG] PCI: pci_scan_bus for bus 0d
|
|
[DEBUG] scan_bus: bus PCI: 00:1e.0 finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 scanning...
|
|
[INFO ] PMH7: ID 03 Revision 10
|
|
[DEBUG] PNP: 00ff.1 enabled
|
|
[INFO ] H8: EC Firmware ID 7XHT25WW-3.6, Version 7.01A
|
|
[INFO ] H8: BDC not installed
|
|
[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed
|
|
[DEBUG] dock is not connected
|
|
[DEBUG] PNP: 00ff.2 enabled
|
|
[DEBUG] PNP: 164e.3 enabled
|
|
[DEBUG] PNP: 164e.2 disabled
|
|
[DEBUG] PNP: 164e.7 disabled
|
|
[DEBUG] PNP: 164e.19 disabled
|
|
[DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 7 msecs
|
|
[DEBUG] PCI: 00:1f.3 scanning...
|
|
[DEBUG] I2C: 01:54 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
|
|
[DEBUG] bus: PCI: 00:1f.3[0]->scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
|
|
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 8 msecs
|
|
[DEBUG] scan_bus: bus Root Device finished in 8 msecs
|
|
[INFO ] done
|
|
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 8 / 0 ms
|
|
[DEBUG] found VGA at PCI: 00:02.0
|
|
[DEBUG] Setting up VGA for PCI: 00:02.0
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
|
|
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
|
|
[INFO ] Allocating resources...
|
|
[INFO ] Reading resources...
|
|
[DEBUG] TOUUD 0x180000000 TOLUD 0x80000000 TOM 0x100000000
|
|
[DEBUG] IGD decoded, subtracting 32M UMA, 4M GTT and 2M TSEG
|
|
[DEBUG] Unused RAM between cbmem_top and TOM: 0x800K
|
|
[INFO ] Available memory below 4GB: 2008M
|
|
[INFO ] Available memory above 4GB: 2048M
|
|
[DEBUG] Adding UMA memory area base=0x7d800000 size=0x2800000
|
|
[DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
|
|
[ERROR] PNP: 00ff.1 missing read_resources
|
|
[ERROR] PNP: 00ff.2 missing read_resources
|
|
[INFO ] Done reading resources.
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] PCI: 02:00.0 10 * [0x0 - 0xffff] mem
|
|
[DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[DEBUG] PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff
|
|
[DEBUG] NONE 18 * [0x0 - 0x1fff] io
|
|
[DEBUG] PCI: 00:1c.3 io: size: 2000 align: 12 gran: 12 limit: ffff done
|
|
[DEBUG] PCI: 00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
|
|
[DEBUG] NONE 10 * [0x0 - 0x7fffff] mem
|
|
[DEBUG] PCI: 00:1c.3 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done
|
|
[DEBUG] PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
|
|
[DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem
|
|
[DEBUG] PCI: 00:1c.3 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
|
|
[DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
|
|
[DEBUG] update_constraints: PNP: 164e.3 60 base 00000200 limit 00000207 io (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 1000, Size: 5e0, Tag: 100
|
|
[INFO ] * Base: 15f0, Size: ea10, Tag: 100
|
|
[DEBUG] PCI: 00:1c.3 1c * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] PCI: 00:19.0 18 * [0x1000 - 0x101f] limit: 101f io
|
|
[DEBUG] PCI: 00:1a.0 20 * [0x1020 - 0x103f] limit: 103f io
|
|
[DEBUG] PCI: 00:1a.1 20 * [0x1040 - 0x105f] limit: 105f io
|
|
[DEBUG] PCI: 00:1a.2 20 * [0x1060 - 0x107f] limit: 107f io
|
|
[DEBUG] PCI: 00:1d.0 20 * [0x1080 - 0x109f] limit: 109f io
|
|
[DEBUG] PCI: 00:1d.1 20 * [0x10a0 - 0x10bf] limit: 10bf io
|
|
[DEBUG] PCI: 00:1d.2 20 * [0x10c0 - 0x10df] limit: 10df io
|
|
[DEBUG] PCI: 00:1f.2 20 * [0x10e0 - 0x10ff] limit: 10ff io
|
|
[DEBUG] PCI: 00:02.0 20 * [0x1100 - 0x1107] limit: 1107 io
|
|
[DEBUG] PCI: 00:1f.2 10 * [0x1108 - 0x110f] limit: 110f io
|
|
[DEBUG] PCI: 00:1f.2 18 * [0x1110 - 0x1117] limit: 1117 io
|
|
[DEBUG] PCI: 00:1f.2 14 * [0x1118 - 0x111b] limit: 111b io
|
|
[DEBUG] PCI: 00:1f.2 1c * [0x111c - 0x111f] limit: 111f io
|
|
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
|
|
[DEBUG] update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 04 base 000a0000 limit 000bffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 05 base 000c0000 limit 000fffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 06 base 00100000 limit 7d7fffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 07 base 100000000 limit 17fffffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 08 base 7d800000 limit 7fffffff mem (fixed)
|
|
[DEBUG] update_constraints: DOMAIN: 0000 09 base f0000000 limit f3ffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
|
|
[DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
|
|
[INFO ] DOMAIN: 0000: Resource ranges:
|
|
[INFO ] * Base: 80000000, Size: 70000000, Tag: 200
|
|
[INFO ] * Base: f4000000, Size: ac00000, Tag: 200
|
|
[INFO ] * Base: fec01000, Size: bff000, Tag: 200
|
|
[INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
|
|
[DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
|
|
[DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
|
|
[DEBUG] PCI: 00:1c.3 20 * [0x90400000 - 0x90bfffff] limit: 90bfffff mem
|
|
[DEBUG] PCI: 00:02.1 10 * [0x90c00000 - 0x90cfffff] limit: 90cfffff mem
|
|
[DEBUG] PCI: 00:1c.1 20 * [0x90d00000 - 0x90dfffff] limit: 90dfffff mem
|
|
[DEBUG] PCI: 00:19.0 10 * [0x90e00000 - 0x90e1ffff] limit: 90e1ffff mem
|
|
[DEBUG] PCI: 00:1b.0 10 * [0x90e20000 - 0x90e23fff] limit: 90e23fff mem
|
|
[DEBUG] PCI: 00:19.0 14 * [0x90e24000 - 0x90e24fff] limit: 90e24fff mem
|
|
[DEBUG] PCI: 00:1f.2 24 * [0x90e25000 - 0x90e257ff] limit: 90e257ff mem
|
|
[DEBUG] PCI: 00:1a.7 10 * [0x90e26000 - 0x90e263ff] limit: 90e263ff mem
|
|
[DEBUG] PCI: 00:1d.7 10 * [0x90e27000 - 0x90e273ff] limit: 90e273ff mem
|
|
[DEBUG] PCI: 00:1f.3 10 * [0x90e28000 - 0x90e280ff] limit: 90e280ff mem
|
|
[DEBUG] PCI: 00:1c.3 24 * [0x180000000 - 0x18fffffff] limit: 18fffffff prefmem
|
|
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
|
|
[DEBUG] PCI: 00:1c.1 mem: base: 90d00000 size: 100000 align: 20 gran: 20 limit: 90dfffff
|
|
[INFO ] PCI: 00:1c.1: Resource ranges:
|
|
[INFO ] * Base: 90d00000, Size: 100000, Tag: 200
|
|
[DEBUG] PCI: 02:00.0 10 * [0x90d00000 - 0x90d0ffff] limit: 90d0ffff mem
|
|
[DEBUG] PCI: 00:1c.1 mem: base: 90d00000 size: 100000 align: 20 gran: 20 limit: 90dfffff done
|
|
[DEBUG] PCI: 00:1c.3 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
|
|
[INFO ] PCI: 00:1c.3: Resource ranges:
|
|
[INFO ] * Base: 2000, Size: 2000, Tag: 100
|
|
[DEBUG] NONE 18 * [0x2000 - 0x3fff] limit: 3fff io
|
|
[DEBUG] PCI: 00:1c.3 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
|
|
[DEBUG] PCI: 00:1c.3 prefmem: base: 180000000 size: 10000000 align: 20 gran: 20 limit: 18fffffff
|
|
[INFO ] PCI: 00:1c.3: Resource ranges:
|
|
[INFO ] * Base: 180000000, Size: 10000000, Tag: 1200
|
|
[DEBUG] NONE 14 * [0x180000000 - 0x18fffffff] limit: 18fffffff prefmem
|
|
[DEBUG] PCI: 00:1c.3 prefmem: base: 180000000 size: 10000000 align: 20 gran: 20 limit: 18fffffff done
|
|
[DEBUG] PCI: 00:1c.3 mem: base: 90400000 size: 800000 align: 20 gran: 20 limit: 90bfffff
|
|
[INFO ] PCI: 00:1c.3: Resource ranges:
|
|
[INFO ] * Base: 90400000, Size: 800000, Tag: 200
|
|
[DEBUG] NONE 10 * [0x90400000 - 0x90bfffff] limit: 90bfffff mem
|
|
[DEBUG] PCI: 00:1c.3 mem: base: 90400000 size: 800000 align: 20 gran: 20 limit: 90bfffff done
|
|
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
|
|
[DEBUG] DOMAIN: 0000 03 <- [0x0000000000000000 - 0x000000000009ffff] size 0x000a0000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 04 <- [0x00000000000a0000 - 0x00000000000bffff] size 0x00020000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 05 <- [0x00000000000c0000 - 0x00000000000fffff] size 0x00040000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 06 <- [0x0000000000100000 - 0x000000007d7fffff] size 0x7d700000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 07 <- [0x0000000100000000 - 0x000000017fffffff] size 0x80000000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 08 <- [0x000000007d800000 - 0x000000007fffffff] size 0x02800000 gran 0x00 mem
|
|
[DEBUG] DOMAIN: 0000 09 <- [0x00000000f0000000 - 0x00000000f3ffffff] size 0x04000000 gran 0x00 mem
|
|
[DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem64
|
|
[DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
|
|
[DEBUG] PCI: 00:02.0 20 <- [0x0000000000001100 - 0x0000000000001107] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:02.1 10 <- [0x0000000090c00000 - 0x0000000090cfffff] size 0x00100000 gran 0x14 mem64
|
|
[DEBUG] PCI: 00:19.0 10 <- [0x0000000090e00000 - 0x0000000090e1ffff] size 0x00020000 gran 0x11 mem
|
|
[DEBUG] PCI: 00:19.0 14 <- [0x0000000090e24000 - 0x0000000090e24fff] size 0x00001000 gran 0x0c mem
|
|
[DEBUG] PCI: 00:19.0 18 <- [0x0000000000001000 - 0x000000000000101f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.0 20 <- [0x0000000000001020 - 0x000000000000103f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.1 20 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.2 20 <- [0x0000000000001060 - 0x000000000000107f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1a.7 10 <- [0x0000000090e26000 - 0x0000000090e263ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:1b.0 10 <- [0x0000000090e20000 - 0x0000000090e23fff] size 0x00004000 gran 0x0e mem64
|
|
[DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
|
|
[DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
|
|
[DEBUG] PCI: 00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem
|
|
[DEBUG] PCI: 00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io
|
|
[DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
|
|
[DEBUG] PCI: 00:1c.1 20 <- [0x0000000090d00000 - 0x0000000090dfffff] size 0x00100000 gran 0x14 bus 02 mem
|
|
[DEBUG] PCI: 02:00.0 10 <- [0x0000000090d00000 - 0x0000000090d0ffff] size 0x00010000 gran 0x10 mem64
|
|
[DEBUG] PCI: 00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 03 io
|
|
[DEBUG] PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
|
|
[DEBUG] PCI: 00:1c.2 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 03 mem
|
|
[DEBUG] PCI: 00:1c.3 1c <- [0x0000000000002000 - 0x0000000000003fff] size 0x00002000 gran 0x0c bus 04 io
|
|
[DEBUG] PCI: 00:1c.3 24 <- [0x0000000180000000 - 0x000000018fffffff] size 0x10000000 gran 0x14 bus 04 prefmem
|
|
[DEBUG] PCI: 00:1c.3 20 <- [0x0000000090400000 - 0x0000000090bfffff] size 0x00800000 gran 0x14 bus 04 mem
|
|
[DEBUG] PCI: 00:1d.0 20 <- [0x0000000000001080 - 0x000000000000109f] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1d.1 20 <- [0x00000000000010a0 - 0x00000000000010bf] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1d.2 20 <- [0x00000000000010c0 - 0x00000000000010df] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1d.7 10 <- [0x0000000090e27000 - 0x0000000090e273ff] size 0x00000400 gran 0x0a mem
|
|
[DEBUG] PCI: 00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 0d io
|
|
[DEBUG] PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 0d prefmem
|
|
[DEBUG] PCI: 00:1e.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 0d mem
|
|
[ERROR] PNP: 00ff.1 missing set_resources
|
|
[ERROR] PNP: 00ff.2 missing set_resources
|
|
[DEBUG] PNP: 164e.3 60 <- [0x0000000000000200 - 0x0000000000000207] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PNP: 164e.3 29 <- [0x00000000000000b0 - 0x00000000000000af] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PNP: 164e.3 70 <- [0x0000000000000005 - 0x0000000000000005] size 0x00000001 gran 0x00 irq
|
|
[DEBUG] PNP: 164e.3 f0 <- [0x0000000000000082 - 0x0000000000000081] size 0x00000000 gran 0x00 irq
|
|
[DEBUG] PCI: 00:1f.2 10 <- [0x0000000000001108 - 0x000000000000110f] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 14 <- [0x0000000000001118 - 0x000000000000111b] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 18 <- [0x0000000000001110 - 0x0000000000001117] size 0x00000008 gran 0x03 io
|
|
[DEBUG] PCI: 00:1f.2 1c <- [0x000000000000111c - 0x000000000000111f] size 0x00000004 gran 0x02 io
|
|
[DEBUG] PCI: 00:1f.2 20 <- [0x00000000000010e0 - 0x00000000000010ff] size 0x00000020 gran 0x05 io
|
|
[DEBUG] PCI: 00:1f.2 24 <- [0x0000000090e25000 - 0x0000000090e257ff] size 0x00000800 gran 0x0b mem
|
|
[DEBUG] PCI: 00:1f.3 10 <- [0x0000000090e28000 - 0x0000000090e280ff] size 0x00000100 gran 0x08 mem64
|
|
[INFO ] Done setting resources.
|
|
[INFO ] Done allocating resources.
|
|
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
|
|
[INFO ] Enabling resources...
|
|
[DEBUG] PCI: 00:00.0 subsystem <- 17aa/20e0
|
|
[DEBUG] PCI: 00:00.0 cmd <- 06
|
|
[DEBUG] PCI: 00:02.0 subsystem <- 17aa/20e4
|
|
[DEBUG] PCI: 00:02.0 cmd <- 03
|
|
[DEBUG] PCI: 00:02.1 subsystem <- 17aa/20e4
|
|
[DEBUG] PCI: 00:02.1 cmd <- 02
|
|
[DEBUG] PCI: 00:19.0 subsystem <- 8086/10f5
|
|
[DEBUG] PCI: 00:19.0 cmd <- 103
|
|
[DEBUG] PCI: 00:1a.0 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1a.0 cmd <- 01
|
|
[DEBUG] PCI: 00:1a.1 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1a.1 cmd <- 01
|
|
[DEBUG] PCI: 00:1a.2 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1a.2 cmd <- 01
|
|
[DEBUG] PCI: 00:1a.7 subsystem <- 17aa/20f1
|
|
[DEBUG] PCI: 00:1a.7 cmd <- 102
|
|
[DEBUG] PCI: 00:1b.0 subsystem <- 17aa/20f2
|
|
[DEBUG] PCI: 00:1b.0 cmd <- 102
|
|
[DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.0 subsystem <- 17aa/20f3
|
|
[DEBUG] PCI: 00:1c.0 cmd <- 100
|
|
[DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.1 subsystem <- 17aa/20f3
|
|
[DEBUG] PCI: 00:1c.1 cmd <- 106
|
|
[DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.2 subsystem <- 17aa/20f3
|
|
[DEBUG] PCI: 00:1c.2 cmd <- 100
|
|
[DEBUG] PCI: 00:1c.3 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1c.3 subsystem <- 17aa/20f3
|
|
[DEBUG] PCI: 00:1c.3 cmd <- 107
|
|
[DEBUG] PCI: 00:1d.0 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1d.0 cmd <- 01
|
|
[DEBUG] PCI: 00:1d.1 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1d.1 cmd <- 01
|
|
[DEBUG] PCI: 00:1d.2 subsystem <- 17aa/20f0
|
|
[DEBUG] PCI: 00:1d.2 cmd <- 01
|
|
[DEBUG] PCI: 00:1d.7 subsystem <- 17aa/20f1
|
|
[DEBUG] PCI: 00:1d.7 cmd <- 102
|
|
[DEBUG] PCI: 00:1e.0 bridge ctrl <- 0013
|
|
[DEBUG] PCI: 00:1e.0 subsystem <- 17aa/20f4
|
|
[DEBUG] PCI: 00:1e.0 cmd <- 100
|
|
[DEBUG] PCI: 00:1f.0 subsystem <- 8086/2917
|
|
[DEBUG] PCI: 00:1f.0 cmd <- 107
|
|
[DEBUG] PCI: 00:1f.2 subsystem <- 17aa/20f8
|
|
[DEBUG] PCI: 00:1f.2 cmd <- 03
|
|
[DEBUG] PCI: 00:1f.3 subsystem <- 17aa/20f9
|
|
[DEBUG] PCI: 00:1f.3 cmd <- 103
|
|
[DEBUG] PCI: 02:00.0 cmd <- 02
|
|
[INFO ] done.
|
|
[INFO ] Initializing devices...
|
|
[DEBUG] CPU_CLUSTER: 0 init
|
|
[DEBUG] FMAP: area COREBOOT found @ 600200 (2096640 bytes)
|
|
[INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xde00 size 0xc000 in mcache @0x7d7dd0ac
|
|
[DEBUG] microcode: sig=0x1067a pf=0x80 revision=0x0
|
|
[INFO ] microcode: load microcode patch
|
|
[INFO ] microcode: updated to revision 0xa0b date=2010-09-28
|
|
[DEBUG] MTRR: Physical address space:
|
|
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
|
|
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
|
|
[DEBUG] 0x00000000000c0000 - 0x000000007d7fffff size 0x7d740000 type 6
|
|
[DEBUG] 0x000000007d800000 - 0x000000007fffffff size 0x02800000 type 0
|
|
[DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
|
|
[DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
|
|
[DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
|
|
[DEBUG] 0x0000000180000000 - 0x000000018fffffff size 0x10000000 type 0
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
|
|
[DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
|
|
[DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
|
|
[DEBUG] MTRR: default type WB/UC MTRR counts: 7/5.
|
|
[DEBUG] MTRR: UC selected as default type.
|
|
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
|
|
[DEBUG] MTRR: 1 base 0x000000007d800000 mask 0x0000000fff800000 type 0
|
|
[DEBUG] MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
|
|
[DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
|
|
[DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
|
|
|
|
[DEBUG] MTRR check
|
|
[DEBUG] Fixed MTRRs : Enabled
|
|
[DEBUG] Variable MTRRs: Enabled
|
|
|
|
[DEBUG] CPU has 2 cores.
|
|
[DEBUG] Setting up SMI for CPU
|
|
[INFO ] Will perform SMM setup.
|
|
[INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz.
|
|
[INFO ] LAPIC 0x0 in XAPIC mode.
|
|
[DEBUG] CPU: APIC: 00 enabled
|
|
[DEBUG] CPU: APIC: 01 enabled
|
|
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
|
|
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
|
|
[DEBUG] Attempting to start 1 APs
|
|
[DEBUG] Waiting for 10ms after sending INIT.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[DEBUG] Waiting for SIPI to complete...
|
|
[DEBUG] done.
|
|
[INFO ] LAPIC 0x1 in XAPIC mode.
|
|
[INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000a0b
|
|
[DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x00038000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7da00800
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x6c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
|
|
[DEBUG] SMM Module: stub loaded at 38000. Will call 0x7d7a7a9e
|
|
[DEBUG] Installing permanent SMM handler to 0x7da00000
|
|
[DEBUG] FX_SAVE [0x7daffc00-0x7db00000]
|
|
[DEBUG] HANDLER [0x7daff000-0x7daff680]
|
|
|
|
[DEBUG] CPU 0
|
|
[DEBUG] ss0 [0x7dafec00-0x7daff000]
|
|
[DEBUG] stub0 [0x7daf7000-0x7daf71e0]
|
|
|
|
[DEBUG] CPU 1
|
|
[DEBUG] ss1 [0x7dafe800-0x7dafec00]
|
|
[DEBUG] stub1 [0x7daf6c00-0x7daf6de0]
|
|
|
|
[DEBUG] stacks [0x7da00000-0x7da00800]
|
|
[DEBUG] Loading module at 0x7daff000 with entry 0x7daff056. filesize: 0x670 memsize: 0x680
|
|
[DEBUG] Processing 27 relocs. Offset value of 0x7daff000
|
|
[DEBUG] Loading module at 0x7daf7000 with entry 0x7daf7000. filesize: 0x1e0 memsize: 0x1e0
|
|
[DEBUG] Processing 11 relocs. Offset value of 0x7daf7000
|
|
[DEBUG] smm_module_setup_stub: stack_top = 0x7da00800
|
|
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400
|
|
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x6c
|
|
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0x100000
|
|
[DEBUG] SMM Module: placing smm entry code at 7daf6c00, cpu # 0x1
|
|
[DEBUG] SMM Module: stub loaded at 7daf7000. Will call 0x7daff056
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7daef000, cpu = 0
|
|
[DEBUG] In relocation handler: cpu 0
|
|
[DEBUG] New SMBASE=0x7daef000
|
|
[WARN ] SMRR not enabled, skip writing SMRR...
|
|
[DEBUG] Relocation complete.
|
|
[DEBUG] VMX status: enabled
|
|
[DEBUG] VMX status: enabled
|
|
[INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7daeec00, cpu = 1
|
|
[DEBUG] In relocation handler: cpu 1
|
|
[DEBUG] New SMBASE=0x7daeec00
|
|
[DEBUG] Writing SMRR. base = 0x7da00000, mask=0xffe00800
|
|
[DEBUG] Relocation complete.
|
|
[INFO ] Initializing CPU #0
|
|
[DEBUG] CPU: vendor Intel device 1067a
|
|
[DEBUG] CPU: family 06, model 17, stepping 0a
|
|
[INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz.
|
|
[DEBUG] writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 0: 0, 0, 9, 0x21, 35000; encoded: 0x0921
|
|
[INFO ] CPU #0 initialized
|
|
[INFO ] Initializing CPU #1
|
|
[DEBUG] CPU: vendor Intel device 1067a
|
|
[DEBUG] CPU: family 06, model 17, stepping 0a
|
|
[INFO ] CPU: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz.
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617
|
|
[DEBUG] writing P-State 1: 0, 0, 9, 0x21, 35000; encoded: 0x0921
|
|
[INFO ] CPU #1 initialized
|
|
[INFO ] bsp_do_flight_plan done after 11 msecs.
|
|
[DEBUG] SMI_STS:
|
|
[DEBUG] GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO7 GPIO5 GPIO4 GPIO3 GPIO2 GPIO0
|
|
[DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
|
|
[DEBUG] TCO_STS:
|
|
[DEBUG] Locking SMM.
|
|
[DEBUG] CPU_CLUSTER: 0 init finished in 33 msecs
|
|
[DEBUG] DOMAIN: 0000 init
|
|
[DEBUG] DOMAIN: 0000 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:00.0 init
|
|
[DEBUG] PCI: 00:00.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:02.0 init
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[ERROR] Null dereference at eip: 0x7d79d35a
|
|
[NOTE ] Your panels EDID `<NULL>` wasn't found in thelookup table.
|
|
[NOTE ] You may have issues with your panelsbacklight.
|
|
[NOTE ] If you want to help improving corebootplease report: this EDID string
|
|
[NOTE ] and the resultof `intel_read read BLC_PWM_CTL`(from intel-gpu-tools)
|
|
[NOTE ] while running vendor BIOS
|
|
[DEBUG] GMA: Display backlight type not found, assuming LED
|
|
[WARN ] CBFS: 'data_led.vbt' not found.
|
|
[WARN ] CBFS: 'pci8086,2a42.rom' not found.
|
|
[DEBUG] PCI Option ROM loading disabled for PCI: 00:02.0
|
|
[DEBUG] GMA: locate_vbt_vbios: ffff ffff ff ff ff
|
|
[ERROR] GMA: VBT couldn't be found
|
|
[DEBUG] LVDS EDID
|
|
[WARN ] EDID block does NOT fully conform to EDID 1.3.
|
|
[ERROR] Missing name descriptor
|
|
[ERROR] Missing monitor ranges
|
|
[DEBUG] Found EDID string: HV121WX4-120 in lookup table, pwm: 110Hz
|
|
|
|
[0.126233] CONFIG =>
|
|
[0.126234] (Primary =>
|
|
[0.126235] (Port => LVDS ,
|
|
[0.126236] Framebuffer =>
|
|
[0.126237] (Width => 1280,
|
|
[0.126238] Height => 800,
|
|
[0.126239] Start_X => 0,
|
|
[0.126240] Start_Y => 0,
|
|
[0.126241] Stride => 1280,
|
|
[0.126242] V_Stride => 800,
|
|
[0.126243] Tiling => Linear ,
|
|
[0.126244] Rotation => No_Rotation,
|
|
[0.126245] Offset => 0x00000000,
|
|
[0.126246] BPC => 8),
|
|
[0.126247] Mode =>
|
|
[0.126248] (Dotclock => 75160000,
|
|
[0.126249] H_Visible => 1280,
|
|
[0.126250] H_Sync_Begin => 1354,
|
|
[0.126251] H_Sync_End => 1412,
|
|
[0.126252] H_Total => 1522,
|
|
[0.126253] V_Visible => 800,
|
|
[0.126254] V_Sync_Begin => 803,
|
|
[0.126255] V_Sync_End => 809,
|
|
[0.126256] V_Total => 823,
|
|
[0.126257] H_Sync_Active_High => False,
|
|
[0.126258] V_Sync_Active_High => False,
|
|
[0.126259] BPC => 5)),
|
|
[0.126260] Secondary =>
|
|
[0.126261] (Port => Disabled,
|
|
[0.126262] Framebuffer =>
|
|
[0.126263] (Width => 1,
|
|
[0.126264] Height => 1,
|
|
[0.126265] Start_X => 0,
|
|
[0.126266] Start_Y => 0,
|
|
[0.126267] Stride => 1,
|
|
[0.126268] V_Stride => 1,
|
|
[0.126269] Tiling => Linear ,
|
|
[0.126270] Rotation => No_Rotation,
|
|
[0.126271] Offset => 0x00000000,
|
|
[0.126272] BPC => 8),
|
|
[0.126273] Mode =>
|
|
[0.126273] (Dotclock => 1000000,
|
|
[0.126275] H_Visible => 1,
|
|
[0.126276] H_Sync_Begin => 1,
|
|
[0.126277] H_Sync_End => 1,
|
|
[0.126278] H_Total => 1,
|
|
[0.126279] V_Visible => 1,
|
|
[0.126280] V_Sync_Begin => 1,
|
|
[0.126281] V_Sync_End => 1,
|
|
[0.126282] V_Total => 1,
|
|
[0.126283] H_Sync_Active_High => False,
|
|
[0.126284] V_Sync_Active_High => False,
|
|
[0.126285] BPC => 5)),
|
|
[0.126286] Tertiary =>
|
|
[0.126287] (Port => Disabled,
|
|
[0.126288] Framebuffer =>
|
|
[0.126289] (Width => 1,
|
|
[0.126290] Height => 1,
|
|
[0.126291] Start_X => 0,
|
|
[0.126292] Start_Y => 0,
|
|
[0.126293] Stride => 1,
|
|
[0.126294] V_Stride => 1,
|
|
[0.126295] Tiling => Linear ,
|
|
[0.126296] Rotation => No_Rotation,
|
|
[0.126297] Offset => 0x00000000,
|
|
[0.126298] BPC => 8),
|
|
[0.126299] Mode =>
|
|
[0.126299] (Dotclock => 1000000,
|
|
[0.126301] H_Visible => 1,
|
|
[0.126302] H_Sync_Begin => 1,
|
|
[0.126303] H_Sync_End => 1,
|
|
[0.126304] H_Total => 1,
|
|
[0.126305] V_Visible => 1,
|
|
[0.126306] V_Sync_Begin => 1,
|
|
[0.126307] V_Sync_End => 1,
|
|
[0.126308] V_Total => 1,
|
|
[0.126309] H_Sync_Active_High => False,
|
|
[0.126310] V_Sync_Active_High => False,
|
|
[0.126311] BPC => 5)));
|
|
[INFO ] framebuffer_info: bytes_per_line: 5120, bits_per_pixel: 32
|
|
[INFO ] x_res x y_res: 1280 x 800, size: 4096000 at 0x80000000
|
|
[DEBUG] PCI: 00:02.0 init finished in 83 msecs
|
|
[DEBUG] PCI: 00:02.1 init
|
|
[DEBUG] PCI: 00:02.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:19.0 init
|
|
[DEBUG] PCI: 00:19.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.0 init
|
|
[DEBUG] PCI: 00:1a.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.1 init
|
|
[DEBUG] PCI: 00:1a.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.2 init
|
|
[DEBUG] PCI: 00:1a.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1a.7 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1a.7 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1b.0 init
|
|
[DEBUG] Azalia: base = 0x90e20000
|
|
[DEBUG] Azalia: codec_mask = 01
|
|
[DEBUG] azalia_audio: Initializing codec #0
|
|
[DEBUG] azalia_audio: codec viddid: 14f15051
|
|
[DEBUG] azalia_audio: verb_size: 32
|
|
[DEBUG] azalia_audio: verb loaded.
|
|
[DEBUG] PCI: 00:1b.0 init finished in 3 msecs
|
|
[DEBUG] PCI: 00:1c.0 init
|
|
[DEBUG] Initializing ICH9 PCIe root port.
|
|
[DEBUG] PCI: 00:1c.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.1 init
|
|
[DEBUG] Initializing ICH9 PCIe root port.
|
|
[DEBUG] PCI: 00:1c.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.2 init
|
|
[DEBUG] Initializing ICH9 PCIe root port.
|
|
[DEBUG] PCI: 00:1c.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1c.3 init
|
|
[DEBUG] Initializing ICH9 PCIe root port.
|
|
[DEBUG] PCI: 00:1c.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.0 init
|
|
[DEBUG] PCI: 00:1d.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.1 init
|
|
[DEBUG] PCI: 00:1d.1 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.2 init
|
|
[DEBUG] PCI: 00:1d.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1d.7 init
|
|
[DEBUG] EHCI: Setting up controller.. done.
|
|
[DEBUG] PCI: 00:1d.7 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1e.0 init
|
|
[DEBUG] PCI: 00:1e.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.0 init
|
|
[DEBUG] i82801ix: lpc_init
|
|
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
|
|
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
|
|
[INFO ] Set power on after power failure.
|
|
[INFO ] NMI sources disabled.
|
|
[DEBUG] rtc_failed = 0x0
|
|
[DEBUG] RTC Init
|
|
[DEBUG] apm_control: Disabling ACPI.
|
|
[DEBUG] APMC done.
|
|
[DEBUG] PCI: 00:1f.0 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.2 init
|
|
[DEBUG] i82801ix_sata: initializing...
|
|
[DEBUG] SATA controller in AHCI mode.
|
|
[DEBUG] ABAR: 0x90e25000
|
|
[DEBUG] PCI: 00:1f.2 init finished in 0 msecs
|
|
[DEBUG] PCI: 00:1f.3 init
|
|
[DEBUG] PCI: 00:1f.3 init finished in 0 msecs
|
|
[DEBUG] PCI: 02:00.0 init
|
|
[DEBUG] PCI: 02:00.0 init finished in 0 msecs
|
|
[DEBUG] PNP: 00ff.2 init
|
|
[DEBUG] PNP: 00ff.2 init finished in 0 msecs
|
|
[DEBUG] PNP: 164e.3 init
|
|
[DEBUG] PNP: 164e.3 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init
|
|
[DEBUG] I2C: 01:54 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init
|
|
[DEBUG] I2C: 01:55 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init
|
|
[DEBUG] I2C: 01:56 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init
|
|
[DEBUG] I2C: 01:57 init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init
|
|
[DEBUG] Locking EEPROM RFID
|
|
[DEBUG] init EEPROM done
|
|
[DEBUG] I2C: 01:5c init finished in 27 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init
|
|
[DEBUG] I2C: 01:5d init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init
|
|
[DEBUG] I2C: 01:5e init finished in 0 msecs
|
|
[DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init
|
|
[DEBUG] I2C: 01:5f init finished in 0 msecs
|
|
[INFO ] Devices initialized
|
|
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 148 / 1 ms
|
|
[INFO ] Finalize devices...
|
|
[INFO ] Devices finalized
|
|
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3ca00 size 0x3a97 in mcache @0x7d7dd1d8
|
|
[WARN ] CBFS: 'fallback/slic' not found.
|
|
[INFO ] ACPI: Writing ACPI tables at 7d74e000.
|
|
[DEBUG] ACPI: * FACS
|
|
[DEBUG] ACPI: * DSDT
|
|
[DEBUG] ACPI: * FADT
|
|
[DEBUG] ACPI: added table 1/32, length now 40
|
|
[DEBUG] ACPI: * SSDT
|
|
[INFO ] Super I/O probe failed, skipping wacom
|
|
[DEBUG] Found 1 CPU(s) with 2 core(s) each.
|
|
[DEBUG] clocks between 800 and 2533 MHz.
|
|
[DEBUG] adding 4 P-States between busratio 6 and 9, incl. P0
|
|
[DEBUG] PSS: 2401MHz power 35000 control 0x492b status 0x492b
|
|
[DEBUG] PSS: 2400MHz power 35000 control 0x921 status 0x921
|
|
[DEBUG] PSS: 1600MHz power 15000 control 0x617 status 0x617
|
|
[DEBUG] PSS: 800MHz power 12000 control 0x8611 status 0x8611
|
|
[DEBUG] clocks between 800 and 2533 MHz.
|
|
[DEBUG] adding 4 P-States between busratio 6 and 9, incl. P0
|
|
[DEBUG] PSS: 2401MHz power 35000 control 0x492b status 0x492b
|
|
[DEBUG] PSS: 2400MHz power 35000 control 0x921 status 0x921
|
|
[DEBUG] PSS: 1600MHz power 15000 control 0x617 status 0x617
|
|
[DEBUG] PSS: 800MHz power 12000 control 0x8611 status 0x8611
|
|
[DEBUG] PCI space above 4GB MMIO is at 0x180000000, len = 0xe80000000
|
|
[WARN ] CBFS: 'pci8086,2a43.rom' not found.
|
|
[DEBUG] PCI Option ROM loading disabled for PCI: 00:02.1
|
|
[WARN ] PCI: 00:02.1: Missing PCI Option ROM
|
|
[DEBUG] Generating ACPI PIRQ entries
|
|
[INFO ] ACPI: * H8
|
|
[INFO ] H8: BDC not installed
|
|
[INFO ] H8: WWAN detection not implemented. Assuming WWAN installed
|
|
[DEBUG] ACPI: added table 2/32, length now 44
|
|
[DEBUG] ACPI: * MCFG
|
|
[DEBUG] ACPI: added table 3/32, length now 48
|
|
[DEBUG] ACPI: * MADT
|
|
[DEBUG] IOAPIC: 24 interrupts
|
|
[DEBUG] ACPI: added table 4/32, length now 52
|
|
[DEBUG] current = 7d752860
|
|
[DEBUG] ACPI: * DMAR
|
|
[DEBUG] ACPI: added table 5/32, length now 56
|
|
[DEBUG] current = 7d7528e0
|
|
[DEBUG] ACPI: * HPET
|
|
[DEBUG] ACPI: added table 6/32, length now 60
|
|
[INFO ] ACPI: done.
|
|
[DEBUG] ACPI tables: 18720 bytes.
|
|
[DEBUG] smbios_write_tables: 7d746000
|
|
[DEBUG] SMBIOS tables: 727 bytes.
|
|
[DEBUG] Writing table forward entry at 0x00000500
|
|
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 6267
|
|
[DEBUG] Writing coreboot table at 0x7d772000
|
|
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
|
|
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
|
|
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
|
|
[DEBUG] 3. 0000000000100000-000000007d745fff: RAM
|
|
[DEBUG] 4. 000000007d746000-000000007d78afff: CONFIGURATION TABLES
|
|
[DEBUG] 5. 000000007d78b000-000000007d7cefff: RAMSTAGE
|
|
[DEBUG] 6. 000000007d7cf000-000000007d7fffff: CONFIGURATION TABLES
|
|
[DEBUG] 7. 000000007d800000-000000007fffffff: RESERVED
|
|
[DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED
|
|
[DEBUG] 9. 0000000100000000-000000017fffffff: RAM
|
|
[INFO ] Manufacturer: c2
|
|
[INFO ] SF: Detected c2 2017 with sector size 0x1000, total 0x800000
|
|
[DEBUG] Wrote coreboot table at: 0x7d772000, 0x364 bytes, checksum c840
|
|
[DEBUG] coreboot table: 892 bytes.
|
|
[DEBUG] IMD ROOT 0. 0x7d7ff000 0x00001000
|
|
[DEBUG] IMD SMALL 1. 0x7d7fe000 0x00001000
|
|
[DEBUG] CONSOLE 2. 0x7d7de000 0x00020000
|
|
[DEBUG] RO MCACHE 3. 0x7d7dd000 0x00000364
|
|
[DEBUG] TIME STAMP 4. 0x7d7dc000 0x00000910
|
|
[DEBUG] AFTER CAR 5. 0x7d7cf000 0x0000d000
|
|
[DEBUG] RAMSTAGE 6. 0x7d78a000 0x00045000
|
|
[DEBUG] SMM BACKUP 7. 0x7d77a000 0x00010000
|
|
[DEBUG] COREBOOT 8. 0x7d772000 0x00008000
|
|
[DEBUG] ACPI 9. 0x7d74e000 0x00024000
|
|
[DEBUG] SMBIOS 10. 0x7d746000 0x00008000
|
|
[DEBUG] IMD small region:
|
|
[DEBUG] IMD ROOT 0. 0x7d7fec00 0x00000400
|
|
[DEBUG] FMAP 1. 0x7d7feb40 0x000000b6
|
|
[DEBUG] ROMSTAGE 2. 0x7d7feb20 0x00000004
|
|
[DEBUG] ROMSTG STCK 3. 0x7d7fea80 0x00000088
|
|
[DEBUG] ACPI GNVS 4. 0x7d7fe980 0x00000100
|
|
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 26 / 0 ms
|
|
[INFO ] CBFS: Found 'fallback/payload' @0x466c0 size 0x11880 in mcache @0x7d7dd270
|
|
[DEBUG] Checking segment from ROM address 0xffe468ec
|
|
[DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable.
|
|
[DEBUG] Checking segment from ROM address 0xffe46908
|
|
[DEBUG] Loading segment from ROM address 0xffe468ec
|
|
[DEBUG] code (compression=1)
|
|
[DEBUG] New segment dstaddr 0x000dedc0 memsize 0x21240 srcaddr 0xffe46924 filesize 0x11848
|
|
[DEBUG] Loading Segment: addr: 0x000dedc0 memsz: 0x0000000000021240 filesz: 0x0000000000011848
|
|
[DEBUG] using LZMA
|
|
[DEBUG] Loading segment from ROM address 0xffe46908
|
|
[DEBUG] Entry Point 0x000fd25b
|
|
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 31 / 0 ms
|
|
[DEBUG] ICH-NM10-PCH: watchdog disabled
|
|
[DEBUG] Jumping to boot code at 0x000fd25b(0x7d772000)
|
|
SeaBIOS (version rel-1.16.1-0-g3208b09)
|
|
BUILD: gcc: (coreboot toolchain v2022-12-18_3b32af950d) 11.2.0 binutils: (GNU Binutils) 2.37
|
|
Found coreboot cbmem console @ 7d7de000
|
|
Found mainboard LENOVO ThinkPad X200
|
|
Relocating init from 0x000e0520 to 0x7c738aa0 (size 54464)
|
|
Found CBFS header at 0xffe0022c
|
|
multiboot: eax=7d7bfa1c, ebx=7d7bf9e4
|
|
Found 22 PCI devices (max PCI bus is 0d)
|
|
Copying SMBIOS from 0x7d746000 to 0x000f67c0
|
|
Copying SMBIOS 3.0 from 0x7d746020 to 0x000f67a0
|
|
Copying ACPI RSDP from 0x7d74e000 to 0x000f6770
|
|
table(50434146)=0x7d751d30 (via xsdt)
|
|
Using pmtimer, ioport 0x508
|
|
Scan for VGA option rom
|
|
Running option rom at c000:0003
|
|
pmm call arg1=0
|
|
Turning on vga text mode console
|
|
SeaBIOS (version rel-1.16.1-0-g3208b09)
|
|
Machine UUID HIDDEN_BY_USER
|
|
EHCI init on dev 00:1a.7 (regs=0x90e26020)
|
|
EHCI init on dev 00:1d.7 (regs=0x90e27020)
|
|
UHCI init on dev 00:1a.0 (io=1020)
|
|
UHCI init on dev 00:1a.1 (io=1040)
|
|
UHCI init on dev 00:1a.2 (io=1060)
|
|
UHCI init on dev 00:1d.0 (io=1080)
|
|
UHCI init on dev 00:1d.1 (io=10a0)
|
|
UHCI init on dev 00:1d.2 (io=10c0)
|
|
AHCI controller at 00:1f.2, iobase 0x90e25000, irq 11
|
|
Searching bootorder for: HALT
|
|
Found 0 lpt ports
|
|
Found 0 serial ports
|
|
Discarding ps2 data aa (status=11)
|
|
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
AHCI/0: Set transfer mode to UDMA-6
|
|
Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
|
|
AHCI/0: registering: "AHCI/0: CT1000MX500SSD1 ATA-10 Hard-Disk (931 GiBytes)"
|
|
PS2 keyboard initialized
|
|
All threads complete.
|
|
Scan for option roms
|
|
|
|
Press ESC for boot menu.
|
|
|
|
Searching bootorder for: HALT
|
|
drive 0x000f6700: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
|
|
Space available for UMB: c7000-ec000, f5fe0-f6700
|
|
Returned 16769024 bytes of ZoneHigh
|
|
e820 map has 7 items:
|
|
0: 0000000000000000 - 000000000009fc00 = 1 RAM
|
|
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
|
|
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
|
|
3: 0000000000100000 - 000000007d744000 = 1 RAM
|
|
4: 000000007d744000 - 0000000080000000 = 2 RESERVED
|
|
5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
|
|
6: 0000000100000000 - 0000000180000000 = 1 RAM
|
|
enter handle_19:
|
|
NULL
|
|
Booting from Hard Disk...
|
|
Booting from 0000:7c00
|