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Bug #256 » coreboot-4.9-wakeup.log

Stefan Ott, 03/19/2020 05:59 PM

 

coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting...
Intel ME early init
Intel ME firmware is ready


coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 postcar starting...


coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 ramstage starting...
Enumerating buses...
PCI: Static device PCI: 00:16.2 not found, disabling it.
Enabling Common Clock Configuration
ASPM: Enabled L1
Failed to enable LTR for dev = PCI: 05:00.0
PMH7: ID 04 Revision 01
EC Firmware ID 6QHT34WW-3.18, Version 5.01B
H8: BDC not installed
H8: WWAN detection not implemented. Assuming WWAN installed
done
Manufacturer: c2
SF: Detected MX25L6405D with sector size 0x1000, total 0x800000
Allocating resources...
Reading resources...
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
Done reading resources.
skipping PNP: 164e.3@29 fixed resource, size=0!
skipping PNP: 164e.3@f0 fixed resource, size=0!
skipping PNP: 00ff.2@60 fixed resource, size=0!
skipping PNP: 00ff.2@62 fixed resource, size=0!
skipping PNP: 00ff.2@64 fixed resource, size=0!
skipping PNP: 00ff.2@66 fixed resource, size=0!
Setting resources...
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
Done setting resources.
Done allocating resources.
Enabling resources...
done.
Found TPM ST33ZP24 by ST Microelectronics
TPM: Handle S3 resume.
TPM: Resume failed (0x9).
Initializing devices...
Initializing CPU #0
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [720000:800000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 10100 size 2c00
CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz.
CPU:lapic=0, boot_cpu=1
Setting up local APIC...done.
Turbo is available and visible
Initializing CPU #1
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [720000:800000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 10100 size 2c00
CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz.
CPU:lapic=1, boot_cpu=0
Setting up local APIC...done.
CPU #1 initialized
Initializing CPU #2
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [720000:800000)
Initializing CPU #3
CBFS: Locating 'cpu_microcode_blob.bin'
CPU #0 initialized
Waiting for 2 CPUS to stop
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [720000:800000)
CBFS: Found @ offset 10100 size 2c00
CBFS: Locating 'cpu_microcode_blob.bin'
CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz.
CBFS: Found @ offset 10100 size 2c00
CPU:lapic=4, boot_cpu=0
CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz.
Setting up local APIC...CPU:lapic=5, boot_cpu=0
done.
CPU #2 initialized
Waiting for 1 CPUS to stop
Setting up local APIC...done.
CPU #3 initialized
GT init timeout
GT init timeout
ME: BIOS path: S3 Wake
Set power off after power failure.
NMI sources disabled.
Devices initialized
Finalize devices...
Devices finalized

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